CN1271506C - Circuit and method for realizing RSA enciphering algorithm - Google Patents

Circuit and method for realizing RSA enciphering algorithm Download PDF

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Publication number
CN1271506C
CN1271506C CN 01107654 CN01107654A CN1271506C CN 1271506 C CN1271506 C CN 1271506C CN 01107654 CN01107654 CN 01107654 CN 01107654 A CN01107654 A CN 01107654A CN 1271506 C CN1271506 C CN 1271506C
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calculation unit
output
mould
result
port multiplier
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CN1375764A (en
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周玉洁
金松
刘英广
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Nationz Technologies Inc
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ZHONGXING INTEGRATED CIRCUIT DESIGN CO Ltd SHENZHEN CITY
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Abstract

The present invention relates to a circuit and a method for realizing an RSA enciphering algorithm. The length of a binary number of a module is n; an initial precalculating circuit of the circuit is formed by connecting n+1 precalculating units; each precalculating unit comprises a trigger D, a full adder FA, a phase inverter N, a front multiplexer and a back multiplexer; an enable signal of a former multiplexer group which is used for selecting precalculation and result normadization is En; after module multiply calculation is completed, the signal En is high; the process of the result normalization is completed. An enable signal Sel of a latter multiplexer group which is used for selecting signal output is a control signal which is produced according to carry. In the present invention, a processing circuit for precalculation and result normalization is integrated in a chip, so convenience is brought to users and the calculation speed is raised.

Description

The realization circuit and the method for RSA cryptographic algorithms
Technical field the present invention relates to the hardware of computing method and realizes the field, relate in particular in the RSA cryptographic algorithms that big digital-to-analogue is taken advantage of, the hardware of Montgomery Algorithm is realized, relate to specifically realize adopting the Montgomery modular multiplication to finish the hardware circuit of large module power multiplication by integrated circuit.
Background technology is along with the development of mechanics of communication, the transmission of Information amount is increasing, the safety problem of information is also more and more important, and especially at commercial field, the security of information transmission, integrality and non repudiation directly have influence on the operating mode and the economic interests of businessman.In the information age, the INTERNET networks development of high-speed computer and globalization, the people that make different regions, the world are exchange message mutually, and the legitimacy of message reference seems and becomes more and more important.Growing various information encryptions, decryption technology adapted to the requirement in epoch, and good cryptographic algorithm makes information transmission more reliable, safer, and wherein public key encryption algorithm can better satisfy user's requirement.Up to the present, RSA cryptographic algorithms is most popular public key algorithm, can be used as to encrypt and digital signature.
RSA cryptographic algorithms is by R.L.Riverst, the algorithm that A.Shamir, and L.Adleman propose, name with three names.In using the system of this cryptographic algorithm, corresponding three very big bigit M, e and d are generally 512 or 1024, difficult more the cracking of number big more institute information encrypted for each user.Between these three bigits special relation is arranged, wherein M and e are disclosed, and d maintains secrecy, and are preserved by the user, and M is a modulus, and e is an encryption key, and d is a decruption key.When certain user sends information C, utilize encryption key e that should the user, information C is encrypted be sent to this user again, C be a plaintext here, and E is a ciphertext, and ciphering process can be expressed as: E=C eMod M; After the user receives cipher-text information E, use and to recover cleartext information C:C=E to its deciphering decruption key d that should the user dMod M.
As seen adopt RSA Algorithm all must carry out large module power multiplication to information encryption and deciphering, well-known Montgomery Algorithm can be decomposed into repeatedly modular multiplication, and establishing the big number that encryption and decryption relates to is C, A, e, and mould is M, that is:
C=A eMod M=(the mod M modular multiplication of A * A * Λ * A) can adopt montgomery modulo multiplication operation method hardware to realize, its calculating of finishing note do Mont (A, A, M).
If the length of the binary number of mould M is the n position, montgomery modulo multiplication just needs through n+1 wheel interative computation, and establishing its operation result of finishing is P, then:
P=Mont (A, A, M)=A * A * 2 -(n+1)Through behind the n+1 wheel Montgomery modular multiplication, the gained result takes advantage of the factor 2 of Duoing than mould to mod M as can be known -(n+1), need construct Montgomery modular multiplication T thus:
T=Mont (P, PP, M)=A * A mod M PP=2 wherein 2n+2Mod M has so finished the required large module power multiplication of encryption and decryption.Wherein the computing of PP is the initial precomputation when adopting the Montgomery modular multiplication algorithm.U.S. Pat 6,061,706 disclose a kind of montgomery modulo multiplication hardware circuit, its initial precomputation PP=2 in this circuit 2n+2Mod M is finished by the user, has brought inconvenience to the user, and adopts software to realize this computing by the user, and it is fast that speed does not have hardware to realize.
After mould took advantage of calculating to finish, its possibility of result was bigger than mould, the modulo operation that therefore must try again, realization result's normalized.
Initial precomputation and the realization circuit and the method for normalized as a result when summary of the invention the objective of the invention is to propose in a kind of RSA cryptographic algorithms to adopt the Montgomery modular multiplication to realize big digital-to-analogue power, modular multiplication.
Realize the Montgomery modular multiplication realization circuit of a kind of large module power multiplication of the object of the invention, its large module power multiplication adopts the Montgomery modular multiplication, the binary number length of mould is n, its initial precomputation circuit is formed by connecting by n+1 pre-calculation unit, the pre-calculation unit that is in precomputation chain most significant digit n comprises trigger D and full adder FA, the result of calculation R[n-1 of a low pre-calculation unit] input trigger D, through writing behind the clock, the carry output Br[n-1 of the output of trigger D and numerical value 1 and a low pre-calculation unit] as operand input full adder FA, produce carry output Br[n at the corresponding levels];
The pre-calculation unit that is in the non-most significant digit i of precomputation chain comprises trigger D, full adder FA, phase inverter N, and former and later two Port Multipliers (101 and 102), wherein i equals 0,1, n-1, the result of calculation R[i-1 of a low pre-calculation unit] and mould power counting circuit pattern under the mould that obtains take advantage of knot PV[i] import previous stage Port Multiplier (101); The value M[i of the binary number i position of mould M] behind phase inverter N and the carry output Br[i-1 of the output of previous stage Port Multiplier (101) and a low pre-calculation unit] import full adder FA respectively simultaneously, full adder FA produces carry output Br[i at the corresponding levels], the output of previous stage Port Multiplier (101) and the result of full adder FA output is input back one-level Port Multiplier (102) respectively, and back one-level Port Multiplier (102) output precomputation is R[i as a result];
Described pre-calculation unit is formed described precomputation chain, the result of calculation R[i of a low pre-calculation unit] the trigger D of the last pre-calculation unit of input, the carry output Br[i of a low pre-calculation unit] the full adder FA of the last pre-calculation unit of input, the trigger D of lowest order pre-calculation unit is input as 0, the carry output Br[i of the low pre-calculation unit output of the correspondence of full adder FA] be input as 1, being used to select the enable signal of modular multiplication and the normalized previous stage Port Multiplier of result (101) group is En, and the enable signal Sel that is used for back one-level Port Multiplier (102) group that signal output selects is the carry output Br[i according to each full adder] control signal that produces;
The generation circuit of the enable signal Sel of described back one-level Port Multiplier (102) group is a Port Multiplier (103), each full-adder carry-out Br[n], Br[n-1], Br[n-2] ..., Br[1], Br[0] import described Port Multiplier (103), the output of this Port Multiplier is with from the Ctrl signal of operation core control circuit mutually or produce control signal Sel, described Ctrl signal the first time time clock to write fashionable be 1.Promptly moving to left for the first time one the time, is later on 0; The value of the enable signal ML of described Port Multiplier (103) is that the binary data length of mould subtracts 1.
Realize the Montgomery modular multiplication implementation method of a kind of large module power multiplication of the object of the invention, its large module power multiplication adopts the Montgomery modular multiplication, the binary number length of mould is n, and its initial precomputation realizes in the link that multistage pre-calculation unit is formed by connecting, and may further comprise the steps:
1. calculate 2 nMod M
2. move to left one and write register, do modulo operation again;
3. 2. repeating step is total to n+2 time.
The present invention has following advantage: with precomputation and as a result the normalized circuit be integrated in the chip, need not the user and import the precomputation data, make things convenient for the user, improve arithmetic speed; Precomputation and as a result normalized adopt same circuit, reduce circuit area, reduce design complexities, reduce cost.
Description of drawings is described in further detail the present invention below in conjunction with accompanying drawing:
Figure 1A is the pre-calculation unit circuit diagram that is in precomputation chain most significant digit;
Figure 1B is the pre-calculation unit circuit diagram of non-precomputation chain most significant digit;
Fig. 2 produces the circuit diagram of selecting signal Sel;
Fig. 3 is a precomputation chain circuit structural representation;
Fig. 4 is that chain length is 4 precomputation circuit diagram.
Embodiment is at precomputation PP=2 2n+2Index 2n+2 is the iterations of twice montgomery modulo multiplication among the mod M, is write following formula as following form:
PP＝(2 n×2×Λ×2)mod?M＝(Λ((2 n?mod?M)×2?mod?M)Λ×2)mod?M
Wherein ... represent n (* 2 mod M) computing.
So the calculating process of PP can be decomposed into:
1. calculate 2 nMod M
2. move to left one and write register, do modulo operation again;
3. repeating step 2 is n+2 time altogether.
Because binary number 2 nLength is the n+1 position, and most significant digit is 1, and other position is 0; Mould M is taken as odd number, and length is the n position, and promptly the most significant digit of M and lowest order are 1; Then the length of 2M is the n+1 position, and most significant digit is 1 with time two of low levels at least, so have:
2M＞2 n＞M is then: 2 nMod M=2 nThis binary arithmetic of-M can obtain by zero complement addition with subtrahend:
0+M MendM wherein Mend=M+1
This result moved to left one promptly to finish multiply by 2 computing, ask mould output again after writing register, promptly finish computing
2 N+1Mod M and then move to left one and write register then asks mould output, i.e. computing again
2 n+2?mod?M
Finish through after n the computing so again:
2 2n+2?mod?M
Two kinds of circuit of Figure 1A and Figure 1B are two kinds of processing units in the precomputation chain.Circuit shown in Figure 1A is used for the most significant digit of precomputation chain, and the D among the figure represents d type flip flop, and FA represents full adder, and Br is the carry output of full adder, and R is the result of calculation of processing unit.The operation of this circuit is such: the result of calculation R[n-1 of next stage] the input d type flip flop, through writing d type flip flop behind the clock; The carry output Br[n-1 of the output of d type flip flop and numerical value 1 and next stage full adder] as operand input full adder FA, Br[n] be the carry output that produces at the corresponding levels, be used to produce the control signal of selecting precomputation chain output result.Circuit shown in Figure 1B is used for the non-most significant digit i position of precomputation chain, its circuit manys two Port Multipliers 101 and 102 than Figure 1A, and PV is that mould is taken advantage of the result, M[i] be the value of the binary number i position of mould M, previous stage Port Multiplier 101 is used for the signal input to be selected, and selects precomputation and modular multiplication; Back one-level Port Multiplier 102 is used for signal output to be selected, and the enable signal of this Port Multiplier 102 produces according to carry, if carry digit is 1, result data (in register D) is described greater than mould value M, and at this moment output data will cut mould M; If carry digit is 0, result data is described less than mould value M, output data can directly be exported.The operation of Figure 1B is identical with Figure 1A.
Shown in Figure 2 is a Port Multiplier, is used to select result of calculation.Enabling of this Port Multiplier is the long ML of mould, and the value of ML is that the binary data length of mould subtracts 1, is 1011 as mould, and then ML is 3.The output carry Br[i of each full adder in the precomputation chain] the input Port Multiplier, the output of Port Multiplier is with Ctrl signal phase or controlled signal Sel, the Ctrl signal is from the control circuit of operation core, the first time time clock write and fashionablely be 1 (promptly move to left for the first time one time), be later on 0.
Fig. 3 is a precomputation chain circuit structural representation, is made up of two kinds of pre-calculation unit shown in Figure 1A and Figure 1B.The length of precomputation chain determines according to the length of mould M: if the length of mould M is n, then need n+1 pre-calculation unit, mould M[i] through behind one group of reverser, it each transfers to a corresponding operand input end that calculates the chain element full adder respectively, in most significant digit input " 1 "; Output data and the mould of d type flip flop group Di are taken advantage of result data PV[i] import each Port Multiplier Si, Port Multiplier S jointly N-1Λ S 1S 0Gating signal En, select mould to take advantage of PV[n-1 as a result], PV[n-2] ..., PV[1], PV[0] and " 0 " of lowest order import corresponding full adder respectively.Port Multiplier group Sel N-1Λ Sel 1Sel 0Output import the d type flip flop of a pre-calculation unit respectively, each like this when writing d type flip flop, the precomputation end value moves to left one.After modular multiplication was finished, signal En was high, and mould is taken advantage of PV[n-1 as a result], PV[n-2] ..., PV[1], PV[0] through Port Multiplier group S N+1Λ S 1S 0Be passed to full adder, its result is less than 2M, but may be greater than M, if export after will taking advantage of the result to ask mould to mould greater than M, if less than then directly output of M, so finish normalization process as a result.
Fig. 4 is that mould takes advantage of is 3 precomputation chain circuit synoptic diagram, the pre-calculation unit of lowest order among the figure, and because of in the process of moving to right, lowest order is 0, so d type flip flop can save.Derivation according to the front, this precomputation chain has 4 pre-calculation unit, the output of each is the upwards input of one d type flip flop even, data PV[2], PV[1], PV[0] be the output that mould is taken advantage of the result, mould M finishes in full adder and data R[2 with complement form input], R[1], R[0] subtraction.Suppose that mould M equals 5, then n is 3, promptly calculates
2 2 * 3+ 2 mod 5 at first calculate the first step
(2 3Mod 5) * 2 with the d type flip flop zero clearing, computing 0+M Mend, the output result that at this moment will get full adder, it is 1 that control signal Ctrl makes Sel, behind a clock, the output result of precomputation chain moves to left one and write d type flip flop group D respectively 2D 1D 0Next calculate
(((2 3Mod 5) * 2) mod 5) * 2 at this moment Ctrl be 0, do not participate in control, signal Sel and Br[3] equivalence, calculate mod5, again through behind the clock, the result is moved to left one writes d type flip flop group D 2D 1D 0So repeatedly, finish computing behind 3 clocks.
R＝2 2n+2?mod?M
After modular multiplication finished, everybody of its binary result was PV[2], PV[1], PV[0], this value may be greater than M, and less than 2M, need be worth delivery to this like this, the post-processing function of this circuit is just finished the modulo operation that mould is taken advantage of the result.After mould was taken advantage of end, input Port Multiplier enable signal EN was 1, and the gating mould is taken advantage of PV[2 as a result], PV[1], PV[0] export and make PV＜M.

Claims (6)

1. the realization circuit of a RSA cryptographic algorithms, its large module power multiplication adopts the Montgomery modular multiplication, the binary number length of mould is n, it is characterized in that: its initial precomputation circuit is formed by connecting by n+1 pre-calculation unit, the pre-calculation unit that is in precomputation chain most significant digit n comprises trigger D and full adder FA, the result of calculation R[n-1 of a low pre-calculation unit] input trigger D, through writing behind the clock, the carry output Br[n-1 of the output of trigger D and numerical value 1 and a low pre-calculation unit] as operand input full adder FA, produce carry output Br[n at the corresponding levels];
The pre-calculation unit that is in the non-most significant digit i of precomputation chain comprises trigger D, full adder FA, phase inverter N, and former and later two Port Multipliers (101 and 102), wherein i equals 0,1, n-1, the result of calculation R[i-1 of a low pre-calculation unit] and mould power counting circuit pattern under the mould that obtains take advantage of PV[i as a result] import previous stage Port Multiplier (101); The value M[i of the binary number i position of mould M] behind phase inverter N and the carry output Br[i-1 of the output of previous stage Port Multiplier (101) and a low pre-calculation unit] import full adder FA respectively simultaneously, full adder FA produces carry output Br[i at the corresponding levels], the output of previous stage Port Multiplier (101) and the result of full adder FA output is input back one-level Port Multiplier (102) respectively, and back one-level Port Multiplier (102) output precomputation is R[i as a result];
Described pre-calculation unit is formed described precomputation chain, the result of calculation R[i of a low pre-calculation unit] the trigger D of the last pre-calculation unit of input, the carry output Br[i of a low pre-calculation unit] the full adder FA of the last pre-calculation unit of input, the trigger D of lowest order pre-calculation unit is input as 0, the carry output Br[i of the low pre-calculation unit output of the correspondence of full adder FA] be input as 1, being used to select the enable signal of modular multiplication and the normalized previous stage Port Multiplier of result (101) group is En, and the enable signal Sel that is used for back one-level Port Multiplier (102) group that signal output selects is the carry output Br[i according to each full adder] control signal that produces;
The generation circuit of the enable signal Sel of described back one-level Port Multiplier (102) group is a Port Multiplier (103), each full-adder carry-out Br[n], Br[n-1], Br[n-2] ..., Br[1], Br[0] import described Port Multiplier (103), the output of this Port Multiplier is with Ctrl signal phase or generation control signal Sel from the operation core control circuit, described Ctrl signal the first time time clock to write fashionable be 1, promptly moving to left for the first time one the time, is later on 0; The value of the enable signal ML of described Port Multiplier (103) is that the binary data length of mould subtracts 1.
2. the realization circuit of RSA cryptographic algorithms according to claim 1 is characterized in that the trigger D of the lowest order pre-calculation unit of described precomputation chain can not want.
3. the realization circuit of RSA cryptographic algorithms according to claim 1 is characterized in that described precomputation chain can independently realize in the integrated circuit block at one.
4. the implementation method of a RSA cryptographic algorithms, its large module power multiplication adopts Montgomery modular multiplication, and the binary number length of mould is n, it is characterized in that its initial precomputation realizes in the link that multistage pre-calculation unit is formed by connecting, and may further comprise the steps:
1. calculate 2nmodM;
2. move to left one and write register, do modulo operation again;
3. 2. repeating step is total to n+2 time.
5. the implementation method of RSA cryptographic algorithms according to claim 4 is characterized in that 1. its step realizes by zero complement addition with modulus M.
6. the implementation method of RSA cryptographic algorithms according to claim 4 is characterized in that after modular multiplication is finished, and enable signal En is set for high, and mould is taken advantage of PV[n-1 as a result], PV[n-2] ..., PV[1], PV[0] pass through Port Multiplier group S respectively N-1Λ S 1S 0Be passed to corresponding full adder FAi, if export after mould takes advantage of the result then to take advantage of the result to ask mould to mould greater than M, otherwise directly output.
CN 01107654 2001-03-19 2001-03-19 Circuit and method for realizing RSA enciphering algorithm Expired - Fee Related CN1271506C (en)

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Publication number Priority date Publication date Assignee Title
US20060059219A1 (en) * 2004-09-16 2006-03-16 Koshy Kamal J Method and apparatus for performing modular exponentiations
US8090957B2 (en) * 2005-10-19 2012-01-03 Panasonic Corporation Information security device, information security method, computer program, computer-readable recording medium, and integrated circuit
CN101169776B (en) * 2006-10-27 2012-01-25 松下电器产业株式会社 Data encryption method and device for promoting central processing unit operation efficiency
CN101196964B (en) * 2006-12-07 2010-08-11 上海爱信诺航芯电子科技有限公司 Anti-bypass attack algorithm chip
CN102646033B (en) * 2011-02-21 2015-08-19 中国科学院信息工程研究所 Provide implementation method and the device of the RSA Algorithm of encryption and signature function
CN103699351B (en) * 2013-12-05 2016-06-29 西安交通大学 One is decaptitated the shift circuit that truncates
CN103729163B (en) * 2013-12-05 2017-01-04 西安交通大学 One is left out the beginning and the end and is shifted benefit value circuit
WO2024036429A1 (en) * 2022-08-15 2024-02-22 Intel Corporation Paillier cryptosystem with improved performance

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