CN113032845A - EdDSA signature implementation method and device for resource-constrained chip - Google Patents
EdDSA signature implementation method and device for resource-constrained chip Download PDFInfo
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Abstract
The invention provides an EdDSA signature realization method and device for a resource-constrained chip, wherein the EdDSA signature realization method comprises the steps of S1, generating a random number k, a random number x and a public key A by using a private key d; s2, generating a digital signature (R, S) of the information M to be signed according to the random number k, the random number x and the public key A, wherein R = [ R ] G represents R times of the point G, and the generation is realized by point addition operation accumulation; r = H (k, M), s = (R + H (R, a, M) x) modL, L being the order of the base point G; in the point addition operation process, calculating the horizontal and vertical coordinates of each point by adopting modulo p multiplication operation; in the modulo-p multiplication operation, when the digit of a modulus p and two multipliers is less than a preset digit, bit complementing operation is carried out; when the digit numbers of the modulus p and the two multipliers are equal to the preset digit number, judging whether the highest bit of the modulus p is 1, if not, shifting the modulus p to the left by n bits until the highest bit is 1, shifting one multiplier to the left by n bits, then obtaining a middle value T by the modular multiplication operation of calculating the two shifted multipliers by using a Barrett algorithm, and shifting the middle value T to the right by n bits to obtain a final result.
Description
Technical Field
The invention relates to the technical field of information security, in particular to a method and a device for realizing EdDSA signature of a resource-limited chip.
Background
Elliptic Curve Cryptography (ECC) is designed based on elliptic curves in the discrete logarithm problem. The current ECC algorithm is often used to replace the RSA algorithm to improve the security and performance of the original algorithm. Compared with RSA, ECC has higher performance and shorter key length, but the implementation difficulty is higher. The digital signature algorithm constructed on the basis of the ECC algorithm is called ECDSA algorithm, and the curve approved by NIST has a plurality of curves, such as secp256r1, secp256k1 and the like. But the curve in the existing ECC algorithm is indicated to be the presence of a back door.
EdDSA also belongs to elliptic curve cryptography in a sense that it uses a distorted edwards curve as an elliptic curve, and a signature mechanism is also different from the ECDSA algorithm. The important realization ED25519 of EdDSA is an EdDSA algorithm designed by Daniel J.Bernstein et al, adopts completely disclosed curve parameters, explains the significance of parameter selection, and ensures that a back door is not built in a curve. Meanwhile, the ED25519 adopts a Schnorr mechanism as a signature construction mode, so that the signature and verification performance is greatly improved.
However, the operation of the random point R in the EdDSA signature process is the most time-consuming point multiplication operation, and consists of a large number of point operations, all of which are modulo-p large number operations, and the security chip hardware adopts the Barrett algorithm to realize the modulo-multiplication operation of two 256-bit integers, so that in order to save area and improve performance, the modulus must be the 256-bit integer and the highest bit must be 1, and if the highest bit is not 1, the operation is incorrect. In addition, the method has no problem in realizing 256-bit large digital-analog multiplication operation, but cannot be used if the modular multiplication is less than 256 bits.
Therefore, how to design an EdDSA signature implementation method for a resource-limited chip is a problem that needs to be solved urgently at present, so that the correctness of the operation can be ensured even if the most significant bit of the modulus is not 1 under the condition that the chip resources are limited.
Disclosure of Invention
In view of the above problems, the present invention needs to provide an EdDSA signature implementation method for a resource-limited chip, which can ensure the correctness of operations even if the most significant bit of a modulus is not 1 under the condition that the chip resources are limited.
The first aspect of the present invention provides a modulo p multiplication operation for a resource-constrained chip, including:
the method comprises two multipliers and a modulus p, wherein p is a finite field characteristic;
when the digit of the modulus p and the two multipliers is not equal to the preset digit, adjusting the digit of the modulus p and the two multipliers to the preset digit by high-order zero padding; when the digit numbers of the modulus p and the two multipliers are equal to the preset digit number, judging whether the highest bit of the modulus p is 1, if not, shifting the modulus p to the left by n bits until the highest bit is 1, shifting one multiplier to the left by n bits, then obtaining a middle value T by the modular multiplication operation of calculating the two shifted multipliers by using a Barrett algorithm, and shifting the middle value T to the right by n bits to obtain a final result.
The second aspect of the present invention provides an EdDSA signature implementation method for a resource-constrained chip, including:
s1, Key Generation
Carrying out Hash calculation on the private key d to generate a value h (H) (d) with the length of 2b, wherein b is the length of the secret key, and h is the length of the secret key0…hb-1Is a random number x for generating a public key hb…h2b-1Is a random number k used for calculating a signature;
calculating a public key A ═ x ] G according to the random number x, wherein G is a base point of the elliptic curve;
s2, signature generation
Generating a digital signature (R, s) of the information M to be signed according to the random number k, the random number x and the public key A, wherein R ═ R ] G represents a point R times of the point G and is realized by point addition operation accumulation; r ═ H (k, M), s ═ R + H (R, a, M) x) modL, L is the order of the base point G;
in the point addition operation process, the horizontal and vertical coordinates of each point are calculated by adopting the modulo p multiplication operation.
The third aspect of the present invention further provides an EdDSA signature implementing apparatus for a resource-constrained chip, including:
a key generation module, configured to perform hash calculation on the private key d to generate a value h (h) (d) with a length of 2b, where b is the key length, and h is the key length0…hb-1Is a random number x for generating a public key hb…h2b-1Is a random number k used for calculating a signature; and for calculating a public key a ═ x from the random number x]G and G are base points of the elliptic curve;
the signature generation module is used for generating a digital signature (R, s) of the information M to be signed according to the random number k, the random number x and the public key A, wherein R ═ R ] G represents an R-time point of the point G and is realized by point addition operation accumulation; r ═ H (k, M), s ═ R + H (R, a, M) x) modL, L is the order of the base point G; in the dot addition operation process, the horizontal and vertical coordinates of each point are calculated by adopting the modulo p multiplication operation.
A fourth aspect of the present invention provides a resource-constrained chip, including: one or more FPGA processors; a storage device for storing one or more programs which, when executed by the one or more FPGA processors, cause the one or more FPGA processors to implement the aforementioned methods.
The invention has prominent substantive characteristics and remarkable progress, in particular to the following steps: the invention can use hardware safety chip to calculate a correct intermediate value when the multiplier is the same as the modulus digit but the maximum modulus digit is not 1, then process the intermediate value to obtain the final result, under the condition of limited chip resource, the operation correctness can be ensured even if the maximum digit is not 1.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow chart of a method for implementing EdDSA signatures for resource constrained chips;
fig. 2 is a schematic diagram of an EdDSA signature implementation apparatus for a resource-constrained chip.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It will be understood that when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Example 1
The present embodiment proposes a modulo-p multiplication operation for a resource-constrained chip, including:
the method comprises two multipliers and a modulus p, wherein p is a finite field characteristic;
when the digit of the modulus p and the two multipliers is not equal to the preset digit, adjusting the digit of the modulus p and the two multipliers to the preset digit by high-order zero padding; when the digit numbers of the modulus p and the two multipliers are equal to the preset digit number, judging whether the highest bit of the modulus p is 1, if not, shifting the modulus p to the left by n bits until the highest bit is 1, shifting one multiplier to the left by n bits, then obtaining a middle value T by the modular multiplication operation of calculating the two shifted multipliers by using a Barrett algorithm, and shifting the middle value T to the right by n bits to obtain a final result.
The invention can use hardware security chip to calculate a correct intermediate value when the multiplier is the same as the digit of the modulus but the high position of the maximum modulus is not 1, then process the intermediate value to obtain the final result, and can ensure the correctness of the operation even if the highest position of the modulus is not 1 under the condition of limited chip resources.
Example 2
As shown in fig. 1, the present embodiment provides an EdDSA signature implementation method for a resource-constrained chip, including:
s1, Key Generation
Carrying out Hash calculation on the private key d to generate a value h (H) (d) with the length of 2b, wherein b is the length of the secret key, and h is the length of the secret key0…hb-1Is a random number x for generating a public key hb…h2b-1Is a random number k used for calculating a signature;
calculating a public key A ═ x ] G according to the random number x, wherein G is a base point of the elliptic curve;
s2, signature generation
Generating a digital signature (R, s) of the information M to be signed according to the random number k, the random number x and the public key A, wherein R ═ R ] G represents a point R times of the point G and is realized by point addition operation accumulation; r ═ H (k, M), s ═ R + H (R, a, M) x) modL, L is the order of the base point G;
in the dot addition process, the modulo-p multiplication described in embodiment 1 is used to calculate the horizontal and vertical coordinates of each dot.
Specifically, in the large number operation of the modulus p, the number of bits of the two multipliers is less than or equal to the number of bits of the modulus p.
It should be noted that the Barrett algorithm used by the secure chip hardware FPGA to implement serial modular multiplication (calculate c ═ a × bmod p) is as follows:
inputting:
wherein
And (3) outputting: c is a bmxp
1) Calculating z as a.b;
2) computing
3) Computing
4) If c is more than or equal to p, c is c-p;
5) and (c) returning.
Some chip implementations are to save area and improve performance, requiring that the modulus p must be a 256-bit integer and the most significant bit must be 1.
Some security chip hardware adopts the Barrett algorithm to realize modular multiplication operation of two 256-bit integers, and in order to save area and improve performance, the module is required to be the 256-bit integer and the highest bit is required to be 1, and the operation is incorrect if the highest bit is not 1. The method realizes 256-bit large digital-analog multiplication operation without any problem, but cannot be used if the multiplication is less than 256-bit modular multiplication. Such as EdDSA signature algorithm (e.g., ED25519), implemented in firmware, and requires the use of the above-mentioned modular multiplication provided by hardware for algorithm acceleration. But the characteristic p of the finite field of the ED25519 adopting the edward signature mechanism and the order L of the elliptic curve group do not satisfy the condition that the highest bit of the modulus is 1, the present application provides a calculation method, which can calculate a correct intermediate value by using hardware when the highest bit of the modulus is not 1, and then process the intermediate value to obtain the final result.
Specifically, the EdDSA signature adopts an ED25519 algorithm, the key length b is 256 bits, and the private key d is a randomly acquired binary number with a length of b bits.
Specifically, the EdDSA signature implementation method further includes S3 signature verification: and verifying whether [ s ] G ═ R + H (R, A, M) A is true, if true, the signature verification passes, and otherwise, the signature verification fails.
In practical applications, R ═ R ] G is a dot product, i.e., R times the point G, and the dot product is finally combined by a dot addition, which is the most basic dot operation and is mod p;
and (3) dot addition operation:
(x3,y3)＝(x1,y1)+(x2,y2)
x3＝(x1*y2+x2*y1)/(1+d*x1*x2*y1*y2)mod p
y3＝(y1*y2–a*x1*x2)/(1–d*x1*x2*y1*y2)mod p
and (3) dot product operation:
[ r ] G represents a point r times (x, y) the point G, and is accumulated by the base point addition operation
When r is 2, (x2, y2) 2G (x1, y1) + (x1, y1)
x2＝(x1*y1+x1*y1)/(1+d*x1*x1*y1*y1)mod p
y2＝(y1*y1-a*x1*x1)/(1-d*x1*x1*y1*y1)mod p
When r is 3, (x3, y3) G +2G (x1, y1) + (x2, y2)
x3＝(x1*y2+x2*y1)/(1+d*x1*x2*y1*y2)mod p
y3＝(y1*y2-a*x1*x2)/(1-d*x1*x2*y1*y2)mod p
In the same way, 4G is 2G +2G
5G＝2G+3G
6G＝3G+3G
7G＝3G+4G。
Example 3
As shown in fig. 2, this embodiment further provides an EdDSA signature implementation apparatus for a resource-constrained chip, where the key generation module is configured to perform hash calculation on a private key d to generate a value h ═ h (d) with a length of 2b, where b is the key length, and h is the key length0…hb-1Is a random number x for generating a public key hb…h2b-1Is a random number k used for calculating a signature; and for calculating a public key a ═ x from the random number x]G and G are base points of the elliptic curve;
the signature generation module is used for generating a digital signature (R, s) of the information M to be signed according to the random number k, the random number x and the public key A, wherein R ═ R ] G represents an R-time point of the point G and is realized by point addition operation accumulation; r ═ H (k, M), s ═ R + H (R, a, M) x) modL, L is the order of the base point G; in the dot addition operation process, the horizontal and vertical coordinates of each point are calculated by adopting the modulo p multiplication operation.
Specifically, in the large number operation of the modulus p, the number of bits of the two multipliers is less than or equal to the number of bits of the modulus p.
Specifically, the EdDSA signature adopts an ED25519 algorithm, the key length b is 256 bits, and the private key d is a randomly acquired binary number with a length of b bits.
Specifically, in the calculation process of the point R, if the multiplier and the modulus are smaller than 256 bits, the number of bits is adjusted to 256 bits by high-order 0 compensation.
Specifically, the EdDSA signature realization device further includes a signature verification module, configured to verify whether [ s ] G ═ R + H (R, a, M) a is true, if true, the signature passes, and otherwise, the signature fails.
Example 4
The present embodiment provides a resource-constrained chip, including: one or more FPGA processors; a storage device for storing one or more programs which, when executed by the one or more FPGA processors, cause the one or more FPGA processors to implement the aforementioned methods.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A modulo-p multiplication operation for a resource constrained chip, characterized by:
the method comprises two multipliers and a modulus p, wherein p is a finite field characteristic;
when the digit of the modulus p and the two multipliers is not equal to the preset digit, adjusting the digit of the modulus p and the two multipliers to the preset digit by high-order zero padding; when the digit numbers of the modulus p and the two multipliers are equal to the preset digit number, judging whether the highest bit of the modulus p is 1, if not, shifting the modulus p to the left by n bits until the highest bit is 1, shifting one multiplier to the left by n bits, then obtaining a middle value T by the modular multiplication operation of calculating the two shifted multipliers by using a Barrett algorithm, and shifting the middle value T to the right by n bits to obtain a final result.
2. The EdDSA signature realization method of claim 1, wherein the modulo-p multiplication operation is performed with two multipliers having a number of bits equal to or less than the number of bits of the modulus p.
3. An EdDSA signature implementation method for a resource-constrained chip, comprising:
s1, Key Generation
Hashing the private key d to generate a value h = h (d) of length 2b, where b is the key length and h is0…hb−1Is a random number x for generating a public key hb…h2b−1Is a random number k used for calculating a signature;
calculating a public key A = [ x ] G according to the random number x, wherein G is a base point of an elliptic curve;
s2, signature generation
Generating a digital signature (R, s) of the information M to be signed according to the random number k, the random number x and the public key A, wherein R = [ R ] G represents R times of points G, and the generation is realized by point addition operation accumulation; r = H (k, M), s = (R + H (R, a, M) x) modL, L being the order of the base point G;
in the dot addition process, the abscissa and the ordinate of each point are calculated by the modulo p multiplication operation of any one of claims 1 to 2.
4. The EdDSA signature realization method of claim 3, wherein: the EdDSA signature adopts an ED25519 algorithm, the length b of the secret key is 256 bits, and the private key d is a binary number which is randomly acquired and has the length of b bits.
5. The EdDSA signature implementation method of claim 3, further comprising S3 signature verification: and verifying whether [ s ] G = R + H (R, A, M) A is true, if true, the signature passes, otherwise, the signature fails.
6. An EdDSA signature implementation apparatus for a resource-constrained chip, comprising:
a key generation module, configured to perform hash calculation on the private key d to generate a value h = h (d) with a length of 2b, where b is the key length, and h is the key length0…hb−1Is a random number x for generating a public key hb…h2b−1Is a random number k used for calculating a signature; and for calculating the public key A = [ x ] from the random number x]G and G are base points of the elliptic curve;
the signature generation module is used for generating a digital signature (R, s) of the information M to be signed according to the random number k, the random number x and the public key A, wherein R = [ R ] G represents an R-time point of the point G, and the generation is realized by point addition operation accumulation; r = H (k, M), s = (R + H (R, a, M) x) modL, L being the order of the base point G; in the dot addition operation process, the horizontal and vertical coordinates of each point are calculated by adopting the modulo p multiplication operation.
7. The EdDSA signature realization apparatus of claim 6, wherein the number of bits of the two multipliers in the large number operation of the modulus p is less than or equal to the number of bits of the modulus p.
8. The EdDSA signature realization apparatus of claim 6, wherein the EdDSA signature is implemented by using the ED25519 algorithm, the key length b is 256 bits, and the private key d is a randomly acquired binary number with a length of b bits.
9. The EdDSA signature realization apparatus of claim 6, further comprising a signature verification module for verifying whether [ s ] G = R + H (R, a, M) a is true, if true, the signature passes, otherwise the signature fails.
10. A resource-constrained chip, comprising:
one or more FPGA processors;
a storage device for storing one or more programs,
when executed by the one or more FPGA processors, cause the one or more FPGA processors to implement the method of any one of claims 3-5.
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