CN1369114A - Method of modifying integrated circuit - Google Patents
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
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Abstract
The invention provides a method of modifying an integrated circuit, the method including the steps of selecting a scaling factor (72), scaling the circuit (74) according to the scaling factor, and adjusting the circuit for functionality and design rule compliance (75-78). The method makes it possible to scale a circuit without losing functionality or destroying the hierarchy of the circuit.
Description
The present invention relates to a kind of method of revising integrated circuit, particularly by a series of equal proportion zoom operations.
The present invention especially but be not exclusively to relate to a kind of method can revise the physical Design (physical design) of integrated circuit or branch road or layout (layout) with the designs that are fit to different covers with make rule by this method.This method comprises that the data of analyzing existing integrated circuit are to determine scale factor, pass through the equal proportion scaled data according to process migration (process migration) technology with the order of regulation then, each layer of equal proportion convergent-divergent is adjusted shape edges and is changed original shape with exchanging geometry and unit.
Process migration is that a kind of integrated circuit (IC) design of revising makes them can produce and have the technology of different geometrical size and relation by new manufacture method.The manufacture method restriction that the physical size of integrated circuit is used.Limiting factor is the size of the smallest elements that can produce, and this size is approximately 0.13 micron at present.
Owing to design novel method, component size can be made forr a short time.Yet before the use new producing method can be constructed available circuit with less ratio, circuit layout must redesign.The overall planning of circuit can be similar to identical, but the different parts of circuit may be with different factor equal proportion convergent-divergents with element.The rule that has these critical dimensions of control.Constraints that some rules rely on to be made, the minimum feasible dimensions of Lian Jieing for example, other then depend on electronic factor such as electric capacity and resistance.
When redesign, but the computer check circuit meets these design rules.
Be transformed into a kind of new manufacture method and have various reasons, comprising:
1) speed: need and less signal distance less element because less electric charge shifts
Has switch transition faster.
2) size: along with each silicon wafer can be made more chip, unit cost has reduced.
3) commodity production: on a production line, can make more products, allow old, economy
The production line that benefit is low is closed.
Main problem is how to revise the physical Design of circuit.This is very difficult and complicated.
Another of redesign chip is former because present many circuit are by the parts or the element that use different manufacturers to provide, is called " system on a chip " element and designs.Yet different design rules be produced and be formed to these elements can by different manufacturers, needs redesign to make them can observe the design rule of identical cover.
Therefore the reason of redesign can comprise:
1) meets particular design-rule;
2) use up-to-date manufacture method; And
3) reduce size of component by certain factor.
The existing method of process migration is as follows:
Symbol migration (symbolic migration).In this method, technical specification as required forms each element again, such as each transistor.This method is not extremely successful, particularly for the circuit of complexity.
Compression.For example, as can be known, it provides a kind of method that redesigns layout from US 5640497.In the method, at first, make circuit become littler in that next pushes all sizes to the minimum dimension that design rule allows on the x direction on the y direction.This technology is success partly, and the circuit but it " has flattened ": promptly it has damaged the level of building block.This needs huge computing capability to go to finish, and because level is no longer consistent, makes modification subsequently very difficult.
The equal proportion convergent-divergent.The equal proportion convergent-divergent means with a constant factor and reduces each size of component.Although reduced component size, consequent circuit is normally inoperable, and this is owing to may destroy thousands of design rule.Therefore, although sometimes it is regarded as desirable solution, can not realize in the past.
One of purpose of the present invention is to provide a kind of method of equal proportion convergent-divergent integrated circuit, and it has alleviated at least some previous described problems.
According to the present invention, a kind of method of revising integrated circuit is provided, this method comprises the step of selecting the equal proportion zoom factor, meets the step of adjusting circuit according to the step of equal proportion zoom factor equal proportion convergent-divergent circuit with for functional with design rule.
This method makes the equal proportion convergent-divergent circuit possibility that becomes under the situation that does not lose functional or infringement circuit level.
Beneficially, the equal proportion zoom factor is to select by calculating a plurality of predetermined equal proportion zoom ratio and the equal proportion zoom factor of selecting to be equal to or greater than maximum predetermined equal proportion zoom ratio.This has just guaranteed that circuit is zoomed at utmost by equal proportion under the prerequisite of not violating basic design rule.Beneficially, predetermined equal proportion zoom factor comprises interconnected equal proportion zoom ratio, how much ratios of clear size of opening ratio and electronic component.
Beneficially, the equal proportion zoom factor is selected to next integral lattice point by be rounded up to (rounding up) from the predetermined equal proportion zoom ratio of maximum.This element that has just guaranteed circuit correctly is placed on the planning grid.
Beneficially, the step according to equal proportion zoom factor circuit equal proportion convergent-divergent circuit comprises the coordinate that multiply by circuit geometry by the equal proportion zoom factor.
Beneficially, adjust circuit functionality and make the step that meets design rule comprise level layer equal proportion convergent-divergent process.Level layer equal proportion convergent-divergent process can comprise the step according to the element in the predetermined layer equal proportion zoom factor equal proportion scaling layer.This can be by absolute equal proportion convergent-divergent (increase and reduce each component size with a fixed amount), perhaps realizes by relative equal proportion convergent-divergent (fixed percentage that multiply by an original size increase or reduce each component size).Level layer equal proportion convergent-divergent process can comprise equal proportion convergent-divergent element so that keep the step of the connectedness of these elements.Level layer equal proportion convergent-divergent process can comprise that identification satisfies the element of preset width standard, and only the equal proportion convergent-divergent does not satisfy the step of the element of those standards.Like this, power connector can exclude from equal proportion convergent-divergent process, to avoid problems of excessive heat.
Beneficially, adjusting circuit is used for step functional and that meet design rule and comprises transistor edge adjustment process.Transistor edge adjustment process can comprise the step of adjusting polysilicon layer width and/or diffusion layer length.This has just recovered to form the correct yardstick of transistorized element, with assurance function.
Beneficially, this method comprises the step of upgrading contact and through hole.Upgrade the contact and the step of through hole can comprise remove existing contact with through hole and with novel contact and the through hole replacement they, to reduce current density.
Beneficially, this method comprises the step that increases and/or delete layer, to adapt to the variation in the technology.
Beneficially, this method comprises the step of using layout verification process check circuit, to guarantee to meet design rule.
Beneficially, this method comprises the preliminary step of analyzing and revising circuit data, finishes the required time of transition process with minimizing.
Beneficially, this method comprises that the node that will comprise design parameter is increased to the step on the device in the circuit, therefore allows easily to visit the information about these devices.
Another object of the present invention is to provide a kind of different process migration technology, it can be described to " complicated equal proportion convergent-divergent ", and can be applied on the computer model of layout of any existing integrated circuit.By using this technology, the layout of chip can be changed into and produced with any new method and any ratio that satisfies new design rule.
This method can be applicable to flat chip layout and those and comprises the layout that designs level, level can be defined as being placed in subelement in the more senior circuit and these more senior circuit be placed again successively more senior in.By the original level of level coupling of migration chip.
According to a further aspect in the invention, provide a kind of method of equal proportion convergent-divergent integrated circuit, comprised and check that existing layout must be comprised and determine the variable-geometry value by the step of the amount of equal proportion convergent-divergent to determine layout; The absolute geometry value; And planning grid, and carry out one or more gate-width degree and length adjustment; Layer equal proportion convergent-divergent; Polygon edge is adjusted; Contact replaces; Adjust overlapping; Increase and the removal layer; Elements exchange; And checking.
By example with will more specifically describe a kind of embodiment of the present invention now with reference to the accompanying drawings, wherein:
Fig. 1 shows the circuit level, and wherein the building block of circuit is positioned in the bigger module, and big module can be positioned in the bigger module again;
Fig. 2 shows the variable rules example, and wherein geometry must be equal to and greater than the distance and the width of setting;
Fig. 3 shows fixedly geometry value example, and wherein geometric scale must equal definition value;
Fig. 4 shows interconnected interval;
Fig. 5 shows through hole geometry and array;
Fig. 6 a and 6b show the CMOS transistor geometry, and Fig. 6 c shows the interval of considering in lateral transistor;
Fig. 7 a and 7b show overall equal proportion convergent-divergent;
Fig. 8 shows the CMOS transistor and defines (definition) and the adjustment of transistor edge;
Fig. 9 shows the Darlington gate-width degree adjustment that is formed on single diffusion geometry;
Figure 10 shows layer and shrinks the destruction connectivity;
Figure 11 shows has internuncial level layer contraction;
Figure 12 shows the size of adjusting layer by geometric widths;
Figure 13 shows the adjustment of transistorized edge;
Figure 14 shows the element that uses contact and through hole connecting circuit;
Figure 15 shows the removal and the replacement of contact;
Figure 16 shows ply;
Figure 17 shows and is limited to existing diffusion new trap on every side;
Figure 18 shows mobile wiring data between layer;
Figure 19 shows the old unit of novel via hole elements exchange;
Figure 20 shows the step of transition process in a flowchart;
Figure 21 shows layer step of adjusted size process as flow chart;
Figure 22 a, 22b and 22c show and are placed on transistor, the node on resistance and the capacitor;
Figure 23 shows the size of resistance and calculates, and
Figure 24 a and 24b show the size of capacitor and calculate.
Figure 1 illustrates the typical circuit level.The building block 1 of circuit is placed in the into bigger module 2, and this module is positioned in again in the bigger module 3.
The unit transition process is made up of following three distinct steps:
1) calculates desirable equal proportion zoom factor;
2) use equal proportion zoom factor equal proportion convergent-divergent entire circuit; And
3) any mistake in the fix-up circuit.
These steps are described below in further detail.
In first step, use at least three cover equations to calculate desirable equal proportion zoom factor, this will be by describing referring to figs. 2 to 6 below in further detail.When solving each equation, the equal proportion zoom factor of use is the least factor that all equations allow.In other words, final circuit is not less than the circuit that is allowed by all equations.
In second step, use the factor equal proportion convergent-divergent entire circuit of calculating.This is to multiply by each yardstick by identical factor to finish, and these yardsticks comprise the position of building block, the position of connector and yardstick, the position of the element in building block and the geometry of these elements.
As shown in Figure 7, final result is that the equal proportion convergent-divergent of ifq circuit duplicates.Yet, run counter to many design rules, and component value will be incorrect, for example, transistorized width and length may be too big and too little, provide or operation or can not operate slowly.Resistance and electric capacity also may have incorrect value.
Third step is a fix errors.For repair operation various steps are arranged, as follows:
1), can adjust all physical dimensions in any concrete layer by adjusting layer size.For example,
Can adjust the coordinate of the shape in the polysilicon layer.This is called " adjusted size of layer ".
For example, the polysilicon area on the diffusion region of transistor formed can increase or reduce, with
Just obtain minimum yardstick or minimum interval is provided.This is presented among Figure 10-11.
Percentage by fixed amount (for example 0.2 micron) rather than original-shape changes yardstick.
2) a part of element can not change: particularly the power connector size is not reduced, and this is
Can influence electric current in the circuit owing to reduce this size.Since power connector often than
Other connector is big, thus by their size it is discerned, or by them
The signal name discern.Thus control logic remain special size element not
Be changed, and only reduce to drop on those size of component under the specific qualification.This
Be presented among Figure 12.
3) edge adjustment.If the area of element is too big, if perhaps an edge is too near to layer
Adjusted size or another element behind the equal proportion convergent-divergent, can be by moving this element
The edge rather than by changing whole size of component it is adjusted.This demonstration
In Figure 13.For example, transistorized size can change by this way.
Therefore equal proportion convergent-divergent process was made up of following three steps:
1) whole equal proportion zooms to an immobilisation factor;
2) the fixedly equal proportion convergent-divergent of element (layer equal proportion convergent-divergent), it can comprise nearly three
Independent step; And
3) edge adjustment.
This process can comprise following feature in addition, and they are preferably but are not basic.
1) contact is removed and replacement (seeing Figure 15).It is many as far as possible that hope provides on each element
Electronics contact, so reduced current density by those contacts.According to newly establishing
The meter rule is not again the contact of equal proportion convergent-divergent, but preferably removes them simply
In available space, insert contact as much as possible then.
2) increase and removal layer (seeing Figure 17).Some manufacture methods needed more than former method
Many layers, and certain methods does not need so much.Can revise this method with according to
Need to increase and the reduction layer.For example, if new method needs extra layer to make crystalline substance
The body pipe, configurable computer is to discern each transistor (for example by the identification diffusion layer
On polysilicon layer), increase extra layer then as required.
The step of this method and this method of composition will be described now in further detail.The technology of revising circuit relates to a series of step, and these steps are scaled data and revise the shape that is included in its inside, produce the design rule of the manufacturing process of last chip to meet domination.
Comprise in the method technology will to all elements on the chip be connected geometry and work, chip is including, but not limited to MOSFET and bipolar transistor, resistor, capacitor and diode.
The input data that are used for process migration can be such as any existing chip or the IC layout of the industry standard format of GDSII or CIF or be included in wherein intellectual property.These files will comprise the data that constitute chip and can comprise rectangle, polygon, passage, sample (instance), array and label.
Revise sequence and will comprise in following some or all:
Design analysis and equal proportion convergent-divergent calculate;
Overall equal proportion convergent-divergent;
Gate-width degree and length adjustment;
The equal proportion convergent-divergent of layer;
Polygon edge is adjusted;
Contact replaces;
Adjust overlapping;
Increase or the removal layer;
Elements exchange;
Checking.
Calculate to overall equal proportion convergent-divergent in order to use a factor, must check that existing layout is to determine that layout must be by the amount of equal proportion convergent-divergent.Three factors must considering in this process are:
1. variable-geometry value;
2. absolute geometry value;
3. planning grid (design grid).
Take out here first, promptly variable geometry value, the many design rules in integrated circuit manufacture method are used as minimum value and provide, and must meet or surpass when design circuit.This example is at interval a rule between two geometries on a kind of definite identical layer, and it must guarantee that these two geometries can not be merged together in manufacturing process.As long as the minimum value that provides is not run counter to, interval rule can be exceeded.
Variable-geometry value example comprises width, the boundary of interval and layer.
Fig. 2 shows the variable rules example, the interval 4 of different geometries wherein, overlapping 5 and width 6 must be equal to and greater than one distance is set.
Second factor relates to the absolute geometry value.For some geometry, the integrated circuit (IC) design rule has usually and must satisfy and intransitable fixed value.These are applied in the contact and through hole of connecting wiring circuit usually, and for each appearance of these shapes, this value must satisfy.In addition, transistor size is limited in the circuit meshwork list (net list), and this must be mated in layout.These values can not be satisfied and mistake will be with respect to circuit arrangement or net table look-up layout the time, caused occurring.
As shown in Figure 3, the example of fixed value comprises contact and clear size of opening 7, transistor size 8, resistor size and capacitor sizes.Show fixedly geometry value example, wherein geometric scale must equal definition value.
At last, integrated circuit is designed to have the conduct coordinate of each shape of the multiple of the grid of qualification in advance.The equal proportion zoom factor must be considered new planning grid, and this can finish in two ways, drop on the grid with the coordinate that guarantees all shapes in the equal proportion convergent-divergent layout by calculating the equal proportion zoom factor, perhaps they during by the equal proportion convergent-divergent with coordinate Fast transforms (snapping) to grid.All coordinates in final chip must be placed on the planning grid of qualification.
The scale factor of any process migration will be from new making method and technology standard rule and the ratiometer that is used between the rule of original device calculate.Have three distinct chip parts, limiting factor and each ratio that they can be in the design of equal proportion convergent-divergent must be calculated.Maximum in these three ratios will be defined as the restriction factor in the equal proportion convergent-divergent chip.
1. interconnected equal proportion zoom ratio.
As ratio, must calculate the width and the interval of each wiring layer by the following formula definition:
Interconnected equal proportion zoom ratio=(new width+at interval new)/(old width+old interval)
Fig. 4 shows interconnected interval 10 and width 11.
2. clear size of opening ratio and seal (enclosure).
Clear size of opening is the size of the fixedly rectangle of the through hole between the composition wiring layer;
Clear size of opening ratio=maximum ((new through hole 1/ old through hole 1), (new through hole 2/ old through hole 2) ...)
Fig. 5 shows through hole geometry 12, and it comprises ground floor 13,3 * 2 arrays 16 of the through hole 14 and the second layer 15 and through hole geometry.
3. transistor geometries ratio.
The transistor geometries ratio dwindles relatively for the shape of forming distance between two transistors in the separate section of diffusion region:
Transistor geometries ratio=new (2a+2b+2c+2d+e)/old (2a+2b+2c+2d+e)
Fig. 6 a and 6b show various transistor geometries, wherein L=transistor length and W=transistor width.
To determine the equal proportion zoom factor from these maximums that calculate.The equal proportion zoom factor is rounded up to the next one whole grid point, i.e. mod (ratio grid)=0.
The 4th factor relation that needs to consider is to the circuit that comprises resistor and capacitor.This need rely on the value of the material that is used to construct them in two kinds of manufacture methods and convergent-divergent.Resistor and capacitor are by the value defined on every square unit of the material that uses in their structures.The ratio of these values in old and new manufacture method is used to calculate the equal proportion zoom factor of these circuit elements.By reference Figure 23 and 24 it is carried out more detailed description.
In case determined the equal proportion zoom factor, it is applied on each unit and geometry in the entire chip.Each coordinate is multiplied by the equal proportion zoom factor, to reduce chip size, keeps the geometry of chip and level intact simultaneously.In this stage, except ratio, new chip will be all identical with old chip.
The equal proportion convergent-divergent of geometry and unit can be defined as coordinate equal proportion convergent-divergent.Each scalar value is by the following formula adjustment:
(x coordinate * ratio) (y coordinate * ratio)
Fig. 7 a and Fig. 7 b show overall equal proportion convergent-divergent.In overall equal proportion convergent-divergent process, original chip 18a is by scaled, and forming new chip 18b, and each the shape 19a in original chip, 19b, 19c be by scaled shape 20a, 20b, and 20c replaces.In each case, new yardstick equals old yardstick and multiply by the equal proportion zoom factor.Each shape in layout will be about the initial point of chip axle, i.e. x=0, and y=0 adjusts.
By two kinds of materials, (being called diffusion) doped silicon, and polysilicon (perhaps being metal sometimes) overlapping, determines the CMOS transistor in the circuit.When transistorized width of equal proportion convergent-divergent and length, always absolute value may be applied to by layout each the diffusion and polysilicon in shape.On the contrary, the diffusion of transistor formed width and length and polysilicon must be changed by the percentage of transistor size, so each must and be adjusted into the multiple of current size by equal proportion convergent-divergent successively.This relates to a kind of edge of use method of adjustment, and its identification constitutes the diffusion of each transistor width and length and edge and mobile their component values to satisfy the demand of polysilicon.It is different with the equal proportion convergent-divergent that the edge adjustment can be considered to.Fig. 8 shows transistorized the defining of defining and be worth of CMOS.
Single transistor is discerned with Boolean (boolean) operation, and this operation is placed into mark shape on the zone of any polysilicon 21 cross-diffusion 22.These shapes will form the basis to other transistor size operations that comprise in the transistorized circuit of CMOS.
The diffusion of transistor formed and the edge of polysilicon are selected by the percentage of gate-width degree and length and are moved, to adjust transistorized value.A diffusion may constitute several transistors, so equal proportion convergent-divergent program must handle each edge successively, to obtain the right value of all crystals pipe.Fig. 8 and Fig. 9 show the edge adjustment of CMOS transistor.
As shown in Figure 8, by adjusting the edge 23 of the polysilicon 21 that forms door, can change transistorized door length L.By the edge 24 intersection polysilicons 21 that move diffusion 22, adjust width W.By adjusting these edges 23 and 24, can change transistorized parameter, therefore changed their effects to entire circuit.
As shown in Figure 9, many transistors can be constructed by a diffusion material 25, and transistorized edge of adjustment formation therefore can exerting an influence to other.By detecting each edge in this diffusion, can adjust and guarantee that all transistors satisfy required parameter.If desired, the transistorized edge that constitutes more than can be divided, to adapt to required device size.For example, edge 26 and 27 is divided at the some place that is marked with " X ", so that change correct.
Some manufacture methods may need transistor size with different quantitative changeizations, depend on their original size and the function in circuit, therefore, a kind of method that defines them can be used to adjust equal proportion convergent-divergent process to satisfy these restrictions, and this method is shown such as equivalence.
In case the whole layout of equal proportion convergent-divergent, each layer that constitutes design drawing must be exaggerated or dwindle to satisfy the design rule of new manufacture method.This is to utilize the technology be called level layer equal proportion convergent-divergent to finish, and the shape connectivity (connectivity) between the holding unit simultaneously in the circuit can be amplified or dwindle to this technology.
With before removing the connection between the shape on the unnecessary overlapping and maintenance identical layer between the shape, utilize all shapes on layer of Boolean function to be incorporated in together at the equal proportion convergent-divergent.For the electric globality of holding circuit, must keep the connection between the shape on the various layers, even these shapes occur on not at the same level in the level.The separation if they become, circuit are with inoperative, so stratum proportion convergent-divergent person considers that this problem is necessary.
The internuncial problem of layer only occurs in the layer that comes into question and will be retracted when comprising level with data.By moving inward all edges of shape, they will be separated with the shape in the subelement, and this will break the electrical connectivity in the circuit.
Figure 10 shows layer contraction and breaks connectivity.Circuit comprises unit, top 30 and some subelement 31a, 31b, 31c.Shape 32 on the shape 32a adjacency in subelement 31a in the unit.If all shape 32a, 32b, 32c shrinks, and they will become and be separated from each other, shown in Figure 10 d.
In order to remedy, before implementing to shrink, the shape in subelement is copied to top and merges with data on this grade.In case contraction process is finished, be used as template applications to remove any unnecessary material from the shape of subelement.
It also is possible layer data being remained on the edge of unit, and this unit is by the bounding box of cell data or represent the shape on border to limit.Topology data can be held on the border of unit to keep equal proportion convergent-divergent connectivity.
Figure 11 shows has internuncial level layer contraction.In example, all these three shape 32a, 32b, 32c shrink but their keep connection between them.Have only disconnected edge to be retracted.Further rule can be applied on the stratum proportion, to limit its operation to the shape of coupling intended size rule, promptly they less than or greater than giving dimensioning.This just allows data on the identical layer with different amount convergent-divergents.
Figure 12 shows the adjusted size by the layer of geometric widths, and the shape 33b that original-shape 33a is modified substitutes.In this example, if the section 34a of shape, 34b, 34c satisfies dimensional standard, and they can be retracted.The section 34a that dwindles, 34b, 34c keep and big period 35 adhere to.
In order to satisfy all design rules of migration chip, be necessary to adjust the partial shape that constitutes chip rather than as overall shape.This can be described as " polygon edge adjustment ", and it checks each summit of shape, and it is adjusted with respect to the position of other shapes in the layout according to it.
Want controlled edge to be used for revising to define their functions by the qualification of the shape on the individual course or by the Boolean logic identification at circuit.In case these have determined, can be by adjusting these edges from the absolute value of their present positions or with respect to another edge on the identical or different layer.Also can be by their another edges on the identical or different layer adjust them apart from percentage.Figure 13 shows the adjustment of transistorized edge.Adjust to limit transistorized first edge 36, or the minimum overlay that second edge 37 is used for transistor or contact is possible.
Contact in the integrated circuit use dielectric layer and through hole are to allow wiring layer connecting circuit element.These are size and the typical square configuration at interval that possess skills and define in the design rule.Connection between the broad gauge of material needs bigger contact area.This can pass through a big contact, or more generally, as the array qualification of even contact shape.
Contact and shape of through holes can be as above-mentioned by the equal proportion convergent-divergents.On the other hand, existing contact and through hole can be removed and use the new shape array that meets new design rule to replace.These can be formation and want the rectangle in connected zone as unit or a series of covering of the contact of single array shape.Want the sequence B oolean function in connected zone to limit this zone by isolating.New shape meets new design rule by structure rather than equal proportion convergent-divergent.
Can use the contact between the other materials of identical technology innovation such as metal and polysilicon.Shown in Figure 14 a and 14b, contact and through hole 40 are used to the silicon 41 in the Connection Element and the metal wire 42 of connecting circuit.They also are used to the different layers of metal is linked together to allow complicated wiring.Many integrated circuits will have the multiple layer of wiring Connection Element.These contacts and through hole are actually the hole in the separated dielectric substance 43 of different layers.
Contact shape from the metal to silicon often is generated as simple polygon, rather than sample (instance), and each shape is satisfied the new shape replacement of new design rule.Each contact is removed and is had the new shape replacement of correct yardstick.
In many cases, it is preferred increasing contact as much as possible between layer, with the current density of each contact that helps to reduce to flow through.This can reach by the zone that a series of Boolean function identifications comprise contact, and the many contacts that will install can be filled in this zone.For example, shown in Figure 15 a and 15b, two the big contact holes 44 of old technology that are placed on the place of metal 42 overlapping silicon 41 can be in new technology be replaced by eight less contact holes 45.
In the integrated circuit some layer need be with overlapping other the layer of the amount that limits in design rule.Force these layers to meet design rule by the edge adjustment of Boolean logic OR by above-mentioned definition.
The common instance of ply comprises that the polysilicon of door is overlapping overlapping with the metal that contacts.Figure 16 shows ply.Polysilicon 48 must be with minimum fixed range 50 overlapping diffusions 49.
Variation between the integrated circuit manufacture method mean some layers needs in original chip be removed with other the layer be increased.This example is implanted layer or isolation well.
All shapes on unnecessary layer by each shape of identification on this layer also deletion and they are hierarchically removed.
New layer may limit with another layer with respect to existing layer: for example, and by trap being placed on around the diffusion layer, if but be that it is intersected by polysilicon and makes a transistor.For example, Figure 17 a shows the diffusion 52 in transistor 53 and the diffusion 54 of transistor outside.Shown in Figure 17 b, 55 on new layer is added at as around the diffusion of the part of transistor 53.
Data also can be thus lifted on the new layer such as extra wiring layer.Wiring information can rise on the new layer from existing layer.This just allows layout to be compressed the gap that forms when being used in these shapes and being moved.Figure 18 a and 18b show the wiring data between the mobile layer.In the old arrangement shown in Figure 18 a, be connected on second metal line 57 by metal 1-metal 2 through holes 58, the first metal lines 56.In the new arrangement shown in Figure 18 b, rise to the 3rd metal line 59 from the wiring information of first metal line 56, and through hole 58a is changed correspondingly.
Figure 19 a and 19b show the old unit of new through hole unit conversion.Through hole unit 60a by old technology limiting comprises the shape that is used to connect two metal levels, first metal 61 and second metal 62.This is the exchange for the new through hole unit 60b that comprises the shape that is used for connecting the new technology metal level.Many through holes are placed as the sample of subelement, and this subelement comprises three shapes that are used to make up it: two metal levels and a via layer.This can utilize the new through hole unit that comprises identical three layers simply to replace, or readjusts size for new design rule.Some through holes may be bigger than minimum dimension, and have the multiple through hole that connects two metal levels.When with these new through hole unit of exchange, adjust new cell size to mate the quantity of the shape of through holes in the old unit.By exchanging each through hole unit by this way, the through hole in circuit is updated to satisfy the constraint of new technology.
In case moved entire circuit or its part, used the industry standard design instrument that it is verified.This comprises Design Rule Checking (DRC) system and layout contrast schematic diagram system (LVS).This will guarantee newly to move the integrality that chip meets new design rule and kept the connection in the circuit.
In addition, at any time can use interconnected chronometric analysis device will correctly carry out in new manufacture method to check layout.This can be used as uses after overall equal proportion convergent-divergent the guidance substantially of the circuit performance in the new method, even it does not meet new design rule.In case transition process finishes can obtain simulating more accurately.
When finishing layout migration and new chip by checking, it can be submitted such as the industry standard format of GDSII or CIF.
With reference to the flow chart shown in Figure 20, the step of transition process will be described now.
Although these technology can be improved transition process, they are for finishing transition process not necessarily.
The 4th step 73 is the conservator event data.Therefore the information that is included in the raw data base can be useful with reference to these data easily by the procedure reference in the whole transition process.A kind of technology that is discussed in more detail below by reference Figure 22 is increased to the node that comprises design parameter on each device in the layout.These nodes can be used for preserving the information about device, such as the size and the title of figure layer.
The 5th step 74 is an equal proportion convergent-divergent design drawing.In case determined the equal proportion zoom factor, each coordinate in design multiply by the equal proportion zoom factor, provides except size and all the same design drawing in original any aspect.
The data of each element of equal proportion convergent-divergent are as follows:
Rectangle: lower-left (X) * ratio
Lower-left (Y) * ratio
Upper right (X) * ratio
Upper right (Y) * ratio
Polygon: coordinate (X) * ratio
Coordinate (Y) * ratio
Path: coordinate (X) * ratio
Coordinate (Y) * ratio
Width * ratio
Literal: coordinate (X) * ratio
Coordinate (Y) * ratio
Font size * ratio
Sample: coordinate (X) * ratio
Coordinate (Y) * ratio
Multiplication factor * ratio
Array: coordinate (X) * ratio
Coordinate (Y) * ratio
Multiplication factor * ratio
Delta (delta) is the * ratio (X)
Delta (delta) is the * ratio (Y)
The 6th step 75 is for adjusting the size of layer.In case the equal proportion scaled data can be adjusted the size of each layer, to satisfy the minimum widith value that limits in design rule.This can finish to guarantee that data on each layer satisfy and is used for rule at interval, and also has electric capacity that reduces on each layer and the advantage that improves circuit performance.When the elementary equal proportion zoom factor of selected design drawing, overall equal proportion convergent-divergent calculates the adjustment subsequently that can consider in layer size.
Can be by absolute value or the percentage equal proportion scaling layer recently by layer size.In order to pass through absolute value equal proportion scaling layer, use following calculating:
Rectangle: lower-left (X)+value
Lower-left (Y)+value
Upper right (X)-value
Upper right (Y)-value
Polygon: coordinate (X)+or-ratio
Coordinate (Y)+or-ratio
Path: width * ratio
Increase or deduct the equal proportion amount of zoom and will depend on coordinate position on the shape shell.If it is in the bottom or the left hand edge of shape, the equal proportion amount of zoom will be added on the coordinate, if it is in the top or the right hand edge of shape, it will be deducted.
Each coordinate that relative equal proportion convergent-divergent relates in the shape multiply by the identical factor to adjust coordinate.
The data of each element of equal proportion convergent-divergent are as follows:
Rectangle: lower-left (X) * ratio
Lower-left (Y) * ratio
Upper right (X) * ratio
Upper right (Y) * ratio
Polygon: coordinate (X) * ratio
Coordinate (Y) * ratio
Path: coordinate (X) * ratio
Coordinate (Y) * ratio
Width * ratio
This technology will be readjusted the size of shape, but it also will from they with respect to the offset of other shapes the circuit they.For they being turned back to their home position, can calculate the central point of each shape and the center that new shape moves back to old shape.The middle definition center of the rectangle convex closure by adopting shape.
The 7th step 76 is for adjusting the transistorized size of CMOS.When carrying out overall equal proportion convergent-divergent, the shape of transistor formed will be adjusted size together with other shapes in the layout.At these layers be transistorized parts, promptly spreads or during polysilicon, when further adjusting size and can occur in each individual course by the equal proportion convergent-divergent.Yet, may be owing to other factor elements such as circuit timing and driving force, transistor need be by the equal proportion convergent-divergent.By with reference to figure 8 and Fig. 9, transistor equal proportion convergent-divergent process has been described in more detail in the above.In addition, as being discussed in more detail below by reference Figure 23 and 24, also adjustable resistor and capacitor.
The 8th step 77 is for upgrading contact.Describe this process in the above in detail by reference Figure 15.
The 9th step 78 is for increasing and/or the deletion layer.Different manufacture crafts can have the layer of the varying number that constitutes chip.This example comprises injection and trap layer.
These new layers be created within existing layer around, and this can be by duplicating each shape that limits in the layer, strengthens its size and then it is moved to new layer and go up and finish.If find them less than the appointment minimum range in the design rule, identical materials should be filled in any gap between the shape on this new layer.
If old layout comprises the unwanted shape of new manufacture method, each shape can be deleted from database so.
The tenth step 79 is for checking design.In case finished transition process, can use standard layout's method of inspection to check design drawing.These methods comprise Design Rule Checking (DRC) and layout and schematic diagram check and inspection (LVS).The comparison of carrying out between the old and new layout (LVL) also is useful.These all inspection technology are considered to be in standard in the electronics industry, and the software of carrying out these inspections can obtain from various suppliers there.
The yardstick that is used to make up transistorized shape by change is adjusted transistor.This is for bipolar (NPN ﹠amp; PNP) device and MOS (field effect) device is correct.Bipolar transistor is considered to discrete elements usually, but the MOS device is often combined to save the space in the circuit.The equal proportion convergent-divergent of bipolar device calculates the rule domination that will be configured device, and these rules comprise minimum widith, and is at interval, overlapping and seal.
These regular ratios of in old and new design rule standard each must be considered in the equal proportion convergent-divergent calculates.The public domain of the superimposed diffusion polysilicon of the transistorized size of CMOS limits.The edge that overlapping width and length limit transistorized value and adjusts these two shapes has changed its value.
With reference now to Figure 21, a layer equal proportion convergent-divergent process will be described in more detail.In order to satisfy the standard of new design rule, single layer needs to increase in proportion or reduce in proportion after overall equal proportion convergent-divergent is finished.This will guarantee that data will satisfy the needs of new manufacture method, and metal connecting layer is reduced to their minimum widith, to reduce the electric capacity in the circuit.Layer equal proportion convergent-divergent the most often is applied to interconnection layer and constitutes in the diffusion and polysilicon layer of CMOS.
First step adopts initial data 81 and calculates equal proportion zoom factor 82.After using overall equal proportion zoom factor, calculate the scale factor of each layer and can be used as absolute value or as percentage.Be calculated as follows:
Absolute value:
Percent value:
Each limit that the adjustment size value of deriving is taken from shape, so they need be divided by 2.
Only changing the size of some shape and keep other shape invariance may be needs.This example is the wide power metal on the layer identical with overall interconnected shape.In this case, having only the shape narrower than particular value will be undersize or oversize.This process comprises that selection should and apply the step of equal proportion zoom factor 84 to the sort of selection by the shape 83 of equal proportion convergent-divergent.
When the polygonal shape undersize on the layer, they will be separated from each other, and therefore break the electric integrality of circuit.This must forbid to guarantee that circuit still works after adjusting the size program.If these shapes are attached to other shapes on circuit level not at the same level, this will be further complicated, and this is because attachment issue will depend on the place that shape is placed.If the geomery of discussing is excessive, they will be overlapped, so this problem will can not occur.This process comprises the shape 85 of selecting undersize and the step of selecting to keep being connected to it 86 shape from these shapes.
A kind of method that keeps these all shapes to connect in the unit is before adjusting geomery they to be combined.The shape that this means connection is not dispersed mutually, therefore can not become to break in adjusting dimension process and hold.
To temporary layer, can keep the connection between the shape on level not at the same level by replicating original shape before the data Layer undersize.Data on each subelement can be reduced size successively, and stay original profile at the scene.When the layer data in the unit touches temporary layer in the subelement, use a series of Boolean operation can keep connection, connect shape 87 and fill the gap 88 between unit, top and the subelement and keep electric integrality selecting.
In case defined size value and connectivity information, as required, can pass through absolute value 89 or percentage 90, subsequently by skew shape 91, adjust the size of shape.
The useful post-processing function of adjusting layer size relates to be removed can be by each sulculus mouth 92 and projection in shape of readjusting on the layer that the size program produces.These should be removed, because they may cause the mistake in the Design Rule Checking interim report.
Referring now to Figure 22 a, 22b and 22c describe the method for the old design load in a kind of memory node performance.Before the layout of revising integrated circuit, the information of storing about present layout by certain methods is useful, is used in whole modification process reference.Want stored information can comprise the size of component of forming circuit, such as transistorized width and length or resistance and capacitance.By these information of storage before revising design, update routine subsequently can be checked their values with respect to initial value, need not consider that how those data are by equal proportion convergent-divergent process influence.
A kind of method of storing these data is for storage in ascii text file and with it as a reference, but this has the shortcoming that breaks away from the database that comprises layout and need have the details of each position of components, makes it excessively wordy like this.
A kind of method preferably comprises with each element in the circuit stores this information.Visit these elements and will return the information that obtains from ifq circuit, be used for the new value of comparing element.For example, system can increase simple " node " object to carrying on the individual component database of information.These nodes are not by equal proportion convergent-divergent process influence, and portability is as the relevant information of performance.
For example, Figure 22 a, 22b, 22c shows a node that is placed on the CMOS transistor that comprises original W/L value respectively, is placed on to comprise its type a node on the resistor of yardstick and value, comprise its type with being placed on, a node on the capacitor of yardstick and value.
Calculate referring now to Figure 23 detailed description resistive.Form resistor by between two nodes, placing a slice semi-conducting material.Two factors that limit resistance value are the resistance that needs and want derivative electric current.
The resistance value of resistor is by " sheet resistance " domination to the ratio and its material of formation of its length L of its width W.In the example shown in Figure 24, resistance has following value:
P-diffusion resistance resistivity=100 ohms per squares
Every square of current density=100 μ A
Value=8.5 Ping Fang @100 ohm-sq=850 ohm
Electric current=0.5 square * 100 μ A/ squares=50 μ A.
When applying the equal proportion zoom factor to resistor the time, have to consider these ratios of the current density of layer resistivity and old and new resistor material, to obtain the identical value in the new resistor.Because the width and the length of resistor will be by equal influences, equal proportion convergent-divergent resistor will cause same square number, with therefore identical value.Yet the layer resistivity of new method may be different, and this need consider to calculate its value.This obtains by using following equation:
New square number=(old resistivity/new resistivity) old square number of *
After equal proportion convergent-divergent resistor, its width also will influence the portable maximum current of resistance.Therefore the electric current that relates to will can only be obtained this value by the check circuit performance by the regulation of the circuit around the resistor.If the width of resistor need increase to hold high current, must be with the factor equal proportion convergent-divergent length that equates, to keep identical resistance value.
Describe capacitor calculating in detail referring now to Figure 24 a and 24b.By placing conduction or semi-conducting material 95,96 thin layers to another thin layer, and the 3rd material 97 is placed between them to form dielectric, forms the capacitor in the integrated circuit.For each manufacture method, the type of spendable layer is defined in the design rule that is used for each manufacture method, and these are also with the specified capacitance value, is every square of some farad.Because farad is very big unit, these with the typical case with skin (pico-) farad or fly the definition of (femto-) farad.
The value of capacitor is provided by following formula:
Width * length * nF per unit area
Because the value of capacitor is almost completely limited by its surface area, equal proportion convergent-divergent capacitor chop and change should value.If this is the case, the yardstick of capacitor is adjusted value with retention capacitor with needs after equal proportion convergent-divergent process is finished.
Claims (17)
1. revise the method for integrated circuit, this method may further comprise the steps:
Select an equal proportion zoom factor,
According to equal proportion zoom factor equal proportion convergent-divergent circuit, and
For functional and meet design rule and adjust circuit.
2. method as claimed in claim 1, its moderate proportions zoom factor is selected by calculating a plurality of predetermined equal proportion zoom ratio, and selects to be equal to or greater than an equal proportion zoom factor of maximum predetermined equal proportion zoom ratio.
3. method as claimed in claim 2, wherein predetermined equal proportion zoom ratio comprises interconnected equal proportion zoom ratio, how much ratios of clear size of opening ratio and electronic component.
4. as the method for claim 2 or claim 3, its moderate proportions zoom factor is selected by be rounded up to the whole grid point of the next one from the predetermined equal proportion zoom ratio of maximum.
5. as the method for previous arbitrary claim, wherein the step according to equal proportion zoom factor circuit equal proportion convergent-divergent circuit comprises that the equal proportion zoom factor multiply by the circuit geometries coordinate.
6. as the method for previous arbitrary claim, wherein for functional and meet design rule and adjust the step of circuit and comprise level layer equal proportion convergent-divergent process.
7. method as claimed in claim 6, wherein level layer equal proportion convergent-divergent process comprises the step according to the element in layer of predetermined layer equal proportion zoom factor equal proportion convergent-divergent.
8. method as claimed in claim 7, wherein level layer equal proportion convergent-divergent process comprises that the step of equal proportion convergent-divergent element is so that keep the connectivity of these elements.
9. as the method for claim 7 or claim 8, wherein level layer equal proportion convergent-divergent process comprises that identification satisfies the element of preset width standard, and only the equal proportion convergent-divergent does not satisfy the step of the element of those standards.
10. as the method for previous arbitrary claim, wherein for functional and meet design rule and adjust the step of circuit and comprise transistor edge adjustment process.
11. as the method for claim 10, wherein transistor edge adjustment process comprises the step of adjusting polysilicon layer width and/or diffusion layer length.
12., comprise the step of upgrading contact and through hole as the method for previous arbitrary claim.
13. as the method for claim 12, wherein renewal contacts with the step of through hole and comprises that removing existing the contact with through hole and with new the contact with through hole replaces them.
14., comprise the step that increases and/or delete layer as the method for previous arbitrary claim.
15., comprise the step of using the method for testing distribution check circuit as the method for previous arbitrary claim.
16., comprise the primary step of analyzing and revising circuit data as the method for previous arbitrary claim.
17. as the method for previous arbitrary claim, comprise the step that increases on the node that the comprises design parameter device in the circuit.
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| GB9914380.2 | 1999-06-21 |
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| CN1369114A true CN1369114A (en) | 2002-09-11 |
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| EP (1) | EP1188186A1 (en) |
| JP (1) | JP2003502769A (en) |
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| CN (1) | CN1369114A (en) |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7882463B2 (en) | 2004-10-15 | 2011-02-01 | International Business Machines Corporation | Integrated circuit selective scaling |
| CN101446993B (en) * | 2007-11-29 | 2012-03-21 | 国际商业机器公司 | Automated optimization of device structure during circuit design stage |
| CN102446237A (en) * | 2010-09-30 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Design method for non-shrinkable IP integration |
| CN104657533A (en) * | 2013-11-18 | 2015-05-27 | 台湾积体电路制造股份有限公司 | Different scaling ratio in FEOL / MOL/ BEOL |
| CN105283955A (en) * | 2013-06-18 | 2016-01-27 | 高通股份有限公司 | Method and apparatus for a diffusion bridged cell library |
| CN105989202A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method for performing DRC (Design Rule Checking) verification on layout |
Families Citing this family (28)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7036103B2 (en) * | 1999-10-14 | 2006-04-25 | Synopsys, Inc. | Detailed placer for optimizing high density cell placement in a linear runtime |
| US6985843B2 (en) * | 2001-06-11 | 2006-01-10 | Nec Electronics America, Inc. | Cell modeling in the design of an integrated circuit |
| US7089524B1 (en) * | 2002-01-22 | 2006-08-08 | Cadence Design Systems, Inc. | Topological vias route wherein the topological via does not have a coordinate within the region |
| US7149991B2 (en) * | 2002-05-30 | 2006-12-12 | Nec Electronics America, Inc. | Calibrating a wire load model for an integrated circuit |
| US6904575B2 (en) * | 2002-06-11 | 2005-06-07 | International Business Machines Corporation | Method for improving chip yields in the presence of via flaring |
| US7069533B2 (en) * | 2003-03-14 | 2006-06-27 | Chatered Semiconductor Manufacturing, Ltd | System, apparatus and method for automated tapeout support |
| US7363236B2 (en) * | 2003-03-14 | 2008-04-22 | Chartered Semiconductor Manufacturing Ltd. | System, apparatus and method for reticle grade and pricing management |
| US7055114B2 (en) * | 2003-10-08 | 2006-05-30 | Hewlett-Packard Development Company, L.P. | Systems and processes for asymmetrically shrinking a VLSI layout |
| US7093211B1 (en) * | 2003-11-03 | 2006-08-15 | General Electric Company | Techniques for modeling current spreading uniformity in light emitting diodes |
| US20050114808A1 (en) * | 2003-11-24 | 2005-05-26 | Mcbride John G. | Framework for accurate design rule checking |
| US7120887B2 (en) * | 2004-01-16 | 2006-10-10 | International Business Machines Corporation | Cloned and original circuit shape merging |
| US7448012B1 (en) | 2004-04-21 | 2008-11-04 | Qi-De Qian | Methods and system for improving integrated circuit layout |
| US7302651B2 (en) | 2004-10-29 | 2007-11-27 | International Business Machines Corporation | Technology migration for integrated circuits with radical design restrictions |
| JP4377342B2 (en) * | 2005-01-18 | 2009-12-02 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor integrated circuit, layout method, layout apparatus, and layout program |
| US7406671B2 (en) * | 2005-10-05 | 2008-07-29 | Lsi Corporation | Method for performing design rule check of integrated circuit |
| JP4674164B2 (en) * | 2006-01-11 | 2011-04-20 | 富士通セミコンダクター株式会社 | Layout method, CAD apparatus, program, and storage medium |
| US20080022250A1 (en) * | 2006-07-20 | 2008-01-24 | Charudhattan Nagarajan | Chip finishing using a library based approach |
| US7823103B2 (en) * | 2006-10-24 | 2010-10-26 | International Business Machines Corporation | Method and system of introducing hierarchy into design rule checking test cases and rotation of test case data |
| US20080201677A1 (en) * | 2007-02-21 | 2008-08-21 | Faye Baker | Integrated Circuit (IC) Chip Input/Output (I/O) Cell Design Optimization Method And IC chip With Optimized I/O Cells |
| US8013400B1 (en) * | 2008-04-21 | 2011-09-06 | National Semiconductor Corporation | Method and system for scaling channel length |
| JP2010021187A (en) * | 2008-07-08 | 2010-01-28 | Nec Electronics Corp | Method of designing semiconductor integrated circuit, design program, and method of manufacturing semiconductor integrated circuit |
| US8775979B2 (en) * | 2010-01-30 | 2014-07-08 | Synopsys. Inc. | Failure analysis using design rules |
| US8627247B1 (en) * | 2012-07-11 | 2014-01-07 | International Business Machines Corporation | Systems and methods for fixing pin mismatch in layout migration |
| US9940428B2 (en) * | 2014-10-07 | 2018-04-10 | Mentor Graphics Corporation | Hierarchical fill in a design layout |
| US9594864B2 (en) | 2015-04-22 | 2017-03-14 | Qualcomm Incorporated | Method for asymmetrical geometrical scaling |
| DE102017127276A1 (en) * | 2017-08-30 | 2019-02-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | STANDARD CELLS AND ADAPTATIONS FROM THEREOF WITHIN A STANDARD CELL LIBRARY |
| US10552567B2 (en) | 2018-01-17 | 2020-02-04 | Globalfoundries Inc. | Automated redesign of integrated circuits using relaxed spacing rules |
| US10685161B2 (en) * | 2018-08-20 | 2020-06-16 | Taiwan Semiconductor Manufacturing Company Ltd. | Region based shrinking methodology for integrated circuit layout migration |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4630219A (en) * | 1983-11-23 | 1986-12-16 | International Business Machines Corporation | Element placement method |
| JPH03142934A (en) | 1989-10-30 | 1991-06-18 | Mitsubishi Electric Corp | Wiring connecting structure for semiconductor integrated circuit device |
| JP2863239B2 (en) | 1990-01-17 | 1999-03-03 | 富士通株式会社 | Simulation method for semiconductor integrated circuit |
| US5862260A (en) * | 1993-11-18 | 1999-01-19 | Digimarc Corporation | Methods for surveying dissemination of proprietary empirical data |
| US5625568A (en) | 1993-12-22 | 1997-04-29 | Vlsi Technology, Inc. | Method and apparatus for compacting integrated circuits with standard cell architectures |
| US5856754A (en) | 1996-01-16 | 1999-01-05 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit with parallel/serial/parallel conversion |
| US5936868A (en) * | 1997-03-06 | 1999-08-10 | Harris Corporation | Method for converting an integrated circuit design for an upgraded process |
| US6279142B1 (en) * | 1998-10-02 | 2001-08-21 | International Business Machines Corporation | Method of on-chip interconnect design |
| US6381730B1 (en) * | 1999-07-09 | 2002-04-30 | Sequence Design, Inc. | Method and system for extraction of parasitic interconnect impedance including inductance |
-
1999
- 1999-06-21 GB GBGB9914380.2A patent/GB9914380D0/en not_active Ceased
-
2000
- 2000-06-21 CA CA002374211A patent/CA2374211A1/en not_active Abandoned
- 2000-06-21 AU AU55436/00A patent/AU5543600A/en not_active Abandoned
- 2000-06-21 WO PCT/GB2000/002256 patent/WO2000079595A1/en not_active Application Discontinuation
- 2000-06-21 IL IL14717700A patent/IL147177A0/en unknown
- 2000-06-21 CN CN00809298A patent/CN1369114A/en active Pending
- 2000-06-21 KR KR1020017016376A patent/KR20020027363A/en not_active Application Discontinuation
- 2000-06-21 US US10/018,867 patent/US6756242B1/en not_active Expired - Fee Related
- 2000-06-21 EP EP00940509A patent/EP1188186A1/en not_active Withdrawn
- 2000-06-21 JP JP2001505063A patent/JP2003502769A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7882463B2 (en) | 2004-10-15 | 2011-02-01 | International Business Machines Corporation | Integrated circuit selective scaling |
| CN101446993B (en) * | 2007-11-29 | 2012-03-21 | 国际商业机器公司 | Automated optimization of device structure during circuit design stage |
| CN102446237A (en) * | 2010-09-30 | 2012-05-09 | 台湾积体电路制造股份有限公司 | Design method for non-shrinkable IP integration |
| CN102446237B (en) * | 2010-09-30 | 2013-09-18 | 台湾积体电路制造股份有限公司 | Design method for non-shrinkable IP integration |
| CN105283955A (en) * | 2013-06-18 | 2016-01-27 | 高通股份有限公司 | Method and apparatus for a diffusion bridged cell library |
| CN105283955B (en) * | 2013-06-18 | 2018-01-30 | 高通股份有限公司 | For spreading the method and apparatus in bridge-jointing unit storehouse |
| CN104657533A (en) * | 2013-11-18 | 2015-05-27 | 台湾积体电路制造股份有限公司 | Different scaling ratio in FEOL / MOL/ BEOL |
| CN104657533B (en) * | 2013-11-18 | 2018-01-26 | 台湾积体电路制造股份有限公司 | The integrated chip design method and eda tool of different zoom ratio |
| CN105989202A (en) * | 2015-02-04 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method for performing DRC (Design Rule Checking) verification on layout |
| CN105989202B (en) * | 2015-02-04 | 2019-04-09 | 中芯国际集成电路制造(上海)有限公司 | The method that a kind of pair of domain carries out DRC verifying |
Also Published As
| Publication number | Publication date |
|---|---|
| CA2374211A1 (en) | 2000-12-28 |
| IL147177A0 (en) | 2002-08-14 |
| KR20020027363A (en) | 2002-04-13 |
| JP2003502769A (en) | 2003-01-21 |
| AU5543600A (en) | 2001-01-09 |
| GB9914380D0 (en) | 1999-08-18 |
| WO2000079595A1 (en) | 2000-12-28 |
| EP1188186A1 (en) | 2002-03-20 |
| US6756242B1 (en) | 2004-06-29 |
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