CN1367979A - Graphics subsystem bypass method and apparatus - Google Patents
Graphics subsystem bypass method and apparatus Download PDFInfo
- Publication number
- CN1367979A CN1367979A CN99816920A CN99816920A CN1367979A CN 1367979 A CN1367979 A CN 1367979A CN 99816920 A CN99816920 A CN 99816920A CN 99816920 A CN99816920 A CN 99816920A CN 1367979 A CN1367979 A CN 1367979A
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- 238000000034 method Methods 0.000 title claims description 12
- 238000003780 insertion Methods 0.000 claims description 9
- 230000037431 insertion Effects 0.000 claims description 9
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 238000004088 simulation Methods 0.000 claims description 4
- 239000002131 composite material Substances 0.000 claims 7
- 230000008676 import Effects 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000002238 attenuated effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 210000003733 optic disk Anatomy 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42653—Internal components of the client ; Characteristics thereof for processing graphics
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/434—Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/41—Structure of client; Structure of client peripherals
- H04N21/426—Internal components of the client ; Characteristics thereof
- H04N21/42607—Internal components of the client ; Characteristics thereof for processing the incoming bitstream
- H04N21/4263—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners
- H04N21/42638—Internal components of the client ; Characteristics thereof for processing the incoming bitstream involving specific tuning arrangements, e.g. two tuners involving a hybrid front-end, e.g. analog and digital tuners
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Computer Graphics (AREA)
- Studio Circuits (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
The present invention provides an on-screen graphics (OSD) subsystem for overlaying OSD graphic images into analog or digital video source signals. The OSD system has a video graphics bypass path and graphics bypass switch for directing and analog video channel around the OSD subsystem during time intervals when the OSD subsystem in not required to insert graphics into the source signal.
Description
Background
The present invention relates to cable TV (CATV) system.More particularly, the invention belongs to a kind of method and apparatus that is used for display graphics insertion subsystem on digital screen of bypass.
Along with being extensive use of of analog video display, produced and the analog video data display graphics image demand of alpha-numeric characters or other figure for example simultaneously.Usually these figures cover on the remote signaling source vision signal that for example broadcast television transmissions, optic disk, videotape or other video source receive independently.Known have the whole bag of tricks to be used for cover graphics image on the vision signal that receives from far-end video source independently.
The United States Patent (USP) 5,051,817 of authorizing Takano has disclosed the system of a stack color character on incoming video signal.In this system, first sync separator separates the horizontal synchronization pulse from incoming video signal.One phase-locked loop (PLL) circuit uses these horizontal synchronization pulses to generate a reference clock signal (P1) that is locked on the incoming video signal.Second sync separator, a timing pulse generator, synchronous selection pass gate circuit of the same colour and one the 2nd PLL circuit produce a phase-locked oscillation output signal on incoming video signal.Reference clock signal and oscillation output signal are used for the character signal and the incoming video signal that generate synchronous.One switching signal maker changeover control signal is so that only export incoming video signal, or the incoming video signal of the color character that superposeed.
Authorize people's such as Zeidler United States Patent (USP) 5,541,666 have disclosed a system that covers digital character signal on the analog signal that comprises a colour subcarrier of being scheduled to, and this subcarrier comprises that a subcarrier phase-locked loop, a digital character produce equipment, a digital video code and a switchgear.The user phase-locked loop produces the clock signal of system on the colour subcarrier that a colour subcarrier and is locked in the analog video origin system respectively.Digital character generates the level and vertical timing of the Pixel Information in the Equipment Inspection analog video source signal, and generates the digital character signal on the intended pixel that will cover analog video source.The digital signal encoding device is responsible for colour subcarrier and clock signal of system to generate an independent colour subcarrier that is locked on the analog video source signal.Digital video code also is transformed into an analog video output signal that has comprised the colour subcarrier that this digital video code generates with digital character signal from digital character generating mode.Master cock just means, respectively when digital character will cover or not cover on the analog video source signal, with analog video output signal from the lead a certain output of this system of digital video code or analog video source signal.
There is a problem in these technology, promptly may only need digital information is inserted in the analog video source in particular time interval.Insertion process must weaken vision signal.In the time interval of inserting digital information with do not have that signal all can weaken in time interval of digital information.
Summary of the invention
Therefore the purpose of this invention is to provide a kind of method and apparatus, be used for cover graphics on vision signal, and one of bypass is used for the OSD graphics subsystem of cover graphics on vision signal in the time interval of cover graphics not.
By a receiving digital video source signal being provided or analog video source signal being converted to the graphics subsystem of digital video signal, the insertion screen is gone up and is shown (OSD) figure to form complex digital signal and to be converted into the analog video signal of exporting to display in video source signal, and these purposes and other purpose all realize.In order in the time interval that does not cover the OSD figure, the analog video source signal of importing to be delivered directly to display, provide a graphics subsystem bypass circuit.
Brief description
With reference to following accompanying drawing the present invention is described by way of example below, in the accompanying drawing:
Fig. 1 is the structured flowchart that comprises the system of graphics subsystem bypass according to of the present invention.
Fig. 2 is the operational flowchart of the system among Fig. 1.
Preferred embodiment
Fig. 1 is the structure chart of a set-top terminal 10.This set-top terminal comprises the tuner 12 that links to each other with the cable of community's cable TV (CATV) net introducing.One switch 14 links to each other with the output of tuner 12.What it will be appreciated by those skilled in the art that is that switch 14 also can be substituted by a splitter as required.The output 15,17 of switch 14 is connected respectively to an analog video path 19 and a digital video path 21.One analog channel video demodulator 16 is connected to first switch output 15 by analog video path 19.What it will be appreciated by those skilled in the art that is, the cable input be in the system of scrambling signal, analog channel video demodulator 16 also can comprise a descrambler as required.
One digital channel demodulator 18 is connected to second switch output 17 by digital video path 21.What it will be appreciated by those skilled in the art that is, in order there to be encrypted digital information to pass through to use in the system of tuner 12, digital channel demodulator 18 also can comprise a decipher as required.One " motion picture expert group " (MPEG) decoder 20 links to each other with digital channel demodulator 18 in digital video path 21.Analog video path 19 is all gone up with a screen with digital video path 21 and is shown that (OSD) graphics subsystem 40 is connected.
Show on the screen that (OSD) graphics subsystem 40 comprises an analog to digital (A/D) transducer 42, it is connected to the switch 43 that analog video path 19 and has two-way input 45,47. Input 45,47 links to each other with MPEG decipher 20 with modulus (A/D) transducer 42 respectively.Show on the screen that (OSD) graphics subsystem 40 comprises that also an OSD inserts unit 44, it is connected to switch output 49, and a digital to analogy (D/A) transducer 46.Digital to analog converter 46 inserts unit 44 with OSD and links to each other with output 50.Show on the screen that (OSD) graphics subsystem 40 and analog to digital converter 42, switch 43, OSD insert unit 44 and digital to analog converter 46 promptly constitutes independent chip or chipset, for example an ATI Technologies Rage Pro and a Rage Theatre.Should understand other manufacturer similar chip and the chipset that possesses these functions also is provided.Can use any suitable chip or chipset that possesses these functions at this.
The one figure by-pass switch 24 that possesses two- way input 56,54 is connected to OSD graphics subsystem output 50 and one OSD bypass path 22.Bypass path 22 extends to figure by-pass switch input 54 from analog video path 19.Figure by-pass switch output 58 provides video output 60.Memory 52 is connected to OSD graphics subsystem 40.And, have a microprocessor 26 to be used for optionally controlling above-mentioned each element.
Fig. 2 has described the general operation of system 10 among Fig. 1.At first, a separated or switching of input channel that comes self-tuner 12.Then, microprocessor 26 determine these channels be numeral or simulation.If digital channel, just the switch 14 by microprocessor control starts and separates the mpeg decode process that is in harmonious proportion, and is that screen is gone up and shown that the insertion process is inserted into osd information in the digital video input subsequently.After OSD insertion process, the vision signal that has comprised digital video and figure insertion information simultaneously is converted into analog signal and is input to standard indicator in digital to analog converter 46.Get back to the top of Fig. 2, if channel is simulated, then the switch 14 by microprocessor control is directed to simulaed path 19.Signal is by the OSD graphics subsystem then, and perhaps microprocessor 26 activates a bypass, and the input channel of demodulation directly is directed to video output 60 to be presented on the standard indicator.
Describe system operation in detail referring now to Fig. 1.Memory 52 has comprised the OSD Figure and Image of the digital form of being stored by microprocessor 26.Be understandable that this information may be revised by microprocessor 26 so that show different OSD graph images in video output 60.Preposition terminal 10 receives the cable input by the tuner 12 that can select required channel from catv network.Based on selected channel is simulation or digital, and switch 14 is directed to analog channel video demodulator 16 by analog video path 19 with selected channel, perhaps is directed to digital channel demodulator 18 by digital video path 21.To call digital channel and analog channel in the following text.Digital channel comprises mpeg compressed video usually, and analog channel comprises picture intelligence usually, as NTSC or PAL or other standard signal.But be understandable that these channels can transportation simulator and the out of Memory content of digital form.
Analog channel video demodulator 16 is used for the demodulation analog channel, and it is any by the analog video signal of scramble to be used for anti-scramble as required.Demodulated analog video signal 19 is transported to figure bypass path 22 and OSD graphics subsystem 40 from analog channel video demodulator 16 along video path.
Digital channel demodulator 18 is used for the demodulation digital channel, and can decipher the digital signal of any encryption as required.Demodulated signal from digital channel demodulator 18 is transported to mpeg decoder 20 along digital video path 21.Be understandable that although decoder 20 is exemplified as mpeg decoder, other digital compression technology also can be in this utilization and correspondingly decoding.It is the pure digi-tal vision signal that mpeg decoder 20 is used for the mpeg encoded signal decoding, sends into OSD graphics subsystem 40 then.
Digital video signal from mpeg decoder 20 is admitted to second switch input 47.When tuner 12 is transferred to analog channel, microprocessor 26 master cock 43 in the selected time interval will be sent into OSD through analog-to-digital vision signal and insert unit 44.When tuner 12 is transferred to digital channel, microprocessor 26 master cock 43 in the selected time interval will be sent into OSD from the digital video signal of mpeg decoder 20 and insert the unit.According to the position of switch, OSD inserts unit 44 and will mix from the digital video signal in digital video path 21 or from the digitized analog video signal in analog video path 19 and the required OSD figure that is stored in the memory 52 in advance.This mixing or compound then signal is admitted to digital to analog converter 46 converting analog signal to, and it has comprised the numeral or the analog video source signal of the OSD figure that comes self-tuner 12 and insert from memory 52.The data that memory 52 also is used for storing modulus, digital-to-analogue information temporarily and inserts unit 44 from OSD.
An advantage of the invention is do not need with the OSD figure mix with analog signal the time Between in the interval, analog video signal can directly be delivered to video output 60, and can be because of OSD Signal conversion attenuated signal in the graphics subsystem.
Claims (19)
1. video and graphic subsystem that is used for video terminal comprises: one sets the digital video output that is used for receiving digital signals; One sets the analog video input that is used to receive analog video signal; One AD converter, it has a numeral output and an input, is used for receiving analog video signal from the analog video input; One screen is gone up display unit, and it has a numeral output and an input, and this input optionally links to each other with the numeral output of digital video input or AD converter; One digital-to-analog converter, it has a simulation output and one and goes up the numeral that the numeral output of display unit links to each other with screen and import; And one extended out and be connected to the bypass of simulation output by a switch by analog video input.
2. video and graphic subsystem as claimed in claim 1 is characterized in that, also comprises second switch, and it has the input of the digital video of being connected to input and analog video input and is connected to the output that screen is gone up the display unit input.
3. video and graphic subsystem as claimed in claim 1 is characterized in that, comprises that also one is used to store the memory from the information of AD converter and digital-to-analog converter.
4. video and graphic subsystem as claimed in claim 3 is characterized in that, also comprises a microprocessor that is used to generate figure and stores memory into.
5. video and graphic subsystem as claimed in claim 4 is characterized in that, display unit receives figure and figure is mixed with the signal that is applied to its input on the screen.
6. video and graphic subsystem as claimed in claim 5 is characterized in that, the signal guide bypass that microprocessor was imported analog video in the time interval that does not need figure.
7. video and graphic subsystem comprises: an analog video signal that is used for receiving is converted to first conversion equipment of digital video signal; Be used for digital video signal is mixed with digital figure to form the insertion device of composite digital video signal; One is used for composite digital video signal is converted to second conversion equipment of composite analog video signal; And the shunting device that is used for bypass first conversion equipment, insertion device and second conversion equipment.
8. video and graphic subsystem as claimed in claim 7 is characterized in that shunting device comprises a by-pass switch.
9. video and graphic subsystem as claimed in claim 8 is characterized in that, by-pass switch can detect according to the demand of digital figure and control.
10. video and graphic subsystem as claimed in claim 9 is characterized in that, also comprises demand and control switch that a microprocessor is used to detect digital figure.
11. one kind is inserted the intermittently method of figure signal, comprises the steps: a) analog video signal to be converted to digital video signal in analog video signal; B) to the major general intermittently one of figure signal insert digital video signal to form a composite digital video signal; C) composite digital video signal is converted to composite analog video signal; And d) bypass step a, b and c in the time interval that does not have the figure signal at intermittence.
12. method as claimed in claim 11 is characterized in that, the step that also comprises the digitized representations that generates image is to form figure signal.
13. method as claimed in claim 12 is characterized in that, also is included in the step of this digitized representations of storage in the memory.
14. method as claimed in claim 13 is characterized in that, also is included in step b reads this digitized representations before from memory step.
A 15. video and graphic subsystem, it has screen and goes up demonstration insertion device, being used for a vision signal is digital signal from the dummy source conversion of signals, graphical information is mixed with this digital signal to form a composite signal, and this complex digital signal is converted to the analog video output signal that links to each other with display again, this subsystem is characterised in that: one has the bypass of gate-controlled switch, is used for the dummy source signal is directly connected to display.
16. video and graphic subsystem as claimed in claim 15 is characterized in that its bypass comprises a switch.
17. video and graphic subsystem as claimed in claim 15 is characterized in that its switch is controlled by a microprocessor, thereby bypass is inoperative in the time interval of graphical information needing, bypass is activated in the time interval that does not need graphical information.
18. video and graphic subsystem as claimed in claim 15 is characterized in that, comprises that also one is used for the memory of graphics information.
19. video and graphic subsystem as claimed in claim 18 is characterized in that, comprises that also one is used for generating graphical information and it is stored in the microprocessor of memory.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US1999/022305 WO2001024517A1 (en) | 1999-09-27 | 1999-09-27 | Graphics subsystem bypass method and apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1367979A true CN1367979A (en) | 2002-09-04 |
| CN1164093C CN1164093C (en) | 2004-08-25 |
Family
ID=22273689
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB99816920XA Expired - Fee Related CN1164093C (en) | 1999-09-27 | 1999-09-27 | Graphics subsystem bypass method and apparatus |
Country Status (6)
| Country | Link |
|---|---|
| CN (1) | CN1164093C (en) |
| AU (1) | AU6163599A (en) |
| BR (1) | BR9917505A (en) |
| DE (1) | DE19983982T1 (en) |
| GB (1) | GB2370444B (en) |
| WO (1) | WO2001024517A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296812C (en) * | 2003-07-08 | 2007-01-24 | 精工爱普生株式会社 | Graphics controller providing flexible access to a graphics display device by a host |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1527594B (en) * | 2003-02-21 | 2010-04-28 | Lg电子株式会社 | Apparatus and method for display image on display screen in mixed video equipment |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5541666A (en) * | 1994-07-06 | 1996-07-30 | General Instrument | Method and apparatus for overlaying digitally generated graphics over an analog video signal |
| CA2156871C (en) * | 1994-09-09 | 2005-04-05 | Thomas Patrick Newberry | Unified program guide interface |
| US5638112A (en) * | 1995-08-07 | 1997-06-10 | Zenith Electronics Corp. | Hybrid analog/digital STB |
| US6226047B1 (en) * | 1997-05-30 | 2001-05-01 | Daewoo Electronics Co., Ltd. | Method and apparatus for providing an improved user interface in a settop box |
-
1999
- 1999-09-27 GB GB0207050A patent/GB2370444B/en not_active Expired - Fee Related
- 1999-09-27 AU AU61635/99A patent/AU6163599A/en not_active Abandoned
- 1999-09-27 WO PCT/US1999/022305 patent/WO2001024517A1/en active Application Filing
- 1999-09-27 CN CNB99816920XA patent/CN1164093C/en not_active Expired - Fee Related
- 1999-09-27 DE DE19983982T patent/DE19983982T1/en not_active Withdrawn
- 1999-09-27 BR BR9917505-3A patent/BR9917505A/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1296812C (en) * | 2003-07-08 | 2007-01-24 | 精工爱普生株式会社 | Graphics controller providing flexible access to a graphics display device by a host |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2001024517A1 (en) | 2001-04-05 |
| GB2370444A (en) | 2002-06-26 |
| GB2370444B (en) | 2003-10-08 |
| BR9917505A (en) | 2002-06-04 |
| GB0207050D0 (en) | 2002-05-08 |
| DE19983982T1 (en) | 2002-12-05 |
| CN1164093C (en) | 2004-08-25 |
| AU6163599A (en) | 2001-04-30 |
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