CN1345089A - Semiconductor device with ideal grid contour and manufacture thereof - Google Patents
Semiconductor device with ideal grid contour and manufacture thereof Download PDFInfo
- Publication number
- CN1345089A CN1345089A CN 00135511 CN00135511A CN1345089A CN 1345089 A CN1345089 A CN 1345089A CN 00135511 CN00135511 CN 00135511 CN 00135511 A CN00135511 A CN 00135511A CN 1345089 A CN1345089 A CN 1345089A
- Authority
- CN
- China
- Prior art keywords
- layer
- floating gate
- oxide layer
- trench
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention relates to a method for manufacturing non-volatile memory device or other semiconductor device, including forming a silicon layer on a buffering oxide layer of semiconductor substrate. Barrier layer is formed, after a bufferong oxide layer being formed. Using following way forms the control grid electrode of conducting material. Channel is formed on upper part of substrate after composing a picture on silicon layer, oxide layer of grid electrode and substrate. The beaked part is produced on the upper and lower parts of the control grid electrode material via oxide channel sidewall. Its uniformity is realized by preventing positive slope of sidewall of float grid electrode for example. Then a field oxide layer is formed to fill in the channel.
Description
The present invention relates to a control gate, such as a floating gate in a memory device, and to a method of fabricating such a gate, but more particularly to a self-aligned shallow trench isolation technique that allows both a gate and an active region to be formed simultaneously.
During the fabrication of memory devices, the packing density of the memory cells is largely determined by the layout of the memory cells in the array and the physical dimensions of the memory cells themselves. At a design scale of half a micron, scalability is limited by the lithographic resolution achievable during manufacturing and by the positioning tolerances of the masks used in the production process. The positioning tolerances are in turn limited by the mechanical techniques used in forming the mask and the techniques used to align the mask between the multiple layers. Because positioning errors accumulate during multi-stage manufacturing, it is desirable to use as few masks as possible. Fewer masks may reduce the likelihood of misalignment. Therefore, in order to manufacture semiconductor devices, "self-alignment (overlay)" process steps have been developed.
Isolation structures, such as field oxides (fieldoxides), between individual memory cells in a memory cell array occupy areas of the chip that might otherwise be used for active circuitry. Therefore, in order to increase the packing density of memory cells and active circuits in a substrate, the size of isolation structures needs to be reduced. However, the dimensions of the isolation structures are typically determined by their formation process and/or the alignment process of such structures.
Usually, an isolation structure can be grown on different regions of the chip by a thermal field oxidation process, such as local oxidation of silicon (hereinafter referred to as "LOCOS"). According to the LOCOS method, after a filling oxide layer and a nitride layer are sequentially formed, the nitride layer is patterned. The silicon substrate is then selectively oxidized using the patterned nitride layer as a mask to form field oxide regions. However, in the case of LOCOS isolation, during selective oxidation of a silicon substrate, the growth of oxide attacks the sides of the filling oxide layer in the lower part of the nitride layer used as a mask, thereby creating a so-called bird's beak at the end of the field oxide layer. Due to the bird's beak shape, the field oxide layer extends to the active region of the memory cell, thus reducing the width of the active region. This phenomenon is undesirable because it can degrade the electrical performance of the memory device.
For this reason, shallow trench isolation (hereinafter referred to as "STI") structures are attractive in the fabrication of very large scale semiconductor devices. In the STI process, a silicon substrate is first etched to form a trench, and then an oxide layer is deposited to fill the trench. Thereafter, the oxide layer is etched by an etch back method or a Chemical Mechanical Planarization (CMP) method to form a field oxide layer within the trench.
The LOCOS and STI methods described above collectively include a masking step to define the area of the isolation structure on the substrate; and includes a step of forming a field oxide layer in those regions. After the isolation structure is formed, a step of forming a memory cell is performed. Thus, alignment errors associated with forming the isolation structures and memory cells accumulate to cause misalignment, which can lead to device failure.
In fabricating floating gates for non-volatile memory devices, for example, one method of mitigating misalignment includes using a self-aligned gate to form a LOCOS isolation structure, such as disclosed in U.S. patent 6,013,551 (to Jong Chen et al). According to the method described therein, a single mask can be used to simultaneously define and fabricate the floating gate and the active region so that alignment errors do not accumulate.
Non-volatile memory devices may be used in fast memory devices and have long term storage capabilities, e.g., almost indefinite storage capabilities. In recent years, the demand for such electrically programmable flash memory devices, such as EEPROMS, has increased. The memory cells of these devices typically have a vertically stacked gate structure including a floating gate formed on top of a silicon substrate. The multi-layer gate structure typically includes one or more tunnel oxide or dielectric layers over and/or around the floating gate and a control gate. In the flash memory cell having such a structure, data is stored by transferring electrons to or from the floating gate by applying a control voltage to the control gate and the substrate. The dielectric is used to maintain the potential on the floating gate.
Although the self-aligned STI process has the advantage of simultaneously forming the floating gate and the active region, it has disadvantages in that the aspect ratio of the gap formed during the process is increased, which may form a gap or a void in the trench during the gap filling process. In addition, when a high-concentration plasma (hereinafter, referred to as "HDP") oxide layer is used to fill the gaps, the edge portion of the polishing end-point detection layer under the HDP oxide layer gradually erodes during deposition of the HDP oxide layer, which undesirably forms a negative slope in the field oxide region. For this reason, during the subsequent gate etching, residues of the gate may be generated around the bottom of the inclined portion of the field region.
The above problem can be solved by: optimizing process conditions in the deposition process of the HDP oxide layer to improve the filling capacity of the gap; or a method may be used that eliminates the negative slope of the field regions by a wet etchant.
Fig. 1A to 1E are perspective views of a substrate, which in turn illustrate a method of fabricating a conventional fast memory device using self-aligned STI techniques.
Referring to fig. 1A, after a gate oxide layer (i.e., a tunnel oxide layer) 11 is formed on a silicon substrate 10, a first polysilicon layer 13 and a nitride layer 15 are sequentially formed on the gate oxide layer 11.
Referring to fig. 1B, a photolithography process is performed to pattern the nitride layer 15, the first polysilicon layer 13 and the gate oxide layer 11 to form a nitride layer pattern 16, a first floating gate 14 and a gate oxide layer pattern 12. Thereafter, the exposed portion of the substrate 10 is etched to a predetermined depth to form a trench 18. That is, the active region and the floating gate may be simultaneously determined using a single mask during the formation of the trench.
Referring to fig. 1C, the exposed portions of the trench 18 are heat treated in an oxygen ambient to cure silicon damage caused by energetic ion bombardment during the trench etch. Thus, a trench oxide layer 20 may be formed along the interior surfaces, including the bottom and sidewalls, of trench 18 by oxidation of the exposed silicon with an oxidizing agent.
In the above oxidation process, the oxidizing agent attacks the side of the gate oxide layer pattern 12 at the lower portion of the first floating gate 14, thereby forming bird's beak-shaped portions at both ends of the gate oxide layer pattern 12. Due to such bird's beak shaped portions, the bottom edge portion of the first floating gate 14 is bent outward while both end portions of the gate oxide layer pattern 12 are expanded, and the lower portion of the sidewall of the first floating gate 14 has a positive slope. Here, a positive slope indicates that such a slope allows the etchant to perform sidewall etching. In other words, as shown in the drawing, the intrusion of the oxidizer into the portion under the nitride layer pattern 16 is hindered by the presence of the nitride layer pattern 16, thereby forming a negative slope at the upper portion of the sidewall of the first floating gate 14. Meanwhile, the bottom edge portion of the lower portion of the first floating gate 14 is bent outward to have a positive slope, and it is corroded by the etchant introduced from the upper portion of the substrate in the same manner as the sidewall of the mesa structure, or functions as a barrier layer of the underlying layer when the etchant is used, which is undesirable.
Referring to fig. 1D, after an oxide layer (not shown) for filling the trench 18 is formed by a chemical vapor deposition (hereinafter, referred to as "CVD") method, the CVD oxide layer may be removed by a CMP process until the upper surface of the nitride layer pattern 16 is exposed. Thus, a field oxide layer 22, including the trench oxide layer 18, is formed within the trench 18.
After the nitride layer pattern 16 is removed by a phosphoric acid stripping process, a second polysilicon layer (not shown) is formed by depositing the same material as the first polysilicon layer 13 for constituting a second floating gate at the upper portion of the first floating gate 14 and the field oxide layer 22. The second polysilicon layer on the field oxide layer 22 is partially etched by a photolithography process to form a second floating gate 24 in a memory cell, which is separated from an adjacent memory cell. The second floating gate 24 is in electrical contact with the first floating gate 14 and has the function of increasing the area of the dielectric interlayer that will be formed in a subsequent process.
Thereafter, an ONO electrolyte interlayer 26 and a control gate layer 28 are sequentially formed over the entire surface of the formed structure. The control gate layer 28 is typically formed of a polysilicon silicide (polycide) structure obtained by stacking a doped polysilicon layer and a tungsten silicide layer.
In fig. 1E, the control gate layer 28 is patterned bya photolithography process. Next, the exposed electrolyte interlayer 26 and the second and first floating gates 24 and 14 are anisotropically etched by a dry etching process to complete the nonvolatile memory device.
At this time, as shown in a portion represented by a dotted line a in fig. 1D, the sidewall lower portion of the first floating gate 14 has a positive slope. Therefore, due to the anisotropic etching characteristic of the dry etching process (i.e., the etching is performed only in the vertical direction), the bottom edge portion of the first floating gate 14 masked by the field oxide layer 22 is not etched and remains intact. As a result, a line-shaped polysilicon residue 14a is formed along the surface boundary of the field oxide layer 22 and the active region. The polysilicon residue 14a forms a bridge between adjacent floating gates which can lead to electrical failure of the device.
It is therefore an object of the present invention to provide a method of fabricating a non-volatile memory or other device having a gate or other conductive structure of desired profile, such as a floating gate structure in a flash memory device, which avoids a positive slope on its sidewalls during formation.
In order to achieve the above aspects of the present invention, a self-alignment method of manufacturing a semiconductor device including a floating gate and an associated active region, and a corresponding semiconductor device, are provided. The floating gate and the active region are formed in a region of a substrate of the semiconductor memory device, which is at least partially defined by a field oxide region formed in the trench. A trench is formed with at least the first portion of the floating gate. The method comprises the following steps: an oxide layer is uniformly formed on sidewalls of the first portion of the floating gate by forming abuffer layer on the first portion of the gate before forming the trench, and then removing the buffer layer. This is achieved: a more uniform oxidation of the sidewalls of the first portion of the floating gate at least prior to disposing another portion of the conductive material on the first portion.
In another embodiment, a gate oxide layer is formed on a semiconductor substrate, a first conductive layer is formed on the gate oxide layer, and a buffer layer (e.g., an oxide layer) is formed on the first conductive layer. Thereafter, a barrier layer is formed over the buffer layer, and the barrier layer and the buffer layer are patterned to form a barrier layer pattern and a buffer layer pattern. Then, the first conductive layer and the gate oxide layer are patterned to form a floating gate layer as a first conductive layer pattern and a gate oxide layer pattern, and an upper portion of the substrate is etched to form a trench. The inner surface portion of the trench is oxidized to form a trench oxide layer along the inner surface of the trench and bird's beak shaped portions are formed at the upper and lower portions of the floating gate layer to prevent a positive (sloped) profile from being formed on the sidewalls of the patterned floating gate layer. Finally, a field oxide layer is formed to fill the trench.
Further, in order to achieve the above-described features of the present invention, a method of manufacturing a memory device is implemented by: a gate oxide layer is formed on a semiconductor substrate, a first conductive layer is formed on the gate oxide layer, and a buffer layer, such as an oxide layer, is formed on the first conductive layer. Then, a barrier layer is formed on the buffer layer. The barrier layer, the buffer layer, the first conductive layer, the gate oxide layer and the substrate are patterned using a single mask to form a floating gate from the first conductive layer. Also, a trench aligned with the floating gate is formed in the substrate adjacent to the floating gate to define an active area of the substrate. Thereafter, portions of the inner surface of the trench are oxidized to form a trench oxide layer along the inner surface of the trench and bird's beak shaped portions are formed on the upper and lower portions of the floating gate layer to prevent a positive (sloped) profile from being formed on the sidewalls of the patterned floating gate layer. Finally, a field oxide layer is formed to fill the trench.
In accordance with another aspect of the present invention, a buffer layer is formed between the floating gate layer and the nitride layer as an oxide mask layer to create bird's beak shaped portions in the upper and lower portions of the floating gate layer during the subsequent sidewall oxidation process. In this way, the bird's beak shaped portions can prevent the sidewalls of the floating gate layer from having a positive slope, which can prevent device failure caused by the residue of the gate during subsequent gate etching.
In addition to these methods, the present invention also includes floating gate semiconductor memory devices and elements thereof as defined by the appended claims.
The above features and other advantages of the present invention will become more apparent with reference to the embodiments described in conjunction with the accompanying drawings, in which:
FIGS. 1A to 1E illustrate a method of fabricating a fast memory device having self-aligned shallow trench isolation regions according to the prior art;
fig. 2A to 2I illustrate a method of manufacturing a floating gate of a nonvolatile memory device according to a first embodiment of the present invention;
fig. 3 is an enlarged sectional view showing a portion B in fig. 2D;
fig. 4A and 4B illustrate a method of fabricating a floating gate of a memory device according to a second embodiment of the present invention.
Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. The layers, structures or graphics described herein, whether on, laid down on, or overlaid on another layer, graphic or structure, are meant to include or not include intervening layers, graphics or structures.
Fig. 2A to 2I are perspective views illustrating a method of manufacturing a nonvolatile memory device according to a first aspect of the present invention.
Referring to fig. 2A, a silicon oxide layer or a silicon oxynitride layer is grown on a semiconductor substrate 100, which includes a semiconductor substrate made of silicon or the like, to form a gate oxide layer (e.g., tunnel oxide layer) 101 of the triode memory cell. When its surface is exposed and reacts with oxygen in the atmosphere, a native oxide layer is formed on the semiconductor substrate 100. Accordingly, the native oxide layer may be formed on the semiconductor substrate 100 by a known method not shown in the drawings. In the illustrated embodiment, gate oxide layer 101 is grown in an oxygen atmosphere to a thickness of about 10 to 500 angstroms, preferably 75 angstroms for low voltage semiconductor devices and 300 angstroms for high voltage semiconductor devices, excluding the native oxide layer.
The first silicon layer 103 is formed on the gate oxide layer 101 by LPCVD to be used as a floating gate, and has a thickness of about 200 to 1500 angstroms, preferably 500 angstroms. Then, by a typical doping method, such as POCl3Layer 103 is doped with a high concentration of N-type impurities by methods such as diffusion, ion implantation, or in-situ doping. The silicon layer 103 is preferably formed of polysilicon or amorphous silicon. The silicon layer 103 is then exposed to an oxygen atmosphere to form a native oxide layer (not shown) having a thickness of about 30 to 35 angstroms.
A buffer layer 105 is then formed on the first silicon layer 103 to a thickness of about 10 to 500 angstroms, which is approximately the same as the thickness of the gate oxide layer 101 (excluding the native oxide layer thickness). The buffer layer 105 may be an oxide layer that may be formed by thermal oxidation or plasma enhanced chemical vapor deposition (PE-CVD). In addition, the buffer layer 105 may be formed by partially oxidizing the surface of the silicon layer 103, which may be formed by using an oxidizing gas such as oxygen (O) gas2) Or dinitrogen monoxide (N)2O) performing plasma treatment. A buffer material other than oxide is also contemplated by the present invention as long as it can prevent irregular formation of the gate or can achieve flatness or planarity of the first or other portion edges and/or sidewalls of the gate during formation of the trench. As noted above, the floating gate may deform or have an undesirable positive slope when no buffer material is used prior to trench oxidation.
An etch stop layer 107 is formed on the buffer oxide layer 105 to a thickness of about 100 to 3000 angstroms, preferably 1500 angstroms, by LPCVD. The barrier layer 107 serves as an endpoint detection layer in a subsequent CMP process or etch back process. The barrier layer 107 covers the buffer oxide layer 105 in a subsequent trench thermal oxidation process to help prevent oxygen and oxidizing agents from invading the first silicon layer 103 through the buffer oxide layer 105. Accordingly, the blocking layer 107 is preferably formed of a material having oxidation-resistant properties, such as a nitride, e.g., SiN, SiON or BN.
The barrier layer 107 may be formed of polysilicon. In this case, the barrier layer 107 is partially oxidized during a subsequent oxidation process. However, the barrier layer 107 may also be used as an endpoint detection layer in an etch back or CMP process.
An anti-reflective layer may optionally be formed over the barrier layer 107 by CVD methods to precisely align the subsequent photolithography process. Such an anti-reflection layer may be formed of polysilicon, silicon oxides such as high temperature oxides and medium temperature oxides, or silicon oxynitride (SiON). The antireflective layer may be composed of a single layer or multiple layers.
In the present invention, a double layer of a high temperature oxide (hereinafter referred to as "HTO") layer 140 and a SiON layer 150 is used as an anti-reflective layer. The HTO layer 140 and the SiON layer 150 may be simply formed by well-known CVD methods and serve as anti-reflective layers to prevent light from reflecting from the underlying substrate during the photolithography process. The HTO layer 140 is formed to a thickness of about 200 to 2000 angstroms, preferably 500 angstroms, and the SiON layer 150 is formed to a thickness of about 200 to 3000 angstroms, preferably 800 angstroms.
Referring to fig. 2B, a photoresist is coated on the SiON layer 150 by a spin coating method to form a photoresist film (not shown). Thereafter, a photoresist pattern 160, which defines the layout of the floating gate electrode, is formed by exposing and developing the photoresist film using a photomask.
The photoresist pattern 160 may be used as an etching mask to sequentially etch the SiON layer 150, the HTO layer 140, the barrier layer 107, and the buffer oxide layer 105. Thus, as shown in the figure, a pattern composed of the SiON layer pattern 151, the HTO layer pattern 141, thebarrier layer pattern 108 and the buffer oxide layer pattern 106 is formed. Then, the photoresist pattern 160 is removed through an ashing or stripping process.
Referring to fig. 2C, the formed structure is moved to another etch chamber to perform an etch process on the polysilicon and oxide. Here, an etching gas for etching polysilicon is introduced to etch the first silicon layer 103, thereby forming a first silicon layer pattern 104. The first silicon layer pattern 104 formed at this time may be used as a first floating gate of a nonvolatile memory device.
Next, in the same etch chamber, the gate oxide layer 101 is etched to form a gate oxide pattern 102 and the substrate 100 is etched to a depth of about 1000 to 5000 angstroms, preferably 2700 angstroms, to form a trench 109. As a result, the floating gates defined by the silicon layer pattern 104 are isolated from each other by the trench 109.
During the etching of the silicon layer pattern 104 and the upper portion of the semiconductor substrate 100, the SiON layer pattern 151 and the HTO layer pattern 141 formed on the barrier layer pattern 108 are removed.
By forming trenches 109, both the active area and the floating gate can be simultaneously defined with a single mask. Thus, the floating gate is self-aligned with the active region.
Referring to fig. 2D, the inner surface portion of the trench 109 is treated in an oxidizing atmosphere to eliminate damage caused by high energy ion bombardment during trench etching and to prevent leakage current during device operation. A trench oxide layer 110 is then formed along the interior surfaces of trench 109, i.e., on the bottom and sidewalls thereof, to a thickness of about 10 to 500 angstroms, preferably 30 to 40 angstroms. The trench oxide layer 110 may be formed using a dry oxidation process under the condition of nitrogen N2And oxygen O2At a temperature of from 800 to 950 ℃; or by a wet oxidation process at a process temperature of at least 700 deg.c.
As is well known in the art, the reaction to form the oxide layer is as follows:
as can be seen from the above reaction, since the diffusion of oxygen into the layer having the Si source of silicon realizes the oxidation of silicon, an oxide layer is grown on the surface of the silicon layer pattern 104 and the surface of the trench 109.
Fig. 3 is an enlarged sectional view showing a portion B of fig. 2D.
In forming the trench oxide layer 110, as shown in fig. 3, an oxidizer (or oxidizing gas) intrudes into the side of the gate oxide layer pattern 102 at the lower portion of the silicon layer pattern 104, thereby forming a first bird's beak-shaped part "a". Meanwhile, the oxidizing agent intrudes into the side of the buffer oxide layer pattern 106 at the lower portion of the barrier layer pattern 108, thereby forming a second bird's beak shaped part "b" at the upper portion of the first polysilicon layer pattern 104.
According to the conventional method shown in fig. 1C, the bird's beak-shaped part is generated only in the lower portion of the silicon pattern used as the floating gate. The lower portion of the gate sidewall exhibits a positive slope as the oxide grown at the bottom edge portion of the floating gate expands during oxidation. In contrast, in the present invention, the first bird's beak shaped part "a" and the second bird's beak shaped part "b" are formed at the lower and upper portions of the sidewall of the gate electrode at the same time. Thus, the bottom edge portion of the gate sidewall is not bent outward. In other words, the second bird's beak shapedpart "b" is formed at the same time as the upper portion of the first silicon layer pattern 104, preventing a positive slope which would otherwise occur. Thus, in accordance with an important aspect of the present invention, the floating gate formed in the silicon layer pattern 104 has a desired profile.
Referring to FIG. 2E, an oxide layer 112 with good gap-filling properties, such as USG (undoped silicate glass), O, is deposited by CVD process3A TEOS (tetraethylorthosilicate) USG or HDP oxide layer with a thickness of about 5000 angstroms to fill trench 109. The High Density Plasma (HDP) oxide layer 112 is preferably SiH4、O2Ar or He gas is deposited as a plasma source.
The trench 109 is filled by increasing the gap filling capability of the HDP oxide layer 112 to prevent voids or voids from being created in the trench 109.
During the formation of the HDP oxide layer 112, the deposition of the oxide layer and the sputter etching of the oxide layer are performed simultaneously. Thus, when it is deposited in a wide area at a constant rate, the deposition rate and the sputter etching rate become equal after a narrow area is deposited to a predetermined thickness, so that the oxide does not continue to be deposited. If the sputter etch capability is increased to improve the gap-filling performance of the HDP oxide layer 112, the edge portion of the nitride-containing barrier layer pattern 108 is etched to make the field oxide layer have a negative slope. To prevent this problem, a method of eliminating the negative slope of the field oxide layer may be implemented by changing the deposition conditions or using a wet etchant in forming the barrier layer 108.
Then, by using Si (OC)2H5)4As a plasma method of the ion source, a capping oxide layer (not shown) composed of PE-TEOS (plasmaenhanced TEOS) is deposited on the HDP oxide layer 112.
The HDP oxide layer 112 may optionally be densified by annealing at a high temperature of about 800 to 1050 c in an inert gas atmosphere to reduce the wet etch rate in a subsequent cleaning process.
Referring to fig. 2F, the HDP oxide layer 112 is planarized. The planarization is performed by an etch back or CMP process until the upper surface of the barrier layer pattern 108 is exposed. In this way, the HDP oxide layer 112 on the barrier layer may be partially removed to create field oxide isolation in the trench 109.
Referring to fig. 2G, the barrier layer pattern 108 including silicon nitride is removed through a lift-off process using phosphoric acid. At this time, the buffer oxide layer pattern 106 may prevent damage to the underlying silicon layer pattern 104 during the removal of silicon nitride through a lift-off process, the silicon layer pattern 104 being a first floating gate electrode made of silicon.
Thereafter, a pre-cleaning step is performed, and the substrate is subjected to a cleaning process using an etchant containing a fluorine acid for about 30 seconds. The field oxide layer 124 is partially removed by the lift-off preventing layer 108 and the pre-cleaning process, and the buffer oxide layer pattern 106 formed on the silicon layer pattern 104 is also removed. At this time, the thickness of the field oxide layer 124 is reduced by more than about 250 angstroms.
Referring to fig. 2H, a second silicon layer (not shown), such as a polysilicon layer or an amorphous silicon layer, is deposited on the exposed first silicon layer pattern 104 and on the field oxide layer 124 (fig. 2G) by a well-known method, for example, by a Chemical Vapor Deposition (CVD) method, to a thickness of about 2000 a by an LPCVD method. During the formation of the conductive silicon layer pattern 104,dopants or the like are typically includedAnd (c) other charge carriers. The second silicon layer thus deposited is in electrical contact with the first silicon layer pattern 104, the first silicon layer pattern 104 being a first floating gate. Subsequently, by typical doping methods, e.g. POCl3Diffusion, ion implantationThe second floating gate 126 is doped with a high concentration of N-type impurities by an in-situ doping method, thereby forming a second conductive layer.
Further, the second conductive layer may be formed in this manner without performing a separate doping process: in forming the second silicon layer, doped polysilicon is deposited by performing a CVD process while impurities are added to the source gases. In order to increase the area of the electrolyte interlayer formed in the subsequent process, a second floating gate electrode composed of a second conductive layer is formed, the thickness of which should be formed as large as possible.
Thereafter, the second conductive layer on the field oxide layer 124 is partially removed by a conventional photolithography process to form a second silicon layer pattern 126, which constitutes a second portion of the floating gate. Next, the second floating gate thus formed is separated from the adjacent memory cell.
Thereafter, a dielectric interlayer 128 composed of ONO is formed on the entire surface of the formed structure so as to completely isolate the second silicon pattern 126 as a second floating gate. For example, after the second floating gate 126 is oxidized to grow a first oxide layer having a thickness of about 100 angstroms, a nitride layer having a thickness of about 130 angstroms is deposited thereon, and a second oxide layer having a thickness of about 40 angstroms is deposited on the nitride layer, thereby forming a dielectric interlayer 128 having a total thickness of about 100 to 200 angstroms.
Next, a control gate layer 130, which is a third conductive layer and is formed by stacking an N layer, is formed on the dielectric interlayer 128+Type-doped polycrystalline silicon layer and a metal silicide layer, such as tungsten silicide WSixTitanium silicide TiSixCobalt silicide CoSixAnd tantalum silicide TaSix. The polysilicon layer of control gate layer 130 is preferably formed to a thickness of about 1000 angstroms and the metal silicide layer thereof is preferably formed to a thickness of about 100 to 1500 angstroms.
Referring to fig. 2I, after the control gate layer 130 is patterned by a photolithography process, the exposed dielectric interlayer 128, the second floating gate portion 126, and the first floating gate portion 104 are sequentially patterned within each memory cell by a dry etching method, thereby forming stacked floating gate memory cells. At this time, dry etching is performed in a specific region until the upper surface of the substrate 100 between the field oxide layers 124 is exposed.
Since the sidewall of the first silicon layer pattern 104, which is the first floating gate, does not have a positive slope, the sidewall portion of the first silicon layer pattern 104 is not deformed, and there is no portion bent outward. Accordingly, in the above dry etching process, the portion of the first silicon layer pattern 104 exposed by the mask pattern is completely removed. Therefore, silicon residue does not remain on the surface boundary between the field oxide layer 124 and the active region.
Thereafter, although not shown in the drawings, source/drain regions of the memory cell are formed by ion implantation, and then an interlayer insulating layer ILD is coated on the formed structure. After forming contact holes for exposing the source/drain regions by etching the interlayer insulating layer, contact plugs for filling the contact holes are formed. Then, a metal layer in electrical contact with the metal plug is deposited, and a back-end process is performed using an inter-layer insulating layer IMD through a metal mask.
The processes of the first embodiment, as shown in fig. 2B and 2C, are performed in separate etching chambers, respectively, but they may be performed continuously in a single etching chamber, thereby forming the second embodiment. The second embodiment is the same as the first embodiment except that an anti-reflection layer is not formed and the substrate etching process is performed in a single etching chamber using a photoresist as an etching mask. Here, the same reference numerals as in the first embodiment are used to denote the same members.
Fig. 4A and 4B are sectional views showing a method of manufacturing a nonvolatile memory device according to a second embodiment of the present invention.
Referring to fig. 4A, a gate oxide layer 101, a first silicon layer 103, a buffer oxide layer 105, and a stopper layer 107 are sequentially formed on a substrate 100 in the same manner as in the first embodiment.
Referring to fig. 4B, a photoresist pattern 160 is formed on the barrier layer 107 using a kind of photomask for defining a floating gate, just as in the first embodiment. Then, the barrier layer 107, the buffer oxide layer 105, the first silicon layer 103 and the gate oxide layer 101 are patterned using the photoresist pattern 160 as an etching mask, thereby forming a pattern structure consisting of the barrier layer pattern 108, the buffer oxide layer pattern 106, the first silicon layer pattern 104 and the gate oxide layer pattern 102.
Next, the substrate 100 is etched to form the trench 109, and an ashing or stripping process is performed to remove the photoresist pattern 160.
Thereafter, the processes shown in fig. 2C to 2I in the first embodiment are performed, thereby providing a floating gate nonvolatile memory device according to the second aspect of the present invention.
According to the present invention as described above, a buffer oxide layer is additionally formed between the first portion of the floating gate layer and the barrier layer, thereby creating a bird's beak-shaped portion at the upper portion of the floating gate. The bird's beak shaped portions at the upper and lower portions of the first portion of the floating gate flatten or planarize the sidewall portions of the floating gate during the subsequent oxidation of the trench sidewalls. This prevents undesired tilting of the sidewalls of the floating gate layer and results in a non-volatile memory device having a gate with a desired profile.
In addition, after dry etching for forming a gate electrode later, a silicon residue does not remain. The absence of such residues will help to avoid electrical failure of the device caused by shorts between adjacent gates.
It is apparent that the present invention can be applied to the formation of other conductive layers in a semiconductor device, which have requirements for uniformity, in addition to the uniform formation of a floating gate layer. In other words, the invention can be applied in any case where it is necessary to avoid the phenomenon of the beak-shaped parts.
While the invention has been particularly shown and described with reference to the illustrated embodiments, it will be understood by those skilled in the art that: various changes in form and detail may be made without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (45)
1. In a self-aligned method of fabricating a conductive layer and corresponding active region in a region of a substrate of a semiconductor device, the region being at least partially defined by a field oxide region formed within a trench in the substrate and formed with at least a first portion of a control gate formed over the substrate and a first dielectric material, a method of forming an oxide planarly on sidewalls of the first portion comprising:
a buffer layer is formed on the first portion of the control gate prior to forming the trench and is subsequently removed to achieve more uniform oxidation of the sidewalls of the first portion before at least laying another portion over the first portion of the control gate.
2. The method of claim 1, wherein the first portion comprises at least one of polysilicon and amorphous silicon.
3. The method of claim 1, wherein the buffer layer is an oxide formed by thermal oxidation.
4. The method of claim 1, wherein the buffer layer is formed by plasma enhanced chemical vapor deposition.
5. The method of claim 1, wherein the buffer layer is formed by oxidizing a surface of the first portion of the control gate electrode by plasma treatment of an oxidizing gas.
6. The method of claim 5, wherein the oxidizing gas comprises one of oxygen and nitrous oxide.
7. The method of claim 1, wherein the buffer layer is formed to a thickness of 10 to 500 angstroms.
8.In a self-aligned method of forming a floating gate and associated active region in a substrate of a semiconductor memory device, a method comprising:
forming a gate oxide layer on a substrate;
forming a first conductive layer on the gate oxide layer;
forming a buffer oxide layer on the first conductive layer;
forming a barrier layer on the buffer oxide layer;
patterning the barrier layer and the buffer oxide layer to form a barrier layer pattern and a buffer oxide layer pattern;
patterning the first conductive layer to form a floating gate layer as a first conductive layer pattern, and etching the gate oxide layer and an upper portion of the substrate to form a gate oxide layer pattern and a trench;
oxidizing an inner surface portion of the trench to form a trench oxide layer on the inner surface of the trench and bird's beak shaped portions on upper and lower portions of the floating gate layer to prevent a positive (sloped) profile from being formed on sidewalls of the patterned floating gate layer; and
a field oxide layer is formed to fill the trench.
9. The method of claim 8, wherein the first conductive layer comprises one of polysilicon and amorphous silicon.
10. The method of claim 8, wherein the material of the barrier layer comprises a nitride composition.
11. The method of claim 8, wherein the buffer oxide layer is formed by thermal oxidation.
12. The method of claim 8, wherein the buffer oxide layeris formed by plasma enhanced chemical vapor deposition.
13. The method according to claim 8, wherein the buffer oxide layer is formed by oxidizing a surface of the first conductive layer by plasma treatment of an oxidizing gas.
14. The method of claim 13, wherein the oxidizing gas comprises at least oxygen (O)2) And nitrous oxide (N)2O).
15. The method of claim 8, wherein the buffer oxide layer is formed to a thickness of 10 to 500 angstroms.
16. The method of claim 8 wherein the field oxide layer is formed by: forming an oxide layer covering the oxidized barrier layer while filling the trench, and etching the oxide layer by at least one of a chemical mechanical polishing method and an etch back method until a surface of the barrier layer pattern is exposed, thereby obtaining a flat surface.
17. The method of claim 8, further comprising forming an anti-reflective layer on the barrier layer by chemical vapor deposition.
18. The method of claim 17, wherein the anti-reflective layer comprises at least one material selected from the group consisting of: polysilicon, silicon nitride, silicon oxynitride, and silicon oxide.
19. The method as claimed in claim 17, wherein, after forming a photoresist pattern for forming the floating gate on the anti-reflection layer in the first etching chamber, the anti-reflection layer, the blocking layer and the buffer oxide layer are patterned by using the photoresist pattern asan etching mask, and the photoresist pattern is removed; and then, in a second etching chamber, forming a first conductive layer pattern, a gate oxide layer pattern and a trench while removing the anti-reflection layer pattern.
20. The method of claim 17, wherein after forming a photoresist pattern for forming the floating gate on the barrier layer, an etching process is sequentially performed in a single etching chamber by using the photoresist pattern as an etching mask to pattern the barrier layer, the buffer oxide layer, the first conductive layer, and the gate oxide layer; an upper portion of the substrate is etched to form a barrier layer pattern, a buffer oxide layer pattern, a first conductive layer pattern, a gate oxide layer pattern, and a trench.
21. A method of fabricating a floating gate structure of a non-volatile memory device, comprising:
forming a gate oxide layer on a semiconductor substrate;
forming a first conductive layer on the gate oxide layer;
forming a buffer layer on the first conductive layer;
forming a barrier layer on the buffer layer;
patterning the barrier layer, the buffer oxide layer, the first conductive layer, the gate oxide layer and the substrate using a single mask to form a floating gate from the first conductive layer and simultaneously forming a trench aligned with and adjacent to the floating gate in the substrate to define an active region of the substrate;
oxidizing an inner surface portion of the trench to form a trench oxide layer on the inner surface of the trench and bird's beak shaped portions on upper and lower portions of the floating gate layer to prevent a positive (sloped) profile from being formed on sidewalls of the patterned floating gate layer;
a field oxide layer is formed to fill the trench.
22. The method of manufacturing a memory device of claim 21, wherein the first conductive layer comprises at least one of polysilicon and amorphous silicon.
23. The method of fabricating a memory device of claim 21, wherein the barrier layer comprises a nitride composition.
24. The method of fabricating a memory device of claim 21, wherein the buffer layer comprises a thermally oxidized oxide.
25. The method of manufacturing a memory device of claim 21, wherein the buffer layer is formed by plasma enhanced chemical vapor deposition.
26. The method of manufacturing a memory device according to claim 21, wherein the buffer layer is formed by oxidizing a surface of the first conductive layer by surface plasma treatment with an oxidizing gas.
27. The method of manufacturing a memory device of claim 26, wherein the oxidizing gas comprises oxygen (O)2) And nitrous oxide (N)2O).
28. The method of manufacturing a memory device of claim 21, wherein the buffer layer is formed to a thickness of 10 to 500 angstroms.
29. The method of manufacturing a memory device of claim 21, further comprising: flattening the field oxide layer by using the surface of an anti-oxidation layer; removing the patterned blocking layer; after the field oxide layer is formed, a dielectric interlayer and a control gate are sequentially formed on the floating gate.
30. The method of manufacturing a memory device of claim 21, further comprising forming an anti-reflective layer on the barrier layer by chemical vapor deposition.
31. The method of manufacturing a memory device of claim 30, wherein the anti-reflective layer comprises at least one material selected from the following materials: polysilicon, silicon oxynitride, and silicon oxide.
32. A floating gate semiconductor memory device comprising a substrate, an insulating layer and a floating gate over the insulating layer, wherein the floating gate is at least partially defined by field oxide regions formed in a trench in the substrate with formation of the floating gate, and wherein, prior to forming the trench, a buffer layer is formed over a first portion of the floating gate, the buffer layer being removed after forming the first portion to allow at least a second portion of the floating gate to be formed, whereby more uniform oxidation of upper and lower portions of sidewalls of the first portion is achieved before laying the second portion over the first portion of the floating gate.
33. The floating gate semiconductor memory device of claim 32, wherein the first portion of the floating gate comprises at least one of polysilicon and amorphous silicon.
34. The floating gate semiconductor memory device according to claim 32, wherein the buffer layer is an oxide formed by thermal oxidation.
35. The floating gate semiconductor memory device according to claim 32, wherein the buffer layer is formed by plasma enhanced chemical vapor deposition.
36. The floating gate semiconductor memory device according to claim 32, wherein the buffer layer is formed by oxidizing a surface of the first portion of the floating gate by plasma treatment of an oxidizing gas.
37. The floating gate semiconductor memory device of claim 36, wherein the oxidizing gas comprises one of oxygen and nitrous oxide.
38. The floating gate semiconductor memory device according to claim 32, wherein the buffer layer is formed to a thickness of 10 to 500 angstroms.
39. A self-aligned floating gate for a semiconductor memory device and associated active region, comprising:
a semiconductor substrate;
a gate oxide layer formed on the substrate;
a first conductive layer formed on the gate oxide layer, which constitutes a first portion of the floating gate;
the first conductive layer is formed by: disposing a buffer layer on the first conductive layer; a barrier layer formed on the buffer layer; patterning the barrier layer and the buffer layer to form a barrier layer pattern and a buffer layer pattern; patterning the first conductive layer to form a first portion of the floating gate layer; etching the gate oxide layer and the upper portion of the substrate to form a gate oxide layer pattern and a trench; oxidizing the inner surface of the trench to form a trench oxide layer on the inner surface of said trench, which in turn forms bird's beak shaped portions on theupper and lower portions of the first portion of the floating gate layer, thereby planarizing the sidewalls of the first portion of the floating gate during the formation of the trench oxide layer;
a field oxide layer formed in the trench after oxidation of an inner surface of the trench; and
a second portion of the floating gate is in electrical contact with the first portion after planarizing the field oxide layer until the first portion is exposed.
40. The self-aligned floating gate and associated active region of claim 39, wherein the first portion of the floating gate comprises at least one of polysilicon and amorphous silicon.
41. The self-aligned floating gate and associated active region of claim 39, wherein the buffer layer is formed by thermal oxidation.
42. The self-aligned floating gate and associated active region of claim 39, wherein the buffer layer is formed by plasma enhanced chemical vapor deposition.
43. The self-aligned floating gate and associated active region of claim 39, wherein the buffer layer is formed by oxidizing a surface of the first portion of the floating gate by plasma treatment with an oxidizing gas.
44. The self-aligned floating gate and associated active region of claim 43, wherein the oxidizing gas comprises one of oxygen and nitrous oxide.
45. The self-aligned floating gate and associated active region of claim 39, wherein the buffer layer is formed to a thickness of 10 to 500 angstroms.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001355112A CN1193420C (en) | 2000-09-20 | 2000-09-20 | Semiconductor device with ideal grid contour and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB001355112A CN1193420C (en) | 2000-09-20 | 2000-09-20 | Semiconductor device with ideal grid contour and manufacture thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1345089A true CN1345089A (en) | 2002-04-17 |
| CN1193420C CN1193420C (en) | 2005-03-16 |
Family
ID=4596752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001355112A Expired - Lifetime CN1193420C (en) | 2000-09-20 | 2000-09-20 | Semiconductor device with ideal grid contour and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1193420C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7115940B2 (en) | 2003-01-29 | 2006-10-03 | Renesas Technology Corp. | Semiconductor device |
| CN100435282C (en) * | 2003-03-18 | 2008-11-19 | 华邦电子股份有限公司 | Method for producing flash storage float grid |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7358140B2 (en) * | 2005-11-04 | 2008-04-15 | International Business Machines Corporation | Pattern density control using edge printing processes |
-
2000
- 2000-09-20 CN CNB001355112A patent/CN1193420C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7115940B2 (en) | 2003-01-29 | 2006-10-03 | Renesas Technology Corp. | Semiconductor device |
| CN1330000C (en) * | 2003-01-29 | 2007-08-01 | 株式会社瑞萨科技 | Semiconductor device |
| US7355242B2 (en) | 2003-01-29 | 2008-04-08 | Renesas Technology Corp. | Semiconductor device |
| CN100435282C (en) * | 2003-03-18 | 2008-11-19 | 华邦电子股份有限公司 | Method for producing flash storage float grid |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1193420C (en) | 2005-03-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6620681B1 (en) | Semiconductor device having desired gate profile and method of making the same | |
| US6548374B2 (en) | Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device comprising the same | |
| KR100476691B1 (en) | Method for Shallow Trench Isolation and Method of manufacturing Non-Volatile Memory Device comprising the same | |
| US20060017093A1 (en) | Semiconductor devices with overlapping gate electrodes and methods of fabricating the same | |
| KR100645458B1 (en) | Method for fabrication of semiconductor device capable of protecting attack by wet cleaning | |
| US20020072197A1 (en) | Method for self-aligned shallow trench isolation and method of manufacturing non-volatile memory device using the same | |
| KR100341480B1 (en) | Method for self-aligned shallow trench isolation | |
| US20120007184A1 (en) | Semiconductor device and method of fabricating the same | |
| JP4015369B2 (en) | Semiconductor device having desirable gate profile and manufacturing method thereof | |
| JP5093945B2 (en) | Manufacturing method of flash memory cell | |
| KR20050049254A (en) | Method for fabrication of semiconductor device | |
| KR100717812B1 (en) | Method for manufacturing semiconductor device | |
| US7101803B2 (en) | Method of trench isolation and method for manufacturing a non-volatile memory device using the same | |
| US20080003799A1 (en) | Method for forming contact plug in semiconductor device | |
| CN1193420C (en) | Semiconductor device with ideal grid contour and manufacture thereof | |
| US20080305595A1 (en) | Methods of forming a semiconductor device including openings | |
| US6562682B1 (en) | Method for forming gate | |
| KR100523920B1 (en) | Method of manufacturing a flash device | |
| KR100670916B1 (en) | Method for Self-Aligned Shallow Trench Isolation and Method of manufacturing Non-Volatile Memory Device comprising the same | |
| CN110416218B (en) | Method for manufacturing memory element | |
| US6967151B2 (en) | Method of manufacturing a semiconductor device | |
| KR20020095690A (en) | Method of manufacturing flash memory device | |
| CN1542919A (en) | Semiconductor structure with partial etching grid and making method thereof | |
| US20090004854A1 (en) | Method of Fabricating Flash Memory Device | |
| KR20070014407A (en) | Method of forming a gate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20050316 |