CN1339821A - 倒装片式接合芯片与载体的封合结构 - Google Patents
倒装片式接合芯片与载体的封合结构 Download PDFInfo
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- CN1339821A CN1339821A CN 00123593 CN00123593A CN1339821A CN 1339821 A CN1339821 A CN 1339821A CN 00123593 CN00123593 CN 00123593 CN 00123593 A CN00123593 A CN 00123593A CN 1339821 A CN1339821 A CN 1339821A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
一种倒装片式接合芯片与载体的封合结构,是以倒装片式技术在载体贴上芯片,并再以芯片复合后予以封合的结构,其主要是由载体、母芯片及子芯片所组合构成,载体提供芯片承载的基础,一般使用的载体为导线架或基底,以扁平封装方式贴一芯片在载体上,再用一长有凸块的芯片,以倒装片式方式贴附在芯片上,同时跨贴在载体上,以载体、芯片、另一芯片重叠的方式形成封装。
Description
本发明涉及一种倒装片式接合于一承载有芯片的载体的封装技术。
有关半导体集成电路(lntegrated Circuit,IC)的封装(Packaging)技术的演进,一般是跟随着IC设计及制造而进化;随着IC技术的发展,集成度逐渐升高,而导体出入部的插脚数(信号、电源、接地)也增加,且有将更多的功能整合于单一芯片和缩小芯片尺寸的趋势。因此,传统电子构造的封装技术将不足以满足先进体集成电路IC发展的需求,各厂商纷纷采用更合适的封装技术,如倒装片式(flip chip)技术、球栅阵列接脚(Ball GridArray,BGA)、芯片尺寸封装(Chip Size/Scale Package,CSP)、多芯片模组(Multi Chip Module)等。
为了提高处理速度,厂商在实际制作上采用组合封装,即(如图1所示)在一载体(Base)11上,例如导线架(Lead frame)110上先贴好一母芯片(Chip)12,并利用金(Au)线121打线(Wire Bonding),使母芯片12与导线架110导通,又以倒装片技术在母芯片12的顶层复盖以另一个子芯片13,最后,再以合成树脂(Molding Compound)14将整体封装(Packaging)成一个模组(Module)。但是,上述的组合封装虽然可以适度改善一些信号交换速度,但整体的封装模组过大,即使该金线采用低回路(LOOP)键合设计,其体积仍过于臃肿,对可携式电子产品的轻、薄、短小、及省电需求而言,其厚薄尚无法达到要求。
本发明的目的是提供一种可以解决上述缺陷的倒装片式接合芯片舆载体的封合结构。
本发明的目的是这样实现的:一种倒装片式接合芯片与载体的封合结构,是以倒装片式技术在载体贴上芯片,并再以芯片复合后予以封合的结构,以增加信号传送速度,并有效降低封装高度;其特征在于:主要是由载体、母芯片及子芯片所组合构成,载体提供芯片承载的基础,并以表面贴着的扁平封装方式贴一芯片在载体上,再用一长有凸块的芯片,以倒装片式方式贴附在芯片上,同时跨贴在载体,以载体、芯片、另一芯片重叠的方式形成封装。
上述的载体为导线架的形式。
上述的载体为集成电路板基底。
上述的载体为一多层组合式的基底:先在底层基底上叠一基底,并在第二层基底切有一预留嵌贴母芯片的通孔;再铺上一层最上层的基底,并在同样位置预留一通孔,各层基底组成一阶梯形断面,使母芯片贴在最底层基底上,另将子芯片以倒装片式技术贴在母芯片上层,且子芯片并以外围的凸块贴在第二层基底上,使整体最底层基板、母芯片、子芯片所组成的封装高度比该三层组合基底的总厚度为低。
本发明可以在作为载体的导线架(Lead Frame)或基底(Substrate)上贴母芯片,再以倒装片式接合另一子芯片于母芯片上,使载体、母芯片舆倒装片式子芯片整体并予以封合,依此发明技术实施后,因子芯片与母芯片、子芯片与载体之间都是采用信号传递距离最短的倒装片式技术,使得构装装置本身的电感变小,进而提高整体执行速度,且倒装片式接合只需小面积的接合,可有效减低整体封装的厚度,并可使该模组局部高密度化,缩小配线延迟,使得能够高速传送信号。
下面配合简单附图和较佳实施例说明本发明的上述目的、特征及优点:
图1是传统技术的导线架封装结构剖视图。
图2是本发明的导线架载体结构剖视图。
图3是本发明的基底载体结构剖视图
图4是本发明的多层组合式基底载体结构剖视图。
如前所述,本发明使用倒装片式技术在载体贴上芯片,并再以芯片复合后予以封合的结构,以增加信号传送速度,并有效降低封装高度。
请参见图2所示,本发明是一种倒装片式接合芯片与载体的封合结构,主要是由载体(Base)、贴附芯片及倒装片式芯片所组合,其中载体为导线架(Lead Frame)211,以提供各芯片承载的基础,并以表面贴着的扁平封装(Flat Package)方式贴一母芯片22在导线架211上,再用一长有凸块的子芯片23,以倒装片式方式贴附在母芯片22之上,同时跨贴在导线架211上,以导线架211的载体21、母芯片22、另一子芯片23重叠的方式形成封装。上述所指的载体21也可如图3所示的另一种方式来实施,其载体31为基底(Substrate)311的形式:一般有聚醯亚铵薄膜(Polyimide film)、叠层电路板(Laminate)等方式,以提供各芯片承载的基础,而将基底对外电气连接的锡球(Solder ball)25设置在基底底部。
另外,本发明的载体也可为一多层式的基底411,如图4所示,先将第一层基底(Substrate)4111铺在最底层,再依需要叠一基底4112,并在第二层基底4112切有一预留嵌贴母芯片42的通孔;再铺上一层最上层的基底4113,并在同样位置预留一通孔,各层基底4111、4112及4113组成一阶梯形断面,使母芯片42贴在最底层,另以子芯片43以倒装片式技术先在母芯片42上方与基底411之间涂上填胶44,再贴在母芯片42上层,且子芯片43以外围的凸块431贴在第二层基底4112上,使整体最底层基板4111、母芯片42、子芯片43所组成的封装高度与该三层组合基底的总厚度不致高于锡球45的高度,而顶层基底4113对外的电气连接则以锡球45设置于顶层基底顶面。
Claims (4)
1、一种倒装片式接合芯片与载体的封合结构,是以倒装片式技术在载体贴上芯片,并再以芯片复合后予以封合的结构,其特征在于:主要是由载体、母芯片及子芯片所组合构成,载体提供芯片承载的基础,并以表面贴着的扁平封装方式贴一芯片在载体上,再用一长有凸块的芯片,以倒装片式方式贴附在芯片上,同时跨贴在载体,以载体、芯片、另一芯片重叠的方式形成封装。
2、如权利要求1所述的倒装片式接合芯片与载体的封合结构,其特征在于:上述载体为导线架的形式。
3、如权利要求1所述的倒装片式接合芯片与载体的封合结构,其特征在于:上述载体为叠层电路板基底。
4、如权利要求1所述的倒装片式接合芯片与载体的封合结构,其特征在于:上述的载体为一多层组合式的基底:先在底层基底上叠一基底,并在第二层基底切有一预留嵌贴母芯片的通孔;再铺上一层最上层的基底,并在同样位置预留一通孔,各层基底组成一阶梯形断面,使母芯片贴在最底层基底上,另将子芯片以倒装片式技术贴在母芯片上层,且子芯片并以外围的凸块贴在第二层基底上,使整体最底层基板、母芯片、子芯片所组成的封装高度比该三层组合基底的总厚度为低。
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CN101246877B (zh) * | 2007-02-15 | 2010-10-27 | 南茂科技股份有限公司 | 多晶片面对面堆叠封装构造 |
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CN101246877B (zh) * | 2007-02-15 | 2010-10-27 | 南茂科技股份有限公司 | 多晶片面对面堆叠封装构造 |
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