CN1330453A - 并行特博格栅编码调制 - Google Patents
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Abstract
一种用于turbo编码的格栅码调制的编码器包括用于存储输入数据的编码器数据块,和至少两个并行递归系统卷积编码器,所述递归系统卷积编码器被连接来并行地从所述编码器数据块接收数据。解码器也采用并行实现。
Description
本发明涉及数字通信领域,具体涉及用于实现turbo(特博)格栅编码调制方案的编码器和解码器。
Turbo码由于具有较大的编码增益而获得极大关注。例如,参见AT&T Shannon实验室的Hamid R.Sadjapour在1996发表的“离散多音调制的turbo码应用”。turbo码包括由对第一编码器的输入序列操作的交织器所分离的两个或多个卷积码。在数字用户线路(DSL)系统中,可以使用turbo码代替格栅码来获得更好的误码率(BER)性能。但是,当构象(constellation)尺寸增加时,turbo码的编码增益优点开始减小。这是因为冗余比特使得构象尺寸变得更大。
我们在同一天提交的共同待审专利申请描述了如何使用turbo码来仅对构象中的最低有效位(LSB)进行编码,并从而达到比当前使用的格栅编码调制(例如Wei码)更好的性能。可获得的数据率仅与Shannon容量相差几dB。
本发明的一个目的是提供一种用于turbo格栅编码调制的编码器和解码器的快速实现。
根据本发明,提供一种产生turbo格栅码调制信号的编码装置,包括用于存储输入数据的编码器数据块,和至少两个递归系统卷积编码器,所述卷积编码器被连接来并行地从所述编码器数据块接收数据。
所述的并行实现结构减小了编码器和解码器的实现周期(implementation cycle)。而且,在三比特并行实现的情况下,还可以使turbo解码器的存储器(RAM)需求节省1/3。
本发明还提供一种用于turbo编码的格栅码调制信号的解码装置,包括对输入信号执行前向和后向迭带的一对解码器,和交织器,解交织器,每个解码器采用n个软比特输入用于每个turbo解码器迭带,其中n是大于1的整数。
下面将仅以例示方式参照附图对本发明进行详细说明,其中:
图1是用于turbo格栅码调制的编码器的方框图;
图2是编码器的并行实现的方框图;
图3a显示典型的RSC编码器;
图3b显示根据本发明原理的并行RSC编码器;
图4是并行turbo解码器的方框图;
图5表示解码器的操作;
图6表示前向迭带的实现;
图7显示图6的细节;
图8表示后向迭带的实现。并行编码器
图1中显示在x>1和y>1情况下,用于turbo格栅编码调制方案的通用构象编码器结构。输入的二进制字u=(uz′,uz′-1,…,u1)确定两个二进制字v=(Vz′-y,…,V0)和W=(Wy-1,…,W0)(其中z′=x+y-1),使用这两个二进制字在编码器表中查找两个构象点。
编码器数据块10接收来自输入比特流的一部分数据并将其存储在存储器中。从编码器数据块读出最低位比特并传递到递归系统卷积编码器RSC1和RSC2。
由块20形成的turbo编码器是以比率1/2穿孔的编码率为3/4的系统编码器。Turbo编码器20包括两个递归系统卷积编码器RSC1和RSC2。编码器RSC1接收来自编码器数据块10的顺序数据,编码器RSC2接收来自相同数据块10的交织数据。在此结构中,需要三个实现周期来得到单个构象点,这主要是由于turbo编码器的实现需求造成的。
为了加速该过程,提供了图2所示的并行编码器结构。与图1的差别在于,RSC1和RSC2都同时取用三个输入数据并在单个实现周期中产生一个差错校验比特。
图3中显示了普通RSC编码器和并行RSC编码器之间的比较,其中图3a是普通的8状态RSC编码器,图3b显示一种并行实现。并行编码器为每三个输入比特仅使用一个实现周期。虽然图3b显示与图3a相同的编码器,但是并行编码器不一定要来源于普通RSC编码器。并行turbo解码器
turbo格栅编码调制的解码程序包括以下步骤:
1.对最低有效位(LSB)进行软解码;
2.对最高有效位(MSB)进行硬解码;
3.使用turbo解码器算法对LSB进行解码;
4.确定所有数据比特。
为了对LSB进行解码(第三步骤),并行turbo解码器取用三个软比特输入用于每个前向(α)和后向(β)迭带。以此方式,每个turbo解码器迭带仅使用1/3周期,并且存储α和β值的存储器需求也减小到三分之一。
图4中显示并行turbo解码器。其包括两个解码器40,42和交织器41,解交织器43。
图5显示解码器40的细节(解码器42具有相同结构)。解码器40,42包括用于计算γ值的块,用于执行迭带的块,和软比特输出块。
图5中所示解码操作的第一步骤是取用三个软比特P3k(0),P3k(1),P3k+1(0),P3k+1(1),P3k+2(0),P3k+2(1)来形成八个概率值(普通turbo解码器仅有两个值,因为其仅包含一比特信息):Pk 000,Pk 001,Pk 010,pk 011,Pk 100,Pk 101,Pk 110,Pk 111。例如,
=P3k(0)+P3k+1(0)+P3k+2(0)通常,
将同一原理应用到输出αk(s),即利用相同的正规化因子正规化在不同状态s的所有αk(s)(对于同一迭带k),使得它们都位于动态范围的中心。正规化因子的确定与普通turbo解码器实现中所使用的确定方式相同。前向迭带中的差别是,由八个先前状态(α′k-1(s′000),α′k-1(s′001),…,α′k-1(s′111))确定在迭带k(αk-1(s))的每个状态s,每个状态s对应于一个输入γj(Rk,s′,s)值(在常规turbo解码器中,仅由两个先前状态确定在迭带k的每个状态,因为其输入仅是一比特信息)。图7中显示图6的LOG-ADD操作,其包括max操作和一查找表。
后向迭带具有与前向迭带相同的结构,并且在图8中显示。
在结束前向和后向迭带后,以如下的两个步骤计算软比特输出:首先对于j=000,001,…,111,计算八个Pj k值, 那么,软输出是Pj 3k值的组合,例如 在最后一次迭带,还输出软差错校验比特: =MAX(s,s′)[γck1(Rk,s,s′)αk-1(s′)βk(s)] =MAX(s,s′)[γck0(Rk,s,s′)αk-1(s′)βk(s)]其中γck0(Rk,s′,s)和γck1(Rk,s′,s)代表差错校验比特(在时间3k+2)分别为0和1的情况下从状态s′到状态s的转换概率。
可以使用数字信号处理领域中技术人员公知的标准数字处理技术在数字信号处理器中实现上述功能块。
上述技术增加了turbo编码器和解码器的实现速度,并能显著节省并行解码器中的存储器需求。
本发明可以应用于具有可变编码率的解码器。
Claims (16)
1.一种用于turbo编码的格栅码调制的编码器,包括用于存储输入数据的编码器数据块,和至少两个并行递归系统卷积编码器,所述递归系统卷积编码器被连接来并行地从所述编码器数据块接收数据。
2.根据权利要求1的编码器,其中每个所述并行递归系统卷积编码器包括:第一组加法器,每个加法器被连接来接收来自所述编码器块的多个数据流;第二组加法器,被连接到第一组加法器中的相应加法器的输出;和延迟单元,用于以递归方式将所述第二组加法器的输出馈送到它们的输入。
3.根据权利要求2的编码器,其中每个所述并行递归系统卷积编码器进一步包括:再一个加法器,其被连接来接收来自所述编码器块的一些所述数据流和一些所述延迟单元的输出,所述再一个加法器的输出提供所述递归系统卷积编码器的输出。
4.根据权利要求2的编码器,其中所述输出代表差错校验比特。
5.根据权利要求2的编码器,其中所述数据流代表所述编码数据的最低有效位。
6.一种用于turbo编码的格栅码调制信号的解码装置,包括对输入信号执行前向和后向迭带的一对解码器,和交织器,解交织器,每个解码器采用n个软比特输入用于每个turbo解码器迭带,其中n是大于1的整数。
7.根据权利要求6的解码装置,其中计算2n个概率值并从概率值中获得对应的差错校验比特。
8.根据权利要求7的解码装置,其中每个解码器包括一正规化单元和一用于执行LOG-ADD操作的单元,以便执行所述迭带。
9.根据权利要求8的解码装置,其中用于执行LOG-ADD操作的单元包括一查找表和一MAX操作单元。
10.一种对turbo格栅编码调制信号进行解码的方法,包括:
取用n个软输入比特,其中n是大于1的整数;
确定所述n个比特的可能组合的概率值;和
并行地对所述输入比特执行前向和后向迭带,以产生解码输出。
11.根据权利要求10的方法,包括首先获得值γi(Rk,s′,s),其中 使值γj(Rk,s′,s)正规化,并对值γj(Rk,s′,s)执行前向和后向递归。
12.根据权利要求11的方法,其中利用相同的正规化因子使所有值γj(Rk,s′,s)正规化,使它们位于动态范围的中心,以允许定点实现的使用。
13.根据权利要求12的方法,其中在前向迭带中,每个状态k由2n个先前状态确定。
14.根据权利要求10的方法,其中n是3。
15.根据权利要求14的方法,其中在执行前向和后向迭带后,以如下两个步骤计算软比特输出:
(i)首先对于j=000,001,...,111,计算八个Pj k值,
(ii)然后导出作为Pj 3k值的组合的软输出,诸如
16.根据权利要求15的方法,其中在最后一次迭带,还输出软差错校验比特: =MAX(s,s′)[γck1(Rk,s,s′)αk-1(s′)βk(s)] =MAX(s,s′)[γck0(Rk,s,s′)αk-1(s′)βk(s)]其中γck0(Rk,s′,s)和γck1(Rk,s′,s)代表差错校验比特(在时间3k+2)分别为0和1的情况下从状态s′到状态s的转换概率。
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GB0010330A GB2361852A (en) | 2000-04-28 | 2000-04-28 | Turbo coded trellis code modulation |
GB0010330.9 | 2000-04-28 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100444524C (zh) * | 2002-08-01 | 2008-12-17 | 扎班纳数字资金有限责任公司 | 用于通信系统中编码数据位的方法、设备和系统 |
CN103986557A (zh) * | 2014-05-23 | 2014-08-13 | 西安电子科技大学 | 低路径延迟的LTE Turbo码并行分块译码方法 |
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US6023783A (en) * | 1996-05-15 | 2000-02-08 | California Institute Of Technology | Hybrid concatenated codes and iterative decoding |
AR010163A1 (es) * | 1997-05-12 | 2000-05-17 | Siemens Ag | Procedimiento para la codificacion de canal de informaciones digitales de comunicacion |
AU6517499A (en) * | 1998-10-13 | 2000-05-01 | Interdigital Technology Corporation | Hybrid interleaver for turbo codes |
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- 2000-04-28 GB GB0010330A patent/GB2361852A/en not_active Withdrawn
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- 2001-04-25 DE DE2001120155 patent/DE10120155B4/de not_active Expired - Fee Related
- 2001-04-27 CN CN 01115658 patent/CN1330453A/zh active Pending
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
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CN100444524C (zh) * | 2002-08-01 | 2008-12-17 | 扎班纳数字资金有限责任公司 | 用于通信系统中编码数据位的方法、设备和系统 |
CN103986557A (zh) * | 2014-05-23 | 2014-08-13 | 西安电子科技大学 | 低路径延迟的LTE Turbo码并行分块译码方法 |
CN103986557B (zh) * | 2014-05-23 | 2017-06-13 | 西安电子科技大学 | 低路径延迟的LTE Turbo码并行分块译码方法 |
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DE10120155B4 (de) | 2008-08-28 |
FR2808390A1 (fr) | 2001-11-02 |
DE10120155A1 (de) | 2001-11-22 |
GB0010330D0 (en) | 2000-06-14 |
GB2361852A (en) | 2001-10-31 |
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