CN1328768C - Thin film transistor and its method for producing circuit - Google Patents
Thin film transistor and its method for producing circuit Download PDFInfo
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- CN1328768C CN1328768C CNB2004100682755A CN200410068275A CN1328768C CN 1328768 C CN1328768 C CN 1328768C CN B2004100682755 A CNB2004100682755 A CN B2004100682755A CN 200410068275 A CN200410068275 A CN 200410068275A CN 1328768 C CN1328768 C CN 1328768C
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Abstract
The present invention relates to a method for manufacturing a thin-film transistor on a basal plate. The surface of the basal plate comprises a gate electrode and a gate insulation layer. Firstly, deposition technology is implemented by utilizing monosilane diluted by hydrogen; a thin film containing silicon is formed on the gate insulation layer; plasma etching technology is implemented by using the hydrogen as reaction gas; then, an interface layer is formed by at least repeating the deposition technology and the etching technology for one time; finally, an amorphous silicon layer, a doped semiconductor layer, a source electrode and drain electrode are formed on the interface layer.
Description
Technical field
The present invention relates to the manufacture method of a kind of thin-film transistor and circuit thereof, particularly relate to a kind of thin-film transistor of the stability with good carrier mobility and starting voltage and the manufacture method of circuit thereof.
Background technology
In recent years, various planes Display Technique is constantly flourish, after the research and development that continue, as new products such as LCD, plasma scope, organic light emitting diode display, commercialization gradually also is applied to various sizes and the display unit of various areas.Present whole flat-panel screens industry develops towards the direction of high image quality, high-resolution, high brightness and low price more, invariably in the hope of producing the display product that has more commercial value.In flat-panel screens technology now, LCD is a wherein ripe technology, to such an extent as to such as in the daily life common mobile phone, digital camera, video camera, mobile computer monitor all are the commodity that utilize this technology manufacturing.LCD adopts the rotation status that utilizes liquid crystal molecule to control the technology of light transmittance, and then the demonstration of realization color, so it is bright secretly to be to adjust via the control light transmittance, when color is constant, liquid crystal molecule also remains unchanged, and LCD also thereby have that picture is stable, the advantage of flicker free sense.Though and organic light emitting diode display starting is than LCD evening, but self-luminous, wide viewing angle, response speed are fast to possess, low power consumption, contrast is strong, brightness is high, thin thickness, can full-colorization, advantage such as simple in structure and operating environment temperature range is big, in many applications, attracted attention gradually.
In addition, LCD and organic light emitting diode display also have another advantage, and promptly it all can be used as and utilizes thin-film transistor to do the active type matrix display of driving.So-called active driving promptly is to make many thin-film transistor, pixel electrode, orthogonal staggered scan line and holding wires that are arranged in array on the substrate of LCD, and cooperates with electronic components such as suitable electric capacity, connection gaskets.When driving, each pixel electrode is driven by the self-powered circuit corresponding to it respectively, that is to say, when the thin-film transistor in each self-powered circuit is unlocked, can transmit specific voltage on corresponding pixel electrode, and then make display produce predetermined picture.Being different from the passive matrix display is to adopt the mode of driven sweep line in proper order, drive the pixel be positioned at different rows/list one by one, the fluorescent lifetime of each pixel that go/lists can not be subject to the scanning frequency and the number of scanning lines of display in the active type matrix display.Therefore, for the big picture or the display of high-resolution (the expression scan line increases), the making of thin-film transistor and circuit thereof can be described as a key technology.
Please refer to Fig. 1 to Fig. 3, Fig. 1 to Fig. 3 is the existing method schematic diagram of making at least one thin-film transistor 26.As shown in Figure 1, existing thin-film transistor is the structure of a bottom-gate.Thin-film transistor 26 is made on the insulated substrate 10, and insulated substrate 10 must be made of the material of printing opacity, and is generally a glass substrate, a quartz base plate or a plastic base.The surface of insulated substrate 10 comprises one source pole presumptive area 11, a drain electrode presumptive area 12 and a passage presumptive area 13.At first carry out one first sputtering technology, form a first metal layer (not shown) in the surface of insulated substrate 10, the first metal layer (not shown) is a tungsten layer, a chromium layer or other conductive metal layer.Then utilize one first photoetching and etch process to form a gate electrode 14 in the surface of insulated substrate 10, and gate electrode 14 is positioned at the top of passage presumptive area 13.
Carry out one first plasma enhanced chemical vapor deposition technology then, form a silicon nitride layer 16 in the surface of gate electrode 14 and insulated substrate 10, to be used as gate insulator.Form semi-conductor layer 18 subsequently on the surface of silicon nitride layer 16, semiconductor layer 18 also is called as active layer, is a hydrogeneous amorphous silicon layer, and is used as the usefulness of the passage when the thin-film transistor (not shown) is unlocked.Deposit a doping semiconductor layer 22 in the top of semiconductor layer 18 again, doping semiconductor layer 22 is made of the amorphous silicons of Doping Phosphorus usually comprehensively.
As shown in Figure 2, carry out one second photoetching and etch process again, to remove the semiconductor layer 18 and the doping semiconductor layer 22 of part.Then carry out one second sputtering technology again, form one second metal level 24 in the top of doping semiconductor layer 22, semiconductor layer 18 and silicon nitride layer 16 comprehensively, and the material that constitutes second metal level 24 comprises tungsten, chromium or molybdenum.
As shown in Figure 3, carry out one the 3rd photoetching and etch process subsequently,, and the semiconductor layer 18 that is positioned on the passage presumptive area 13 is come out with the source electrode 28 and the drain electrode 32 of formation thin-film transistor 26 among second metal level 24.Wherein, source electrode 28 is positioned on the source electrode presumptive area 11, and be positioned at simultaneously on silicon nitride layer 16 partly and the doping semiconductor layer 22, and drain electrode 32 is positioned on the drain electrode presumptive area 12, and be positioned at simultaneously on silicon nitride layer 16 partly and the doping semiconductor layer 22.Doping semiconductor layer 22 is used for promoting 24 pairs of semiconductor layers of second metal level 18 and carries out ohm ability of formula contact, the variety of problems of being derived when directly contacting with semiconductor layer 18 with second metal level 24 of avoiding work function to differ very big.
Deposit a dielectric layer 34 at last again, and utilize one the 4th photoetching and etch process, in the dielectric layer 34 of source electrode presumptive area 11 and drain electrode presumptive area 12 tops, to form the contact hole 36 of a through source electrode 28 and drain electrode 32 respectively, be convenient to fill up electric conducting material within the contact hole 36 thereafter, source electrode 28 and drain electrode 32 are electrically connected to the pole plate or the signal of video signal line (all not being shown among the figure) of electric capacity respectively via contact plunger 38, to finish the making of entire circuit according to circuit design.
Yet existing method of making thin-film transistor 26 but derives a quite serious problem.Owing to be used as the semiconductor layer 18 of passage, constituted by hydrogeneous amorphous silicon material, when thin-film transistor 26 was unlocked, carrier mobility was also not high enough, so that have influence on actuating speed, and when thin-film transistor 26 was closed, leakage current was too big again.Simultaneously because amorphous silicon do not have specific structure, when arbitrary silicon atom lacked one former should with the atomic time of its bond, just produce the outstanding key of so-called Jie's stable state, outstanding key can be regarded as a kind of defective, and may catch electronics or influence the circulation of electronics.Yet because semiconductor layer 18 is a hydrogeneous amorphous silicon layer, hydrogen will combine and form bond in the place that outstanding key produces with silicon atom, and because hydrogen atom is very easy to diffuse to the interface (Si/SiN of semiconductor layer 18 and silicon nitride layer 16
xInterface), more because Si-SiN
xThe discontinuity of interface, hydrogen atom are very easy to be trapped in Si-SiN
xInterface and become interface and be absorbed in electric charge (interface-trapped charge).For any one thin-film transistor, its starting voltage is that semiconductor surface produces minimum gate voltage required when reversing by force, and starting voltage is relevant with flat band voltage, and because interface is absorbed in the generation of electric charge, the size of flat band voltage will be changed, to such an extent as to influence the size of starting voltage, and then influence the stability and the life-span of thin-film transistor 26.
Therefore, develop again in the prior art and a kind of method, amorphous silicon material is transformed into polycrystalline silicon material, in the hope of addressing the above problem.Please refer to Fig. 4, Fig. 4 utilizes quasi-molecule laser annealing technology to handle the method schematic diagram of amorphous silicon membrane 52 in the prior art.As shown in Figure 4, utilize method that quasi-molecule laser annealing technology handles amorphous silicon membrane 52 in the prior art after forming amorphous silicon membrane 52, again insulated substrate 50 is inserted in the airtight reative cell (not shown), to carry out quasi-molecule laser annealing technology.When carrying out quasi-molecule laser annealing technology, but the transparent window (not shown) of the (not shown) top, laser pulse autoreaction chamber 54 of excimer laser exposes to the noncrystal membrane 52 on insulated substrate 50 surfaces, and according to a predefined processing range with the All Ranges in progressively inswept this processing range of a kind of mode of similar scanning, amorphous silicon membrane in this processing range 52 is carried out Fast Heating, make amorphous silicon membrane 52 via the absorption of laser deep UV (ultraviolet light) being reached fusion fast and crystallization again, and then be transformed into polycrystalline silicon material.
Yet this method also faces serious problem.At first, on technology, just must increase the step of a quasi-molecule laser annealing, increase required time and the cost of technology significantly.Secondly, when utilizing quasi-molecule laser annealing technology to make polysilicon membrane, must control many variablees simultaneously well, these variablees include the overlapping degree of the uniformity that distributes on the size, laser energy space of hydrogen content, film thickness uniformity and surface roughness, the laser energy density of amorphous silicon membrane, laser pulse, the temperature of substrate and atmosphere on every side etc. when carrying out laser annealing, when the control of technology was not ideal enough, the quality of the active polysilicon membrane in the passage area will be difficult to control.In addition, because laser crystallization technology is a kind of low temperature solid phase crystallization processes again, the time that solid phase crystallization is again spent is oversize, so crystal grain often can only grow to certain size, can't effectively control the grain boundary number, and then make carrier mobility and leakage current all not as expection.
Therefore, how to develop and a kind of new technology, has the microstructural semiconductor layer of expection to utilize this new technology to produce, when this semiconductor layer of application becomes the active layer of thin-film transistor, can obtain gratifying carrier mobility and low-leakage current, do not need to carry out extra processing step again, just become crucial problem.
Summary of the invention
Main purpose of the present invention is to provide a kind of method of making thin-film transistor and circuit thereof, to address the above problem.
In most preferred embodiment of the present invention, on a substrate, make at least one thin-film transistor, the surface of this substrate comprises that a gate electrode and of this thin-film transistor covers the gate insulator of this gate electrode, this method comprises the following steps: (a). utilizes one to be carried out a depositing operation, on this gate insulator, forms a silicon-containing film by the silicomethane (diluted silanein H2) that hydrogen diluted; (b). utilize hydrogen to carry out a plasma etch process as reacting gas; (c). repeat at least (a) step to (b) step once to form an interface layer; (d). on this interface layer, form an amorphous silicon layer, two doping semiconductor layers, one source pole electrode and a drain electrode of this thin-film transistor in regular turn.
Because the method that the present invention makes thin-film transistor, utilize earlier and carried out depositing operation by the silicomethane that hydrogen diluted, on gate insulator, to form silicon-containing film, utilize hydrogen to carry out a plasma etch process again as reacting gas, etch away so that amorphous silicon is wherein formed, and then provide the condition that microcrystalline silicon film is grown up that is beneficial to.Then, above-mentioned deposition and etch process are repeated alternately again, just utilize technology layer by layer, produce interface layer, make amorphous silicon layer, doping semiconductor layer, source electrode and drain electrode subsequently more in regular turn.Because the microstructure of microcrystal silicon material in the interface layer, no matter be on grain size, hole ratio or crystallization ratio, all can reach expection easily by technology controlling and process, therefore, interface layer can be given full play to the effect of improving amorphous silicon layer and gate insulator interfacial characteristics.Not only the carrier mobility when thin-film transistor is unlocked can maintain certain level, and the thin-film transistor more of the prior art especially of the leakage current when thin-film transistor is closed is low.In addition because interface features effectively improved, in the prior art in Si/SiN
xThe phenomenon that interface produces the stable outstanding key that is situated between can effectively be suppressed, and then promotes the starting voltage stability of thin-film transistor and prolong its useful life.And do not become microcrystal silicon layer owing to do not need whole active layer all deposited in the inventive method, can not derive fully significantly increases the problem of process time.Simultaneously, the inventive method can utilize the online existing plasma enhanced chemical vapor deposition equipment of production to implement, and does not have the consideration that increases new equipment fully.
Description of drawings
Fig. 1 to Fig. 3 is the existing method schematic diagram of making at least one thin-film transistor.
Fig. 4 utilizes quasi-molecule laser annealing technology to handle the method schematic diagram of amorphous silicon membrane in the prior art.
Fig. 5 to Fig. 8 is a method schematic diagram of making at least one thin-film transistor in the first embodiment of the invention.
Fig. 9 is the conversion diagram figure of thin-film transistor in the first embodiment of the invention.
Figure 10 implements the graph of relation of number of times for starting voltage skew and carrier mobility in the technology when making thin-film transistor in the first embodiment of the invention layer by layer.
Figure 11 be in the first embodiment of the invention during depositing operation flow of silicomethane for the graph of relation of starting voltage skew and carrier mobility.
Figure 12 is compared to the graph of relation of starting voltage skew and carrier mobility for the total reaction time of depositing operation article on plasma body etch process in the first embodiment of the invention.
Figure 13 is the performance diagram of thin-film transistor under deviated stress in the first embodiment of the invention.
Figure 14 is the schematic diagram of a thin-film transistor in the second embodiment of the invention.
The simple symbol explanation
10,50,100,200 insulated substrates
11,101 source electrode presumptive areas, 12,102 drain electrode presumptive areas
13,103 passage presumptive areas
14,104,204 gate electrodes, 16,106,206 silicon nitride layers
18,114,214 semiconductor layers
22,116 doping semiconductor layers, 24,118 second metal levels
26,122,222 thin-film transistors
28,124,224 source electrodes, 32,126,226 drain electrodes
34,128 dielectric layers, 36,132 contact holes
38,134,234 contact plungers
52 polysilicon membranes, 54 laser pulses
108,208 boundary layers, 112 silicon-containing film
236 etchings stop pattern
Embodiment
Please refer to Fig. 5 to Fig. 8, Fig. 5 to Fig. 8 is a method schematic diagram of making at least one thin-film transistor 122 in the first embodiment of the invention.As shown in Figure 5, the thin-film transistor in the first embodiment of the invention is the structure of a bottom-gate.Thin-film transistor 122 is made on the insulated substrate 100, and insulated substrate 100 must be made of the material of printing opacity, and is generally a glass substrate, a quartz base plate or a plastic base.The surface of insulated substrate 100 comprises one source pole presumptive area 101, a drain electrode presumptive area 102 and a passage presumptive area 103.At first carry out one first sputtering technology, form a first metal layer (not shown) in the surface of insulated substrate 100.The first metal layer (not shown) can be a single-layer metal layer or a multiple layer metal layer, when if the first metal layer (not shown) is a single-layer metal layer, the material that constitutes the first metal layer comprises an alloy of aluminium, molybdenum, chromium, tungsten, tantalum, copper or above-mentioned metal, and when the first metal layer (not shown) was a multiple layer metal layer, the material that constitutes each metal level comprised an alloy of aluminium, molybdenum, chromium, tungsten, tantalum, copper or above-mentioned metal.Then utilize one first photoetching and etch process to form a gate electrode 104 in the surface of insulated substrate 100, and gate electrode 104 is positioned at the top of passage presumptive area 103.
Carry out one first plasma enhanced chemical vapor deposition technology then, form a silicon nitride layer 106 in the surface of gate electrode 104 and insulated substrate 100, to be used as gate insulator.In fact, gate insulator can be a monolayer insulating layer or a multilayer dielectric layer, and constitutes monolayer insulating layer or the material of each layer insulating comprises tantalum pentoxide, tantalum oxide, alundum (Al, silica, silicon nitride or silicon oxynitride.Subsequently, on the surface of silicon nitride layer 106, form a boundary layer 108, and the method that forms interface layer 108 comprise the following steps: at first to utilize one by silicomethane that hydrogen diluted as reacting gas, carry out one second plasma enhanced chemical vapor deposition technology, to form a silicon-containing film 112.Utilize hydrogen as a reacting gas again, silicon-containing film 112 is exposed in the hydrogen plasma, carry out a plasma etch process.Look the needs of technology, repeat above depositing operation and etch process alternately repeatedly, form the interface layer 108 shown in the figure at last.After handling via hydrogen plasma, the amorphous silicon in the silicon-containing film 112 is formed etched, and forms by etched while progressively when amorphous silicon, also more and more helps the growth of microcrystalline silicon film.And in fact, handle silicon-containing film 112 before without hydrogen plasma and also can be regarded as a kind of microcrystalline silicon film, just it is on grain size, crystallization ratio and hole ratio, if the silicon-containing film 112 after the process hydrogen plasma is handled is ungood.Because the method for above formation interface layer 108, utilization repeats above depositing operation alternately and etch process repeatedly achieves the goal, and therefore can be called as a kind of technology layer by layer.In addition, depositing operation and etch process carry out in same reative cell, and both technological parameters such as pressure and power etc. may be identical, or may adjust according to actual needs.
In the present embodiment, in the silicomethane that hydrogen diluted, silicomethane to the flow-rate ratio of hydrogen between 0.3～2%, the total reaction time ratio of depositing operation article on plasma body etch process is between 0.3～1, and depositing operation and etch process are repeated ten times alternately at least, and the thickness of single silicon-containing film 112 is not more than 50 dusts ().Power density when simultaneously, carrying out depositing operation is 200mW/cm
2, pressure approximately remains on 1200 millitorrs.Since with silicon nitride layer 106 (as previously mentioned, also might be other material) directly the interface layer 108 of contact become a microcrystal silicon structure, not only the electrical characteristic of itself amorphous silicon structures more of the prior art is good, the interface features of itself and gate insulator is also obviously good than the interface features of amorphous silicon layer in the prior art and gate insulator, can effectively improve the problem that the leakage current of thin-film transistor is too high in the prior art, stability is not good and the life-span is not grown.If compare with polysilicon structure, its microstructure also can suppress the grain boundary number, and then leakage current is descended.
Then, as shown in Figure 6, form semi-conductor layer 114 on interface layer 108, semiconductor layer 114 is a hydrogeneous amorphous silicon layer.Deposition one doping semiconductor layer 116 comprehensively in the top of semiconductor layer 114 again, doping semiconductor layer 116 is by amorphous silicon, the amorphous silicon of arsenic doped of Doping Phosphorus or the amorphous silicon of antimony dopant is constituted.It should be noted that amorphous silicon layer utilizes a chemical vapor deposition method made, and doping semiconductor layer utilizes another chemical vapor deposition method made.Perhaps, the silicon nitride layer 106, interface layer 108, semiconductor layer 114 and the doping semiconductor layer 116 that are used as gate insulator also can utilize the plasma enhanced chemical vapor deposition technology of a continous way to deposit in same reative cell and finish, thus, just can repeat the reative cell vacuum breaker to take out insulated substrate 100, make that to make flow process easier.Simultaneously, owing to do not need among the present invention all part depositions of active layer are become microcrystal silicon layer, therefore the sedimentation time that is spent can be not long, very suitable volume production.
As shown in Figure 7, carry out one second photoetching and etch process again, to remove interface layer 108, semiconductor layer 114 and the doping semiconductor layer 116 of part.Then carry out a physical gas-phase deposition again, top in doping semiconductor layer 116, semiconductor layer 114, interface layer 108 and silicon nitride layer 106 forms one second metal level 118 comprehensively, second metal level 118 may be a single-layer metal layer or a multiple layer metal layer, and constitutes the alloy that this single-layer metal layer or the material of each metal level comprise aluminium, molybdenum, chromium, tungsten, tantalum, copper or above-mentioned metal.
As shown in Figure 8, carry out one the 3rd photoetching and etch process subsequently,, and the semiconductor layer 114 that is positioned on the passage presumptive area 103 is come out with the source electrode 124 and the drain electrode 126 of formation thin-film transistor 122 among second metal level 118.Wherein, source electrode 124 is positioned on the source electrode presumptive area 101, and be positioned at simultaneously on silicon nitride layer 106 partly and the doping semiconductor layer 116, and drain electrode 126 is positioned on the drain electrode presumptive area 102, and is positioned at simultaneously on silicon nitride layer 106 partly and the doping semiconductor layer 116.Doping semiconductor layer 116 is used for promoting 118 pairs of semiconductor layers of second metal level 114 and carries out ohm ability of formula contact, the variety of problems of being derived when directly contacting with semiconductor layer 116 with second metal level 118 of avoiding work function to differ very big.
Form a dielectric layer 128 at last again; and dielectric layer 128 comprises a silicon nitride layer or a policapram layer; be used as the usefulness of protection; and utilize one the 4th photoetching and etch process; in the dielectric layer 128 of source electrode presumptive area 101 and drain electrode presumptive area 102 tops, to form the contact hole 132 of a through source electrode 124 and drain electrode 126 respectively; be convenient to fill up electric conducting material within the contact hole 132 thereafter; source electrode 124 and drain electrode 126 are electrically connected to the pole plate or the signal of video signal line (all not being shown among the figure) of electric capacity respectively via contact plunger 134, to finish the making of entire circuit according to circuit design.
Please refer to Fig. 9, Fig. 9 is the conversion diagram figure of thin-film transistor 122 in the first embodiment of the invention.Measurement when Fig. 9 swings to 20 volts for grid voltage by-20 volts, and source electrode-drain voltage is 0.5 volt when the range of linearity, source electrode-drain voltage is 15 volts when the zone of saturation.As shown in Figure 9, if compare with the related data of the thin-film transistor 26 of prior art, utilize the thin-film transistor 122 of the inventive method made, its leakage current is starkly lower than the leakage current of the thin-film transistor 26 of prior art, and its carrier mobility and starting voltage are then very approaching with the thin-film transistor 26 of prior art.
Please refer to Figure 10, Figure 10 implements the graph of relation of number of times for starting voltage skew and carrier mobility in the technology when making thin-film transistor 122 in the first embodiment of the invention layer by layer.As shown in figure 10, when implementing the number of times increase, utilize the thin-film transistor 122 of the inventive method made, its starting voltage skew will become littler and littler, and is better than the thin-film transistor 26 of prior art, and carrier mobility only can slightly reduce.
Please refer to Figure 11, Figure 11 be in the first embodiment of the invention during depositing operation flow of silicomethane for the graph of relation of starting voltage skew and carrier mobility.As shown in figure 11, when the flow of silicomethane during greater than 14 standard cubic centimeter per minutes (SCCM), utilize the thin-film transistor 122 of the inventive method made, its starting voltage skew will obviously become big, and carrier mobility also can obviously reduce, so that cause the electrical characteristic variation of thin-film transistor 122.This is because when the silicomethane flow is too high, and the growth rate of amorphous silicon structures is too fast in the formed film, so that when implementing plasma etching, have little time to etch away the amorphous silicon composition, has only caused the alligatoring of etched surfaces.Therefore, when carrying out depositing operation, silicomethane preferably is controlled in 0.3～2% to the flow-rate ratio of hydrogen, just can produce the thin-film transistor 122 with superior electrical characteristic.
Please refer to Figure 12, Figure 12 is compared to the graph of relation of starting voltage skew and carrier mobility for the total reaction time of depositing operation article on plasma body etch process in the first embodiment of the invention.As shown in figure 12, when the total reaction time of depositing operation article on plasma body etch process than within the scope not the time 0.3～1, utilize the obvious variation of thin-film transistor 122 its electrical characteristics of the inventive method made.
Please refer to Figure 13, Figure 13 is the performance diagram of thin-film transistor 122 under deviated stress in the first embodiment of the invention.The performance diagram of Figure 13 is that 30 volts and temperature are measured under by 60 ℃ bias condition and obtain in grid voltage.As shown in figure 13, after 1000 seconds, the skew of the starting voltage of the thin-film transistor 122 of first embodiment of the invention is 2.2 volts, and (with drain current is 1 * 10
-9Ampere-hour is considered as conducting), and under same condition, the skew of the starting voltage of the amorphous silicon film transistor 26 of prior art is 3.5 volts, the cause of starting voltage skew be since the outstanding key of Jie's stable state at Si/SiN
xDue to interface produces.
Method of the present invention not only can be used for making the thin-film transistor 26 among first embodiment, can also be used for making the thin-film transistor 222 among second embodiment.Please refer to Figure 14, Figure 14 is the schematic diagram of a thin-film transistor 222 in the second embodiment of the invention.As shown in figure 14, thin-film transistor 222 in the second embodiment of the invention is the structure of a bottom-gate, and not the existing together of the thin-film transistor 122 among itself and first embodiment, be to form after the semiconductor layer 214, can be then on glass substrate 200 comprehensively deposition one by etching stopping layer (not shown) that silicon nitride constituted, and in fact, gate insulator 206, interface layer 208, semiconductor layer 214 and etching stopping layer (not shown) are utilized the plasma enhanced chemical vapor deposition technology of a continous way to deposit in same reative cell and are finished.And then carry out a photoetching and etch process, and with in gate electrode 204 tops, forming an etching and stop pattern 236, the Ji is corroded by follow-up etch process to avoid semiconductor layer 214.At last after all processing steps are all implemented to finish, finish the making of the thin-film transistor 222 in the diagram, and source electrode 224 and drain electrode 226 are electrically connected to the pole plate or the signal of video signal line (all not being shown among the figure) of electric capacity respectively via contact plunger 234 according to circuit design, to finish the making of entire circuit.
Because the production method of thin-film transistor of the present invention, utilize earlier and carried out depositing operation by the silicomethane that hydrogen diluted, on gate insulator, to form silicon-containing film, utilize hydrogen to carry out a plasma etch process again as reacting gas, etch away so that amorphous silicon is wherein formed, and then provide the condition that microcrystalline silicon film is grown up that is beneficial to.Simultaneously, above-mentioned deposition and etch process are repeated alternately, just utilize technology layer by layer, produce interface layer.Because the microstructure of microcrystal silicon material in the interface layer, no matter be on grain size, hole ratio or crystallization ratio, all can reach expection easily by technology controlling and process, therefore, interface layer can be given full play to the effect of improving amorphous silicon layer and gate insulator interfacial characteristics.Use the inventive method when an actual production line, can produce and have reasonable carrier mobility, low-leakage current, stablize the thin-film transistor of starting voltage, the while is unlikely to significantly to increase process time and production cost again.
Compared to existing method of making thin-film transistor, the present invention utilizes earlier and is carried out depositing operation by the silicomethane that hydrogen diluted, on gate insulator, to form silicon-containing film, utilize hydrogen to carry out a plasma etch process again as reacting gas, etch away so that amorphous silicon is wherein formed, and then provide the condition that microcrystalline silicon film is grown up that is beneficial to.Simultaneously, above-mentioned deposition and etch process are repeated alternately, just utilize technology layer by layer, produce interface layer, and then make amorphous silicon layer in regular turn, doping semiconductor layer, source electrode and drain electrode.Because the microstructure of microcrystal silicon material in the interface layer, no matter be on grain size, hole ratio or crystallization ratio, all can reach expection easily by technology controlling and process, therefore, interface layer can be given full play to the effect of improving amorphous silicon layer and gate insulator interfacial characteristics.Not only the carrier mobility when thin-film transistor is unlocked can maintain certain level, and the thin-film transistor more of the prior art especially of the leakage current when thin-film transistor is closed is low.In addition because interface features effectively improved, in the prior art in Si/SiN
xThe phenomenon that interface produces the stable outstanding key that is situated between can effectively be suppressed, and then promotes the starting voltage stability of thin-film transistor and prolong its useful life.And do not become microcrystal silicon layer owing to do not need whole active layer all deposited in the inventive method, can not derive fully significantly increases the problem of process time.Simultaneously, the inventive method can utilize the online existing plasma enhanced chemical vapor deposition equipment of production to implement, and does not have the consideration that increases new equipment fully.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (12)
1. method of on a substrate, making at least one thin-film transistor, the surface of this substrate comprises that a gate electrode and of this thin-film transistor covers the gate insulator of this gate electrode, this method comprises the following steps:
(a). utilize one to be carried out a depositing operation, on this gate insulator, form a silicon-containing film by the silicomethane that hydrogen diluted;
(b). utilize hydrogen to carry out a plasma etch process as reacting gas;
(c). repeat at least (a) step to (b) step once to form an interface layer; And
(d). on this interface layer, form an amorphous silicon layer, two doping semiconductor layers, one source pole electrode and a drain electrode of this thin-film transistor in regular turn.
2. the method for claim 1, wherein this substrate is an insulated substrate, and this substrate comprises a glass substrate, a quartz base plate or a plastic base.
3. the method for claim 1, wherein this gate electrode is a multiple layer metal layer, and constitutes the alloy that the material of this metal level respectively comprises aluminium, molybdenum, chromium, tungsten, tantalum, copper or above-mentioned metal.
4. the method for claim 1 wherein should be by in the silicomethane that hydrogen diluted, silicomethane to the flow-rate ratio of hydrogen between 0.3～2%.
5. the method for claim 1, wherein the thickness of this silicon-containing film is not more than 50 dusts.
6. the method for claim 1, wherein (a) step to (b) step is repeated ten times at least.
7. the method for claim 1, wherein this depositing operation to the total reaction time of this plasma etch process than between 0.3～1.
8. the method for claim 1, wherein this interface layer is used for improving the interface features of this amorphous silicon layer and this gate insulator.
9. the method for claim 1, wherein this gate insulator, this interface layer, this amorphous silicon layer and this doping semiconductor layer utilize the plasma enhanced chemical vapor deposition technology of a continous way to deposit in same reative cell to finish.
10. the method for claim 1, wherein this source electrode and this drain electrode are by the made multi-layer metal structure of a physical gas-phase deposition, and constitute the alloy that the material of this metal structure respectively comprises aluminium, molybdenum, chromium, tungsten, tantalum, copper or above-mentioned metal.
11. the method for claim 1, wherein this method also comprises a depositing operation after forming this source electrode and this drain electrode, to form a protective layer that covers this thin-film transistor.
12. method as claimed in claim 11; wherein this method is after forming this protective layer; also comprise a contact process among this protective layer, forming at least one contact plunger, and then this source electrode and this drain electrode are electrically connected to an electric capacity and a signal of video signal line one of them respectively.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5184200A (en) * | 1991-03-27 | 1993-02-02 | Canon Kabushiki Kaisha | Thin film semiconductor device with particular grain size |
| US5834345A (en) * | 1995-09-28 | 1998-11-10 | Nec Corporation | Method of fabricating field effect thin film transistor |
| US6078059A (en) * | 1992-07-10 | 2000-06-20 | Sharp Kabushiki Kaisha | Fabrication of a thin film transistor and production of a liquid display apparatus |
| CN1386301A (en) * | 2000-07-18 | 2002-12-18 | 皇家菲利浦电子有限公司 | Thin film transistors and their manufacture |
-
2004
- 2004-08-27 CN CNB2004100682755A patent/CN1328768C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5184200A (en) * | 1991-03-27 | 1993-02-02 | Canon Kabushiki Kaisha | Thin film semiconductor device with particular grain size |
| US6078059A (en) * | 1992-07-10 | 2000-06-20 | Sharp Kabushiki Kaisha | Fabrication of a thin film transistor and production of a liquid display apparatus |
| US5834345A (en) * | 1995-09-28 | 1998-11-10 | Nec Corporation | Method of fabricating field effect thin film transistor |
| CN1386301A (en) * | 2000-07-18 | 2002-12-18 | 皇家菲利浦电子有限公司 | Thin film transistors and their manufacture |
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| CN1588630A (en) | 2005-03-02 |
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