CN1324794C - Parallel synchronous phase locking method of uninterrupted power source - Google Patents
Parallel synchronous phase locking method of uninterrupted power source Download PDFInfo
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- CN1324794C CN1324794C CNB2004100002130A CN200410000213A CN1324794C CN 1324794 C CN1324794 C CN 1324794C CN B2004100002130 A CNB2004100002130 A CN B2004100002130A CN 200410000213 A CN200410000213 A CN 200410000213A CN 1324794 C CN1324794 C CN 1324794C
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Abstract
The present invention discloses a parallel synchronous phase locking method of an uninterrupted power source, which is characterized in that a synchronous signal is sent out by a UPS which automatically obtains bus controlling power through bus contention in each UPS; when the UPS sending out the synchronous signal has a failure or quits, the bus controlling power can be obtained by the left UPSs through automatic contention, and thus, the present invention ensures uniform adjustment direction of phase locking and does not completely depend upon the determined host machine. The method posed by the present invention does not need additional controlling boards or does not need to preset the host machine; by the method that parallel UPS automatically compete to obtain the bus controlling power, the present invention effectively solves the problem of high risk of a single point failure in the prior art; the present invention can simultaneously complete parallel general genlock and effectively avoid the risk of the single point failures of systems. The method posed by the present invention is simple and practical; the present invention has no need of user intervention in the whole process and only needs to simply update software, and thus, the present invention effectively improves system reliability.
Description
Technical field
The present invention relates to the ac inverter field, relate in particular to a kind of genlock method of uninterrupted power supply.
Background technology
Uninterrupted power supply (hereinafter to be referred as UPS) is because the requirement of power expanding or reliability often needs in parallel the use.For guaranteeing the safety of the UPS that uses in parallel, the output that requires to participate in every UPS in parallel because very little phase error can cause very big circulation, thereby causes serious consequence with width of cloth homophase, particularly phase place.UPS in parallel must face the problem of each UPS output genlock in use.In simulation control field, the way of giving each UPS in parallel after often adopting parallel wire will be given average, but in control chip, exist because of reference waveform in digital field with data mode, can't adopt this method.And phase-locked part is also often finished adjusting by software inhouse in digital control, does not have the phase-locked loop circuit output on the hardware.Give all UPSs as analog circuit with a common reference waveform with regard to having no idea like this.Common solution is now: 1, the adjusting of unifying all UPS with the method that increases the Parallel Control plate; 2 or set an other UPS of working host and follow main frame.Though above-mentioned these two kinds of methods can solve genlock in parallel and work as problem, but these two kinds of methods have also all increased the risk of the Single Point of Faliure of system, promptly when Parallel Control plate or the UPS that is set at main frame break down, can cause the collapse of whole system.
Summary of the invention
The present invention is exactly in order to solve the high problem of Single Point of Faliure risk of system in the above-mentioned prior art, proposes a kind ofly can avoid system's Single Point of Faliure risk, improves the genlock method in parallel of the uninterrupted power supply of system reliability.
Core concept of the present invention is: synchronizing signal is to be sent by the UPS that obtains bus control right automatically by bus contention among each UPS, when the UPS fault of sending synchronizing signal or when withdrawing from, bus control right (transmission synchronizing signal) can be competed automatically by remaining UPS and obtain, so both guarantee unified phase-locked adjusting direction, but not exclusively depended on a certain main frame of identification again.
A kind of genlock method in parallel of uninterrupted power supply comprises the following steps:
First step: be connected in parallel on each UPS on the bus according to synchronizing signal, carry out in parallel phase-locked synchronously;
Second step: bus clock starts, when rising edge that captures synchronizing signal or trailing edge, and the bus clock zero clearing;
Third step: judge whether bus clock is overtime, if not overtime then continue to carry out first step;
The 4th step: if bus clock is overtime, the bus contention flag bit is set then, all UPS that are connected in parallel on the bus forbid sending synchronizing signal, forbid capture interrupt;
The 5th step: all parallel UPSs on the bus are the competition bus control simultaneously, obtains bus control right until certain UPS, occupies bus, and competition finishes;
The 6th step: cancellation bus contention flag bit, the UPS that obtains bus control right begins to send synchronizing signal on bus;
The 7th step: other UPS activates capture interrupt, restarts to carry out first step.
The process of above-mentioned parallel UPS competition bus control comprises the steps:
First substep: the real-time monitoring bus state of each parallel UPS;
Second substep: each UPS judges whether the level of the bus that monitors is consistent with this TV station UPS synchronizing signal transmitting terminal level;
The 3rd substep: if inconsistent then make this TV station UPS withdraw from the bus contention state;
The 4th substep: otherwise judge whether to arrive this TV station UPS stand-by period, if no show this TV station UPS stand-by period then re-executes second substep;
The 5th substep: if arrived this TV station UPS stand-by period, then this TV station UPS sends level signal, occupies bus;
The 6th substep: keep occupying bus a period of time, make other UPS withdraw from bus contention;
The 7th substep: bus contention finishes.
In the technique scheme, the monitoring periods of synchronizing signal is much smaller than synchronous signal cycle.
The method that the present invention proposes does not need to add control board, do not need default main frame yet, obtain the method for bus control right by the automatic competition of each parallel UPS, solve the high problem of Single Point of Faliure risk that exists in the prior art effectively, can when finishing genlock in parallel, effectively avoid the Single Point of Faliure risk of system.The method that the present invention proposes is simple and practical, and whole process need not user intervention, only need carry out the simple software upgrading and can finish, and has improved the reliability of system effectively.
Description of drawings
Fig. 1 is the simplified diagram of the sequential relationship of bus clock and bus level signal in the method flow that proposes of the present invention.
Fig. 2 is the general flow chart of the method that proposes of the present invention.
Fig. 3 is the detail flowchart that carries out bus contention in the proposition method of the present invention.
Embodiment
Below in conjunction with drawings and Examples the present invention is done further to say in detail.
Fig. 1 is the simplified diagram of the sequential relationship of bus clock and bus level signal in the method flow that proposes of the present invention.As shown in Figure 1, the bus clock timing that in the gap of synchronizing signal, adds up, when catching the trailing edge of synchronizing signal, timer zero clearing, reclocking.Synchronizing signal on bus disappears, and the bus free time reaches certain hour to make when bus clock is overtime, sets up the bus contention sign, enters the bus contention state; After the stand-by period of certain UPS arrives, on bus, send the control that low level has obtained bus, after arriving when holding time, the UPS of acquire the right of control begins to send periodic synchronizing signal on bus.
Fig. 2 is the general flow chart of the method that proposes of the present invention.As shown in Figure 2, the genlock method in parallel that the present invention proposes comprises the following steps: 1, be connected in parallel on each UPS on the bus according to synchronizing signal, carries out in parallel phase-locked synchronously.Bus described here is a holding wire in parallel, and the synchronizing signal of any UPS can send to all parallel UPSs by this line, claims that this line is a synchronous bus.In one embodiment of the invention, synchronous bus is a high level when idle, and the synchronizing signal transmitting terminal of any UPS sends the low level signal bus will step-down, occupied.This is the situation of system when being in normal condition: each UPS of parallel connection is coordinated the output of each UPS in phase-locked adjusting and running with a synchronizing signal, a UPS who is connected in parallel on the bus is sent to bus transmission synchronizing signal, the reference of upgrading oneself at rising edge (perhaps trailing edge) parallel UPS of synchronizing signal simultaneously is sinusoidal, can guarantee that so the output of every UPS has Phase synchronization preferably.For the cycle of each synchronizing signal, calculate the step-length of tabling look-up of corresponding inversion ginseng sine table.System catches the difference between inversion zero crossing and the synchronizing signal zero crossing automatically, and according to this difference the phase difference between synchronizing signal and the by-passing signal is adjusted, thereby guarantees the same-phase between inversion output and the bypass.About the phase-lock technique between synchronizing signal and the by-passing signal many disclosed maturation methods have been arranged at present, concrete method can be selected for use arbitrarily as required, list of references is seen: " on line type UPS software is phase-locked " (Li Yanling etc., " power technology application ", the 10th phase of calendar year 2001).2, bus clock starts, when rising edge that captures synchronizing signal or trailing edge, and the bus clock zero clearing.3, judge whether bus clock is overtime, if not overtime then continue execution in step 1.If 4 bus clocks are overtime, the bus contention flag bit then is set, all UPS that are connected in parallel on the bus forbid sending synchronizing signal, forbid capture interrupt.Bus clock is to add up in switch periods is interrupted, and zero clearing in the capture interrupt of synchronizing signal.In one embodiment of the invention, if bus clock surpasses the switch counting of three power frequency periods, illustrating has had three power frequency periods not have synchronizing signal on the synchronous bus, think that at this time bus do not obtained by any UPS, or the UPS fault of occupying bus originally withdraws from and causes the bus free time, and the bus contention flag bit then is set, and enters the bus contention state, this moment, synchronizing signal forbade sending, and capture interrupt also is under an embargo.5, all parallel UPSs while competition bus controls on the bus obtain bus control right until certain UPS, occupy bus, and competition finishes.The detailed process of bus contention will be described in detail among Fig. 3 below.6, cancellation bus contention flag bit.7, the UPS that obtains bus control right begins to send synchronizing signal on bus, and other UPS activates capture interrupt, restarts execution in step 1.
Fig. 3 is the detail flowchart that carries out bus contention in the proposition method of the present invention.The synchronous bus competition here is that UPS in parallel can choose wherein UPS transmission synchronizing signal afterwards automatically by the program of one section setting, and this UPS has obtained bus control right by competition, and the UPS that follows withdraws from the middle of process of competition automatically.As shown in Figure 3, the process of parallel UPS competition bus control comprises the steps: 1, the real-time monitoring bus state of each parallel UPS, just monitors the level of synchronous bus.When in one embodiment of the invention, synchronous bus is idle is high level.2, each UPS judges whether the level of the bus that monitors is consistent with local synchronous signal transmitting terminal level.The assumes synchronization bus is a high level when idle, and the synchronizing signal transmitting terminal level when then UPS does not occupy bus should be high level, and when occupying bus, its synchronizing signal transmitting terminal level just should be low level.If consistent, illustrate that synchronous bus is still idle, if inconsistent, then explanation has the UPS of higher priority to obtain bus, this machine should withdraw from race condition.Therefore: if 3 inconsistent then these machines of making finish after withdrawing from the bus contention state.If inconsistent,, forbid that local synchronous signal sends, and prepares to follow the synchronous bus signal with the zero clearing of this machine latency counter.4 otherwise judge whether to arrive this machine etc. and bide one's time and ask, if this machine of no show stand-by period then re-executes step 2.This machine stand-by period here is meant from entering the bus contention state, obtains time till the bus to this machine.This time can be by the identity code decision of each UPS, and the length of stand-by period and the numerical values recited of identity code are proportional.For example in one embodiment of the invention, the stand-by period of setting a machine is 250us, and the stand-by period of setting No. two machines is 500us, and the like.Correspondingly, the identity code of a machine of setting is that the identity code of 100, No. two machines is 200.Synchronizing signal has been sent by the UPS of address mark sign indicating number minimum earlier.If 5 have arrived this machine stand-by period, then this machine sends level signal, occupies bus.Among the embodiment, bus is a high level when idle, and then this UPS synchronizing signal transmitting terminal sends low level and occupies bus and get final product.If the idle level of bus is a low level, then UPS synchronizing signal transmitting terminal sends high level and occupies bus.7, keep and occupy bus a period of time, make other UPS release bus contention.This is necessary process, because after this UPS takies bus, must make other the UPS of parallel connection learn that this bus control right is acquired, thereby withdraw from the bus contention state automatically, enter following state, need the regular hour, occupy holding time of bus in the present embodiment and be 2.5ms.8, bus contention finishes.
By Fig. 2 and the described genlock method flow in parallel of Fig. 3 as seen, if this of acquire the right of control UPS breaks down, the free time of synchronous bus can be caused the bus contention of a new round, and from the UPS of current normal operation, select the highest UPS transmission synchronizing signal of current priority automatically, and can not cause the interruption of system's power supply because of the fault of separate unit UPS.
Claims (4)
1, a kind of genlock method in parallel of uninterrupted power supply is characterized in that comprising the following steps:
First step: be connected in parallel on each UPS on the bus according to synchronizing signal, carry out in parallel phase-locked synchronously;
Second step: bus clock starts, when rising edge that captures synchronizing signal or trailing edge, and the bus clock zero clearing;
Third step: judge whether bus clock is overtime, if not overtime then continue to carry out first step;
The 4th step: if bus clock is overtime, the bus contention flag bit is set then, all UPS that are connected in parallel on the bus forbid sending synchronizing signal, forbid capture interrupt;
The 5th step: all parallel UPSs on the bus are the competition bus control simultaneously, obtains bus control right until certain UPS, occupies bus, and competition finishes;
The 6th step: cancellation bus contention flag bit, the UPS that obtains bus control right begins to send synchronizing signal on bus;
The 7th step: other UPS activates capture interrupt, restarts to carry out first step.
2, the genlock method in parallel of a kind of uninterrupted power supply according to claim 1 is characterized in that the process of described parallel UPS competition bus control comprises the steps:
First substep: the real-time monitoring bus state of each parallel UPS;
Second substep: each UPS judges whether the level of the bus that monitors is consistent with this TV station UPS synchronizing signal transmitting terminal level;
The 3rd substep: if inconsistent then make this TV station UPS withdraw from the bus contention state;
The 4th substep: otherwise judge whether to arrive this TV station UPS stand-by period, if no show this TV station UPS stand-by period then re-executes second substep;
The 5th substep: if arrived this TV station UPS stand-by period, then this TV station UPS sends level signal, occupies bus;
The 6th substep: keep occupying bus a period of time, make other UPS withdraw from bus contention;
The 7th substep: bus contention finishes.
3, the genlock method in parallel of a kind of uninterrupted power supply according to claim 1 and 2, the monitoring periods that it is characterized in that described synchronizing signal is much smaller than synchronous signal cycle.
4, the genlock method in parallel of a kind of uninterrupted power supply according to claim 3 can think that it is overtime when the timing time that it is characterized in that described bus clock surpasses 3 power frequency periods.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2004100002130A CN1324794C (en) | 2004-01-05 | 2004-01-05 | Parallel synchronous phase locking method of uninterrupted power source |
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| CNB2004100002130A CN1324794C (en) | 2004-01-05 | 2004-01-05 | Parallel synchronous phase locking method of uninterrupted power source |
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| CN1556578A CN1556578A (en) | 2004-12-22 |
| CN1324794C true CN1324794C (en) | 2007-07-04 |
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154093B (en) * | 2006-09-26 | 2011-06-15 | 力博特公司 | Method and apparatus for competing for host computer position in parallel system |
| CN101291058B (en) * | 2007-04-19 | 2011-05-11 | 中兴通讯股份有限公司 | Double AC bus synchronizing apparatus for AC sourced system |
| CN101312302B (en) * | 2007-05-24 | 2011-02-16 | 力博特公司 | Parallel signal transmission method of uninterrupted power source |
| CN101494383B (en) * | 2008-01-23 | 2011-12-14 | 力博特公司 | Control method for parallel connection system of inverter |
| CN102801403B (en) * | 2011-05-24 | 2016-02-10 | 中兴通讯股份有限公司 | The genlock method of power supply and power supply |
| CN102916921B (en) * | 2012-09-19 | 2016-03-30 | 华为技术有限公司 | A kind of carrier synchronization method, Apparatus and system |
| CN103713515B (en) * | 2012-09-28 | 2016-04-06 | 力博特公司 | A kind of determine compensation points method, device and realize the method for Repetitive controller |
| CN105226810B (en) * | 2015-10-12 | 2018-01-19 | 深圳市伊力科电源有限公司 | More ups system power supply synchronization system and methods |
| CN108650068B (en) * | 2018-03-26 | 2022-06-21 | 深圳市伊力科电源有限公司 | Synchronous signal transmission method and system for parallel operation of uninterruptible power supplies |
| CN109617221A (en) * | 2018-11-19 | 2019-04-12 | 浙江德塔森特数据技术有限公司 | The uninterruptible power system and its network-building method of adjustable power configuration |
| CN110504742A (en) * | 2019-08-01 | 2019-11-26 | 深圳市宝安任达电器实业有限公司 | Modular UPS system phase synchronous method and device |
| CN111082511B (en) * | 2019-12-31 | 2023-07-21 | 深圳市核达中远通电源技术股份有限公司 | Main and standby automatic competition and quick switching power supply structure and implementation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1098839A (en) * | 1996-09-24 | 1998-04-14 | I S A:Kk | Universal power supply and continuous operation thereof |
| US5745356A (en) * | 1996-06-25 | 1998-04-28 | Exide Electronics Corporation | Independent load sharing of AC power systems connected in parallel |
| US6356471B1 (en) * | 2000-07-10 | 2002-03-12 | Powerware Corporation | Dynamic feedback adaptive control system and method for paralleling electric power sources and an uninterruptible power supply including same |
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2004
- 2004-01-05 CN CNB2004100002130A patent/CN1324794C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5745356A (en) * | 1996-06-25 | 1998-04-28 | Exide Electronics Corporation | Independent load sharing of AC power systems connected in parallel |
| JPH1098839A (en) * | 1996-09-24 | 1998-04-14 | I S A:Kk | Universal power supply and continuous operation thereof |
| US6356471B1 (en) * | 2000-07-10 | 2002-03-12 | Powerware Corporation | Dynamic feedback adaptive control system and method for paralleling electric power sources and an uninterruptible power supply including same |
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