CN101154093B - Method and apparatus for competing for host computer position in parallel system - Google Patents
Method and apparatus for competing for host computer position in parallel system Download PDFInfo
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- CN101154093B CN101154093B CN2006101523505A CN200610152350A CN101154093B CN 101154093 B CN101154093 B CN 101154093B CN 2006101523505 A CN2006101523505 A CN 2006101523505A CN 200610152350 A CN200610152350 A CN 200610152350A CN 101154093 B CN101154093 B CN 101154093B
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Abstract
The invention discloses a method and an inverter of competing for the position of host in a parallel system, and is used to solve the problem of system breakdown caused by multihost case in the prior art. The method of the invention includes: the inverters connected in parallel in the parallel system intercept the signal in the host bus, and determines whether a host exists in the system at that moment according to the intercept result; If so, the inverter is maintained at the present position; or else, the inverters send ID to the host bus one by one in delay action and the present inverter is taken as the host. The invention is applicable to parallel systems of the same capacity and different capacity, and improves the speed and success rate of the host competition in the parallel system.
Description
Technical field
The present invention relates to power technique fields, particularly the method for competing for host computer position and inverter in parallel system.
Background technology
In the existing parallel system of forming by a plurality of modules (as inverter), the interchange output of each module is wherein connected together, provide capacity or the raising reliability of energy for load jointly to increase system.For guaranteeing the reliability service of parallel system, the amplitude that each module exchanges output must be consistent, and phase place also must keep synchronously, otherwise can produce bigger circulation each other, and then causes the overload or the damage of each module.
In the distributing parallel system, for guaranteeing the phase-locking between each module, need in each module, to choose a certain module as main frame, be used to control the frequency source of whole parallel system output voltage; Other module is used to follow the tracks of the phase place of main frame output voltage all as slave.Such as, at parallel uninterrupted power supply UPS, Uninterrupted Power Supply) in the system, when the bypass power down taking place or when unusual, each module will lose common tracing source, this just needs to determine that by distinguishing the control strategy of host and slave processors a unique main frame comes the phase-locking of each module in the maintenance system.
In this decentralised control strategy, be to have and only have one to the requirement of main frame, in different capabilities (power) parallel system, be the stability that guarantees system, the maximum machine of capacity required (power) is as the main frame of parallel system; This is because if off in the parallel system, the output phase of the equal tracker of each module, can keep substantially each module phase place synchronously, but whole parallel system is in the normal shock state, the output frequency of final system can depart from its nominal value; If there are a plurality of main frames in addition in the parallel system, each main frame all can be as the frequency source of system, produce output voltage based on nominal frequency oscillator separately, owing to exist dispersed between each nominal frequency oscillator inevitably, no matter whether identical original state is, and As time goes on finally meeting forms phase differential and causes failure in parallel on the output voltage of each module.
In above-mentioned phase-locking strategy, for the existence that guarantees main frame and unique, as shown in Figure 1, the module that has different identification numbers in the prior art is connected with competition bus by host bus, each module is carried out the competition of principal and subordinate's machine according to its corresponding host identities marker pulses width and host identities releasing pulse width by host bus and competition bus, thereby determines the main frame status; Host bus is used to guarantee the existence of main frame, as long as off still in the parallel system, the module of unlatching will be found this situation by host bus, and existing side by side own is main frame; Competition bus is used to guarantee the uniqueness of main frame, when a plurality of main frame appears in parallel system, All hosts all sends corresponding host identities marker pulses and host identities releasing pulse to competition bus, by relatively the pulse width and the host identities of self of competition bus are removed pulse, remove the main frame status of the module that priority on the identification number is lower, determines that the higher module of priority is a main frame.
But, if main frame is opened and competed to several modules simultaneously,, therefore there is following deficiency because the time-delay of incoming level signal on the host bus race hazard may take place, thereby causes occurring the simultaneous phenomenon of a plurality of main frames:
When 1, adopting host bus and competition bus to realize the competition of principal and subordinate's machine, the opener of module elder generation is a main frame, and the inversion main frame can not change in the parallel system power supply process;
2, the right of each module acquisition main frame status has equality and uncertainty after system loses main frame;
3, under small probability event, the same time period might occur the phenomenon of a plurality of main frame coexistences;
4, the maximum length in time of a plurality of main frames coexistence is more than 256 timed interrupt cycle, if be that 133us calculates by interruption frequency, the maximum duration that then a plurality of main frames are worked simultaneously is 0.133*256=42.5ms.
Above-mentioned preceding two characteristics are suitable for the parallel system of same capability, but for the parallel system of different capabilities, the parallel system main frame can not change can make the little machine in the different capabilities parallel system become main frame, and make the parallel system bad stability; And latter two deficiency can cause system to exist reaching the situation of a plurality of main frames coexistences in 256 timed interrupt cycle under the small probability situation, can cause parallel system to collapse because of the disorder of output tracking when serious.
Summary of the invention
In view of this, the invention provides a kind of in parallel system the method for competing for host computer position, because the problem that exists a plurality of main frames to cause parallel system to be collapsed, further solved the problem of different capabilities parallel system poor stability in order to solve in the prior art.
The inventive method comprises:
A kind of in parallel system the method for competing for host computer position, comprise step:
Each inverter in parallel is intercepted the signal on the host bus in the parallel system;
Described inverter is determined the current main frame that whether exists in the system according to intercepted result, if then keep the current status of this inverter, otherwise described inverter is delayed time successively and sent the host identities sign to described host bus, and this inverter is considered as main frame.
During described each inverter of parallel system initial start-up, the inverter that is set to main frame sends the host identities sign to described host bus, for the inverter of slave sends the slave identify label to described host bus.
Described host bus presents the information of host identities after receiving host identities sign and slave identify label.
Described host identities is designated high level, and described slave identify label is a low level, and described host bus is or the bus of logic.
Described time-delay is according to the priority setting of described inverter, and its time-delay of the inverter of different priorities is different, and its time-delay of inverter that its medium priority is high is short.
The difference of the time-delay of any two inverters that priority is adjacent is identical.
Described priority is preferential according to the big person of rated capacity, and equal rated capacity is preferentially determined with the little person of identification number.
Described inverter sends the host identities sign to described host bus when the delay time of correspondence arrives.
The condition that the inverter that is in inversion main frame status loses self inversion main frame status is that system loses maximum inversion start max cap. sign in bypass side and this inverter, or system loses maximum inversion power supply max cap. sign in inversion side and this inverter.
Calculate the inversion start max cap. and the inversion power supply max cap. of inverter according to the type capacity that powers on, open state and the power supply state of the inverter of communication bus transmission.
The inverter that is in inversion main frame status sends the slave identify label to described host bus after losing self inversion main frame status.
But a kind of inverter of competing for host computer position comprises:
First reports the unit, is used for sending host identities sign and slave identify label to host bus;
Intercept the unit, be used to intercept signal on the described host bus to determine the current main frame that whether exists of system;
Competitive unit, control when being used for not having the main frame time delay in the system of listening to described first report the unit to described host bus send the host identities sign and with this inverter as main frame; When the system of listening to has main frame to exist, keep the current status of this inverter.
Described inverter also comprises:
Second reports the unit, is used for sending to communication bus power on type capacity, open state and the power supply state of inverter.Described competitive unit comprises:
Main frame is removed module, the inverter that is used to be in inversion main frame status is satisfying the inversion main frame sign of removing self when following condition loses inversion main frame status: system loses maximum inversion start max cap. sign in bypass side and this inverter, or system loses maximum inversion power supply max cap. sign at inversion side and this inverter, and controls described first and report the unit to send the slave identify label to described host bus;
The competition module, be used for the system of listening to is current control when not having inversion main frame time delay described first reporting module to described host bus send the host identities sign and with this inverter as the inversion main frame;
Keep module, be used for keeping the current status of this inverter in that the system of listening to is current when having the inversion main frame.
Described competitive unit is realized by trigger, is perhaps realized by programmable logic device (PLD) and microprocessor.
A kind of parallel system comprises the inverter of a plurality of parallel connections; It is characterized in that, also comprise host bus, described inverter links with described host bus respectively; Wherein, described inverter is intercepted the signal on the host bus, and determine the current main frame that whether exists in the system according to intercepted result, if, then keep the current status of this inverter, otherwise each described inverter is delayed time successively and is sent the host identities sign to described host bus, and this inverter is considered as main frame; This system also comprises:
Main frame is removed module, be used for removing when the inverter that is in inversion main frame status satisfies following condition the main frame sign of himself: system loses maximum inversion start max cap. sign in bypass side and this inverter, or system loses maximum inversion power supply max cap. sign at inversion side and this inverter, and controls described first and report the unit to send the slave identify label to described host bus.
Beneficial effect of the present invention is as follows:
1, the present invention is applicable to the main frame competition of same capability parallel system and different capabilities parallel system;
2, the present invention adopts the competitive strategy of time-delay mechanism simultaneously, has reduced to occur the probability of a plurality of main frames at one time, thereby has avoided a plurality of main frames coexistences and cause the phenomenon of system crash;
3, the present invention adopts main frame candidate mechanism can avoid the situation of low capacity machine as main frame, and having solved in the different capabilities parallel system with big machine is the specific demand of main frame, thereby has solved the problem of different capabilities parallel system poor stability;
4, the present invention has higher real-time, has shortened the time of main frame competition, has improved the success ratio and the rapidity of main frame competition.
Description of drawings
Fig. 1 is the system architecture principle schematic by host bus and competition bus competing for host computer position in the prior art;
Fig. 2 is the same capability parallel system structural principle synoptic diagram that passes through the host bus competing for host computer position in the embodiment of the invention;
Fig. 3 is the different capabilities parallel system structural principle synoptic diagram that passes through the host bus competing for host computer position in the embodiment of the invention;
Fig. 4 is the structural representation of inverter in the embodiment of the invention;
Fig. 5 is the realization flow figure of competing for host computer position in the parallel system in the embodiment of the invention;
Fig. 6 is an inversion main frame candidate schematic diagram of mechanism in the embodiment of the invention;
Fig. 7 is candidate's inverter realization flow figure of competing for host computer position again in the embodiment of the invention;
Fig. 8 A is the waveform synoptic diagram that adopts the synchronous switched system host bus of the inventive method signal in the embodiment of the invention;
Fig. 8 B adopts the inventive method system big machine of inversion side to add the waveform synoptic diagram of aft engine bus signals in the embodiment of the invention.
Embodiment
Parallel system in the present embodiment realizes the main frame competition of each intermodule by host bus, adopts candidate's mechanism and time-delay mechanism to realize the main frame competition of candidate block when having main frame in system; Module in parallel in the present embodiment is an example with the inverter in the ups system, below in conjunction with Figure of description technical solution of the present invention is elaborated.
Consult Fig. 2 and Fig. 3, for carry out the system architecture synoptic diagram of main frame competition in the present embodiment by host bus, in the same capability parallel system shown in Figure 2, connect a plurality of inverters 20 by a host bus 21, realize the competition of main frame by host bus 21, before powering in the identification number of default the inverter 20 of lowest number send host identities signs (high level) to host bus 21, and determine that this inverter is a main frame, because host bus 21 is or the bus of logic, it is that high level is then kept its slave status that other inverters 20 listen to host bus.In the different capabilities parallel system shown in Figure 3, connect a plurality of inverters by a host bus 31, increase a type that powers on that is used between each inverter, transmitting each inverter simultaneously, the communication bus 32 of the communication informations such as inversion open state and inversion power supply state, inverter 30 calculates inversion start max cap. machine by this communication information and inversion is started shooting maximum supply apparatus to judge the condition of main frame status releasing, in that system is current when not having main frame, inverter 30 is delayed time successively according to corresponding priorities and is sent host identities sign (high level) to host bus 31, and determines that this inverter is a main frame.
As shown in Figure 4, the inverter in the present embodiment comprises that first reports unit 40, is used for sending host identities sign (high level) and slave identify label (low level) to described host bus; Second reports unit 42, is used for sending the communication informations such as type capacity, inversion open state and inversion power supply state that power on to communication bus; Intercept unit 41, be used to intercept the level state of described host bus, promptly intercept the current inversion main frame that whether exists in this parallel system; Competitive unit 43, be used for the system of listening to is current control when not having the main frame time delay described first report unit 40 to described host bus send the host identities sign and with this inverter as main frame; Wherein, described competitive unit 43 further comprises main frame releasing module 430, the inverter that is used to be in the main frame status is removed the main frame sign of self when losing the main frame status, and controls described first and report unit 40 to send the slave identify label to described host bus; Competition module 431, be used for the system of listening to is current control when not having the main frame time delay described first report unit 40 to described host bus send the host identities sign and with this inverter as main frame; Keep module 432, be used for keeping the current status of this inverter in that the system of listening to is current when having main frame.
For the same capability parallel system, inverter is intercepted signal on the host bus 21 by intercepting unit 41, in that definite system is current when not having main frame, competition module 431 reports unit 40 to send the host identities sign to described host bus 21 according to the delay time control first of this machine correspondence, determines that this inverter is a main frame; In that definite system is current when having main frame, keep the current status of this inverter.
For the different capabilities parallel system, inverter reports unit 42 communication informations such as type capacity, inversion open state and inversion power supply state that will power on to send to communication bus by second, intercept signal on the host bus 31 by intercepting unit 41, in that definite system is current when not having main frame, competition module 431 reports unit 40 to send the host identities sign to described host bus 31 according to the delay time control first of this machine correspondence, determines that this inverter is a main frame; In that definite system is current when having main frame, keep the current status of this inverter.
In the said system, when the inverter that is in the main frame status loses the main frame status of self, remove module 430 by main frame and remove the main frame sign of self, and control first and report unit 40 to send the slave identify label, determine that this inverter is a slave to host bus.
Host bus described in the present embodiment can be simple or logical organization, also can be that the mode of negative logic shows as and logic; Described communication bus can be the communication pattern of various data such as CAN, RS232 or RS485 or status exchange; Described competition device can be realized by digital circuits such as triggers, also can be realized by programmable logic device (PLD) and microprocessor.
As shown in Figure 5, each inverter is as follows by the process of host bus competing for host computer position in the inversion parallel connection system:
If parallel system is the initial start-up inverter, then need be before step 500 increase will not open or buttoned-up inverter all is set to slave, and to described host bus transmission low level, the inverter that is set to main frame sends the step of high level to host bus.
The different capabilities parallel system adopts candidate's mechanism that each inverter that identification number is set is carried out prioritization according to the information such as the type capacity that powers on, inversion open state and inversion power supply state of each inverter that transmits on the communication bus in the present embodiment; Candidate's priority is preferential with the big person of rated capacity, and capacity determines with the preferential cardinal rule of plane No. smaller on an equal basis.The position of because the inverter state of parallel system changes each inverter being arranged in order to reduce exerts an influence, candidate priorities ordering is the own order that just has been ranked after machine powers on, and the state that the sorting position of every machine is come according to each machine biography carries out real-time update; And when having in the parallel system under the machine behind the electricity, the ordering of machine is change simultaneously also.Each machine only need be just passable according to be ranked oneself order of the current electrifying condition of system when determining candidate priorities, do not need to consider the preferential position situation of other machine, and after other machine power down its priority automatically toward front-seat (being that priority is that 1 machine powers on forever), as shown in Figure 6, inversion main frame candidate schematic diagram of mechanism, the reserve main frame candidate mechanism of this main frame competition have been saved the time of inverter time-delay.
The thought of inversion main frame competition mechanism is the following jumping that utilizes system's inversion host bus signal along being the benchmark moment point, delays time and obtains main frame competition qualification according to the sort inversion main frame candidate priorities that produces of candidate; With 6 machine parallel connections is example, the corresponding relation of identification number, priority sequence number and delay time is as shown in table 1, it is that 1 inverter need not be delayed time that system is provided with priority, priority is 2 inverter time-delay 3ms, priority is 3 inverter time-delay 6ms, equal difference is analogized time-delay successively, finally under 6 machines situation in parallel, the maximum duration of system's off can not surpass 20ms, described delay time is the set time that system is provided with, this time is enough to guarantee that corresponding inverter obtains main frame competition qualification, therefore can not cause the problem of parallel system collapse.
| | # | 1 | #2 | #3 | #4 | #5 | #6 |
| The |
4 | 1 | 2 | 6 | 5 | 3 |
| Delay time (ms) | 9 | 0 | 3 | 15 | 12 | 6 |
Table 1
The specific implementation method of inversion main frame releasing main frame status is as follows in the present embodiment: for the different capabilities parallel system, the requirement system is switched toward inversion in the bypass side, or system works to have the bigger machine of capacity to add in the inversion rear flank fashionable, all to allow big machine become main frame; Calculate the machine of inversion start max cap. and the machine of inversion power supply max cap. by communication bus, and increase the condition that the competition of parallel system main frame is removed:
1) system loses maximum inversion start max cap. sign at bypass side and this machine, inversion start max cap. sign appear at down jumping along the time judge this condition;
2) system loses maximum inversion power supply max cap. sign at inversion side and this machine, inversion power supply max cap. sign appear at down jumping along the time judge this condition.
When one of them of above-mentioned two conditions took place, the inversion main frame was removed and be the sign of inversion main frame, and to the identify label of host bus transmission slave, it is low level, competing for host computer position again that other inverters listen to host bus; As shown in Figure 7, the realization flow of competing for host computer position is as follows again for candidate's inverter:
Inverter obtains corresponding delay time according to this machine priority in the said process, corresponding inversion main frame competition qualification end mark when arriving, this machine delay time is set, adopt candidate's mechanism to set the main frame that different delayed time produces, avoided reaching in the prior art problem that causes the parallel system collapse more than having a plurality of main frames simultaneously in the time of 40ms, this process is in different capabilities inversion parallel connection system, for main frame change switching provides a kind of main frame contention scheme comparatively reliably.
After adopting candidate's inversion main frame competitive strategy, during system inversion main frame competition the off time shorter, under the operating mode of closing the inversion main frame, only need the time of about 4ms just can compete the inversion main frame; Equally, switching synchronously, preferentially switching and system is adding under the situation of big machine in the inversion rear flank, the time of system's off also has only several milliseconds, the big machine of system's inversion side in the synchronous switched system shown in Fig. 8 A shown in host bus signal waveform and Fig. 8 B adds aft engine bus signals waveform, be that the parallel system of forming with Nxb30k and two inverters of Nxb10k is that the verification platform experiment test obtains, from experimental result as can be seen, the inversion main frame competitive strategy of the inventive method can improve the rapidity and the success ratio of main frame competition.
The present invention is applicable to equal capacity parallel system and different capabilities parallel system, simultaneously the inventive method overcome in the prior art determine complex structure that host aspect exists, dumb, reliability is low, the sideline is complicated and problem such as real-time difference, has further solved the problem of different capabilities parallel system poor stability.
The present invention also is applicable to rectifier systems in parallel and the other system with master-slave mode communication RS485 except being applicable to inverter system in parallel, the described implementation procedure of the process of its competing for host computer position and present embodiment in like manner repeats no more.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (15)
1. the method for a competing for host computer position in parallel system is characterized in that, comprises step:
Each inverter in parallel is intercepted the signal on the host bus in the parallel system;
Described inverter is determined the current main frame that whether exists in the system according to intercepted result, if then keep the current status of this inverter, otherwise described inverter is delayed time successively and sent the host identities sign to described host bus, and this inverter is considered as main frame;
The condition that the inverter that is in inversion main frame status loses self inversion main frame status is that system loses maximum inversion start max cap. sign in bypass side and this inverter, or system loses maximum inversion power supply max cap. sign in inversion side and this inverter.
2. the method for claim 1, it is characterized in that, during described each inverter of parallel system initial start-up, the inverter that is set to main frame sends the host identities sign to described host bus, for the inverter of slave sends the slave identify label to described host bus.
3. method as claimed in claim 2 is characterized in that, described host bus presents the information of host identities after receiving host identities sign and slave identify label.
4. method as claimed in claim 3 is characterized in that described host identities is designated high level, and described slave identify label is a low level, and described host bus is or the bus of logic.
5. as each described method of claim 1 to 4, it is characterized in that described time-delay is according to the priority setting of described inverter, and its time-delay of the inverter of different priorities is different, its time-delay of inverter that its medium priority is high is short.
6. method as claimed in claim 5 is characterized in that, the difference of the time-delay of any two inverters that priority is adjacent is identical.
7. method as claimed in claim 6 is characterized in that, described priority is preferential according to the big person of rated capacity, and equal rated capacity is preferentially determined with the little person of identification number.
8. method as claimed in claim 5 is characterized in that, described inverter sends the host identities sign to described host bus when the delay time of correspondence arrives.
9. the method for claim 1 is characterized in that, calculates the inversion start max cap. and the inversion power supply max cap. of inverter according to the type capacity that powers on, open state and the power supply state of the inverter of communication bus transmission.
10. the method for claim 1 is characterized in that, the inverter that is in inversion main frame status sends the slave identify label to described host bus after losing self inversion main frame status.
But 11. the inverter of a competing for host computer position it is characterized in that, comprising:
First reports the unit, is used for sending host identities sign and slave identify label to host bus;
Intercept the unit, be used to intercept signal on the described host bus to determine the current main frame that whether exists of system;
Competitive unit, control when being used for not having the main frame time delay in the system of listening to described first report the unit to described host bus send the host identities sign and with this inverter as main frame; When the system of listening to has main frame to exist, keep the current status of this inverter; Described competitive unit comprises:
Main frame is removed module, be used for satisfying the inversion main frame sign of removing himself when following condition loses inversion main frame status at the inverter that is in inversion main frame status: system loses maximum inversion start max cap. sign in bypass side and this inverter, or system loses maximum inversion power supply max cap. sign at inversion side and this inverter, and controls described first and report the unit to send the slave identify label to described host bus.
12. inverter as claimed in claim 11 is characterized in that, also comprises:
Second reports the unit, is used for sending to communication bus power on type capacity, open state and the power supply state of inverter.
13., it is characterized in that described competitive unit also comprises as claim 11 or 12 described inverters:
The competition module, be used for the system of listening to is current control when not having inversion main frame time delay described first report the unit to described host bus send the host identities sign and with this inverter as the inversion main frame;
Keep module, be used for keeping the current status of this inverter in that the system of listening to is current when having the inversion main frame.
14. inverter as claimed in claim 13 is characterized in that, described competitive unit is realized by trigger, is perhaps realized by programmable logic device (PLD) and microprocessor.
15. a parallel system comprises the inverter of a plurality of parallel connections; It is characterized in that, also comprise host bus, described inverter links with described host bus respectively; Wherein, described inverter is intercepted the signal on the host bus, and determine the current main frame that whether exists in the system according to intercepted result, if, then keep the current status of this inverter, otherwise each described inverter is delayed time successively and is sent the host identities sign to described host bus, and this inverter is considered as main frame; This system also comprises:
Main frame is removed module, be used for satisfying the inversion main frame sign of removing himself when following condition loses inversion main frame status at the inverter that is in inversion main frame status: system loses maximum inversion start max cap. sign in bypass side and this inverter, or system loses maximum inversion power supply max cap. sign at inversion side and this inverter, and controls this inverter and send the slave identify label to described host bus.
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