CN1324653C - Method for improving n-type doping concentration of compound semiconductor under low growth temperature - Google Patents
Method for improving n-type doping concentration of compound semiconductor under low growth temperature Download PDFInfo
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- CN1324653C CN1324653C CNB2004100350336A CN200410035033A CN1324653C CN 1324653 C CN1324653 C CN 1324653C CN B2004100350336 A CNB2004100350336 A CN B2004100350336A CN 200410035033 A CN200410035033 A CN 200410035033A CN 1324653 C CN1324653 C CN 1324653C
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- type doping
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- gallium arsenide
- doping content
- indium gallium
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The present invention relates to a method for improving n type doping concentration in a compound semiconductor at low growth temperature, which comprises the following steps that an MOCVD method is used, and a buffer layer grows on a substrate at high growth temperature; the temperature of a reaction chamber is decreased to the low growth temperature; a reaction source V/III ratio leading into the reaction chamber is reduced, a doping source flow and other growth conditions keep unchanged, and the n type doping compound semiconductor grows.
Description
Technical field
The present invention relates to the semiconductor growing field, relate in particular to a kind of method that improves n type doping content in the indium gallium arsenide semiconductor.
Background technology
Indium phosphide and compound semiconductor thereof are because the advantage of its optical absorption spectra wavelength, circuit speed and power consumption aspect has great application prospect in the long wavelength fiber communications field.Growth can be used for that used high-quality indium phosphide and compound semiconductor thereof is the basis that this series material is applied to this field in the electric device (for example heterojunction bipolar transistor (HBT)) of long wavelength light fiber communication and the photoelectric device.
For example, in the growth course of HBT device,, can adopt the method for low-temperature epitaxy entire device in order to improve the doping content of base.Because the collecting region and the emitter region of HBT device all have high n type doped layer separately, and, be difficult to obtain very high doping content usually as the silane decomposition efficiency reduction at low temperatures of n type doped source.The method that improves doping content in the prior art comprises the increase silane flow rate or adopts alternative dopings source, for example disilane.But because the restriction of growth apparatus, silane flow rate can not infinitely increase, and the increase of silane flow rate certainly will cause unnecessary waste.In addition,, must carry out certain transformation and calibration, expend time and manpower growth apparatus if adopt the alternative dopings source.
Summary of the invention
The object of the present invention is to provide a kind of method that improves n type doping content in the indium gallium arsenide semiconductor, this method adopts n type doped source silane commonly used to obtain high n type doping content with less doped source flow, reduced expending of doped source, simplify growth course, reduced the growth cost.
Technical scheme of the present invention is that a kind of method that improves n type doping content in the indium gallium arsenide semiconductor is characterized in that, comprises following step:
Utilize the MOCVD method, under 655 ℃ of growth temperatures, growth indium phosphide resilient coating on the indium phosphide substrate;
Reaction chamber temperature is reduced to 600 ℃ growth temperature; And
Reduce to feed the reaction source V/III ratio of reative cell, keep doped source flow and other growth conditions constant, the indium gallium arsenide semiconductor that growing n-type mixes.
Wherein, the thickness of resilient coating is 100nm to 300nm.
The V/III ratio that wherein feeds the reaction source of reative cell is to reduce by reducing the group V source flow.
Wherein said group V source is a phosphine.
Wherein said group V source is an arsine.
Wherein said doped source is a silane.
Embodiment
A kind of method that improves n type doping content in the indium gallium arsenide semiconductor comprises following step:
Utilize the MOCVD method, under high growth temperature, growth indium phosphide resilient coating on the indium phosphide substrate, the thickness of this indium phosphide resilient coating is 100nm to 300nm, the high growth temperature that grown buffer layer adopted is 655 ℃;
Reaction chamber temperature is reduced to low growth temperature, and this low growth temperature is less than 600 ℃; And
Reduce to feed the reaction source V/III ratio of reative cell, keep flow and other growth conditions of doped source silane constant, the compound semiconductor that growing n-type mixes, wherein said compound semiconductor is indium phosphide or indium gallium arsenic, the V/III ratio that wherein feeds the reaction source of reative cell is to reduce by reducing the group V source flow, and wherein said group V source is phosphine or arsine.
Embodiment one
In a specific embodiment of the present invention, at first, under 655 ℃ of high growth temperatures-for example, on the indium phosphide substrate, adopt MOCVD method deposition one deck indium phosphide resilient coating; Buffer layer thickness is between 100nm to 300nm.
Subsequently reaction chamber temperature is reduced to and is lower than 600 ℃.
When keeping other reaction source flow constant, reduce to feed the flow of the V family reaction source phosphine of reative cell, the V/III ratio of the growth source that feeds reative cell is reduced to less than 100, the phosphorization phosphide indium layer that deposition n type mixes.
Embodiment two
In another specific embodiment of the present invention, at first, under 655 ℃ of high growth temperatures-for example, on the indium phosphide substrate, adopt MOCVD method deposition one deck indium phosphide resilient coating; Buffer layer thickness is between 100nm to 300nm.
Subsequently reaction chamber temperature is reduced to and is lower than 600 ℃.
When keeping other reaction source flow constant, reduce to feed the flow of the V family reaction source arsine of reative cell, the V/III ratio of the growth source that feeds reative cell is reduced to less than 100, the ingaas layer that deposition n type mixes.
Utilize electrochemistry CV method to detect the compound semiconductor layer of being grown, the gained result is presented at the n type doping content that has obtained in indium phosphide and/or the indium gallium arsenic film greater than 1.0E19.
Claims (6)
1. a method that improves n type doping content in the indium gallium arsenide semiconductor is characterized in that, comprises following step:
Utilize the MOCVD method, under 655 ℃ of growth temperatures, growth indium phosphide resilient coating on the indium phosphide substrate;
Reaction chamber temperature is reduced to 600 ℃ growth temperature; And
Reduce to feed the reaction source V/III ratio of reative cell, keep doped source flow and other growth conditions constant, the indium gallium arsenide semiconductor that growing n-type mixes.
2. the method for n type doping content is characterized in that in the raising indium gallium arsenide semiconductor according to claim 1, and wherein, the thickness of resilient coating is 100nm to 300nm.
3. the method for n type doping content is characterized in that in the raising indium gallium arsenide semiconductor according to claim 1, and the V/III ratio that wherein feeds the reaction source of reative cell is to reduce by reducing the group V source flow.
4. the method for n type doping content is characterized in that wherein said group V source is a phosphine in the raising indium gallium arsenide semiconductor according to claim 3.
5. the method for n type doping content is characterized in that wherein said group V source is an arsine in the raising indium gallium arsenide semiconductor according to claim 3.
6. the method for n type doping content is characterized in that wherein said doped source is a silane in the raising indium gallium arsenide semiconductor according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100350336A CN1324653C (en) | 2004-04-20 | 2004-04-20 | Method for improving n-type doping concentration of compound semiconductor under low growth temperature |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100350336A CN1324653C (en) | 2004-04-20 | 2004-04-20 | Method for improving n-type doping concentration of compound semiconductor under low growth temperature |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1691285A CN1691285A (en) | 2005-11-02 |
| CN1324653C true CN1324653C (en) | 2007-07-04 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2004100350336A Expired - Fee Related CN1324653C (en) | 2004-04-20 | 2004-04-20 | Method for improving n-type doping concentration of compound semiconductor under low growth temperature |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2009046577A1 (en) * | 2007-10-12 | 2009-04-16 | Lattice Power (Jiangxi) Corporation | Method for fabricating an n-type semiconductor material using silane as a precursor |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5141569A (en) * | 1988-12-22 | 1992-08-25 | Ford Microelectronics | Growth of P type Group III-V compound semiconductor on Group IV semiconductor substrate |
| US5498568A (en) * | 1994-06-30 | 1996-03-12 | Sharp Kabushiki Kaisha | Method of producing a compound semiconductor crystal layer with a steep heterointerface |
| US6566256B1 (en) * | 1999-04-16 | 2003-05-20 | Gbl Technologies, Inc. | Dual process semiconductor heterostructures and methods |
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2004
- 2004-04-20 CN CNB2004100350336A patent/CN1324653C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5141569A (en) * | 1988-12-22 | 1992-08-25 | Ford Microelectronics | Growth of P type Group III-V compound semiconductor on Group IV semiconductor substrate |
| US5498568A (en) * | 1994-06-30 | 1996-03-12 | Sharp Kabushiki Kaisha | Method of producing a compound semiconductor crystal layer with a steep heterointerface |
| US6566256B1 (en) * | 1999-04-16 | 2003-05-20 | Gbl Technologies, Inc. | Dual process semiconductor heterostructures and methods |
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| CN1691285A (en) | 2005-11-02 |
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