CN1323102A - Tebo code decoder and its decoding method - Google Patents
Tebo code decoder and its decoding method Download PDFInfo
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- CN1323102A CN1323102A CN 00115594 CN00115594A CN1323102A CN 1323102 A CN1323102 A CN 1323102A CN 00115594 CN00115594 CN 00115594 CN 00115594 A CN00115594 A CN 00115594A CN 1323102 A CN1323102 A CN 1323102A
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Abstract
In the Turbo code decoder, the branch measuring calculating unit (BMU) utilizes the state transfer characteristic to reduce the number of the branch measuring value to be calculated and provides lowest place of prior information Z to the addition, comparison and selection unit (ACS). The ACS performs complementation to the sign place of branch measuring calculating value according to the branch measuring value provided by the BMU and the lowest place of Z, so as to deducts originally required branch valve and to eliminate the quantization error caused by Z/2 in the latter addition, comparison and selection operation. The ACS subtracts the accumulation measured value in foregoing time or present time from the accumulation measured value in various state to realize normalization.
Description
The present invention relates to Te Bo (Turbo) the sign indicating number decoder in the mobile radio system, relate in particular to a kind of decoder of the viterbi algorithm based on soft inputting and soft output, and coding/decoding method.
In wireless communication system, transmission signals can be subjected to the interference of factors such as time diffusion, decline because of transmission medium is inhomogeneous and unstable, causes the mistake of the bit generation randomness that receives., need encode to primary signal for this reason, improve the transmission reliability and the validity of information by some error correction methods.
Convolution code is a kind of error correcting code commonly used.Common convolution code form is the regression system sign indicating number, is called for short the RSC sign indicating number.Encoder for convolution codes uses usually that (n0, k0 m) characterize.Wherein n0 is the output bit of encoder; K0 is the input bit of encoder; And m is the number of shift register in the encoder.Encoder can also be represented its characteristic with constraint length K, and it equals encoder for convolution codes internal displacement the number of registers m and adds 1, is used for determining the scope of zone field bit affects.Shown in Fig. 2 is (3,1, a 3) encoder for convolution codes.Its constraint length is 4, and code check is 1/3.It is the structure in the cdma2000 motion.If adopt the structure in the WCDMA motion, encoder is (2,1,3) so, does not have Y
1Output, code check is 1/2.
Compare with convolution code, Turbo code is the very strong sign indicating number of a kind of error correcting capability.Its encoder can be made of the cascade system of two or more sub-encoders by serial or parallel connection, more generally makes two encoder for convolution codes parallel connections.
Fig. 1 is a kind of structural representation of Turbo code encoder.It is the Turbo code encoder of advising among the cdma2000.In the figure, Turbo code encoder 10 comprises two regression system convolution code (RSC) sub-encoders 14 and 16 in parallel up and down.First sub-encoders 14 is directly imported in input information position one tunnel, and second sub-encoders 16 is imported by interleaver 12 in another road.The effect of interleaver is to the rearrangement of input data, adjusts the distribution of weight.Therefore, import weight distribution and first sub-encoders 14 different of the bit stream of second sub-encoders 16.First sub-encoders 14 and second sub-encoders 16 are respectively to the data coding, then with encoded data input card punch 18.The multichannel bits punching sampling of 18 pairs of two sub-encoders 14 of card punch and 16 outputs and and the string conversion, modulate data on suitable code check (such as 1/2,1/3 or 1/4 code check etc.) output.
Fig. 2 illustration sub-encoders 14 and 16 structure among Fig. 1.Here, the sub-decoder of Turbo code is two (3,1,3) RSC encoder for convolution codess.Its constraint length is 4, and code check is 1/3.It is the structure in the cdma2000 motion.If adopt the structure in the WCDMA motion, encoder is (2,1,3) so, does not have Y
1Output, code check is 1/2.
As seen from Figure 2, encoder comprises three shift registers that are connected in series mutually 20.When input was imported one, the content in each shift register was transmitted to the right successively.Encoder also comprises a plurality of modulo 2 adders 22, and they make addition process according to certain coding rule to the output signal of input signal and shift registers at different levels.In the figure, corresponding to the input of the information of a bit, encoder will be exported three bits, i.e. X, Y
0And Y
1X is the information bit identical with input information, Y
0And Y
1Be two check bits.When error code takes place because of channel disturbance in X, Y
0And Y
1Can be used to error correction.In addition, encoder also comprises a tail bit controller 24.When frame data input finishes, need be to shift register 20 zero clearings.At this moment, the switch of tail bit controller 24 can be switched to the below, by three beats, with the bit in three shift registers 20 as importing zero clearing successively.
The convolutional code decoder device corresponding with encoder for convolution codes is a kind of by the device of maximum likelihood method to deciphering with the code word of convolution coding.Viterbi decoder belongs to the convolutional code decoder device, also is the most successful so far a kind of convolutional code decoder device.Viterbi decoder compares by encoder, the encoding state that will determine and the code word state that receives, and selects immediate coding path, comes the information that transmit in selected path is deciphered.
Fig. 3 shows a kind of structure of Viterbi decoder 30.In this decoder, branch metric calculation unit (BMU) 31 calculates the branched measurement value that arrives two kinds of possibilities of next node state from certain state of certain node according to formula (1):
BM=K
0* R
0+ K
1* R
1+ K
2* R
2(1) wherein BM is the branched measurement value that calculates; K
0, K
1And K
2Be respectively information bit X and two check bit Y to the output of Fig. 2 encoder for convolution codes
0And Y
1Modulation result (0 modulation result be-1,1 modulation result be+1); R
0, R
1And R
2Correspond respectively to K
0, K
1And K
2The information affected by noise that receives after the channel transmission.Then, branch metric calculation unit 31 is sent into result of calculation and is added than selecting computing unit (ACS) 32.ACS unit 32 comprises and adding than selecting computation subunit 321, normalization arithmetic element 322 and maximum rating tolerance detecting unit 323.For each state of certain node, ACS subelement 321 calculates corresponding two accumulative total path metric values with the accumulative total path metric value addition on branched measurement value and the previous path; Two accumulative total path metric values that calculate are compared; And therefrom select bigger accumulative total path metric value.ACS subelement 321 is imported maximum rating tolerance detecting unit 323 and normalization arithmetic element 322 respectively with selection result.Maximum rating tolerance detecting unit 323 detects in all cumulative metrics values has peaked that cumulative metrics value.In order to prevent to overflow, 322 pairs of cumulative metrics values of normalization arithmetic element are made normalized, promptly the cumulative metrics value of each state of ACS subelement 321 outputs is deducted certain value, preferably each cumulative metrics value is deducted maximum rating tolerance detecting unit 323 detected largest cumulative metrics.Then, the cumulative metrics value after the normalization is stored in the state measurement value memory (SMM) 35, so that when next node being done to add, offer ACS unit 32 than choosing calculating.Recall processor 37 and do according to the result of maximum rating tolerance detecting unit 323 and recall processing, and will recall and handle resulting path and be placed in the path memory 33.
The decoder that is used for Turbo code adopts the recursive iteration mode.According to different decoding algorithms, mainly be divided into maximum a posteriori probability (MAP) decoding algorithm and maximum likelihood method (SOVA) decoding algorithm.Fig. 4 illustration a kind of structure of Turbo code decoder 40.It uses the SOVA decoding algorithm.At first, separate perforating device 41 and separate punching to received signal, it is equivalent to the inverse operation of card punch 18 in the Turbo encoder 10 shown in Figure 1.For example,, separate perforating device 41 and will dock the breath of collecting mail and go here and there and change for the situation of (3,1,3) sub-encoders, and the information bit zero padding by card punch 18 is destroyed, three tunnel information are reverted to six the tunnel.In the signal of separating perforating device 41 output, corresponding to three tunnel information R of the coding result of first sub-encoders 14
0, R
1And R
2Import first soft inputting and soft output (SISO) decoder 42, corresponding to three tunnel information R of the coding result of second sub-encoders 16
0', R
1' and R
2' input second soft inputting and soft the output decoder 43.In addition, in order to improve the decode precision of siso decoder device, each decoder 42 and 43 also needs to import a prior information Z or Z '.The initial value of prior information Z can be set to zero.Specifically, the decoding of the coding result of 42 pairs first sub-encoders 14 of the first siso decoder device except that the soft information of output, is also exported an additional extrinsic information.These output informations are after interleaver 44 interweaves, as the prior information Z ' input second siso decoder device 43.Corresponding soft information and extrinsic information are exported in the coding result decoding of 43 pairs second sub-encoders 16 of the second siso decoder device.Then, these output informations revert to the order before interweaving through deinterleaver 46 deinterleavings, and import the first siso decoder device 42 as prior information Z.So iterate, decode precision is more and more higher, and the error rate is more and more lower.Through after the iteration repeatedly,, then import deinterleaver 47 and carry out deinterleaving, the order before reduction interweaves if think and reached required precision.Because the output of deinterleaver is signed numbers (for example, 0.8 ,-1.2,5.5 or the like) of some expression probability, so need make hard decision with the information after 48 pairs of deinterleavings of decision device.When information greater than 0 the time, decision device output 1; When information less than 0 the time, decision device output 0.The information that obtains after decoding can not equal 0.At last, decision device output decoder result recovers original information X.
For each the siso decoder device 42 and 43 among Fig. 4, Fig. 5 illustration its internal structure.As shown in the drawing, branch metric calculation unit (BMU) 51 calculates the branched measurement value that arrives two kinds of possibilities of next node state from certain state of certain node according to formula (2):
BM=K
0* R
0+ K
1* R
1+ K
2* R
2± Z/2 (2) wherein BM is the branched measurement value that calculates; K
0, K
1And K
2Be respectively information bit X and two check bit Y to the output of Fig. 2 encoder for convolution codes
0And Y
1Modulation result; R
0, R
1And R
2Correspond respectively to K
0, K
1And K
2The information affected by noise that receives after the channel transmission; Z is a prior information.Then, BMU unit 51 is sent into result of calculation and is added than selecting computing unit (ACS) 52.ACS unit 52 is with the accumulative total path metric value addition on branched measurement value and the previous path, calculate two the accumulative total path metric values and the poor absolute value thereof of current state, two accumulative total path metric values that calculate are compared, therefrom select bigger accumulative total path metric value and corresponding path thereof, then with selection result respectively input state metric memory (SMM) 55 and path memory 53, and in the absolute value input difference memory 56 with the difference of two accumulative total path metric values calculating on the current state.Recall processor 57, the path P B[k that provides according to path memory 53] and the difference Mdiff[k+1 of the accumulative total path metric value that provides of difference memory 56], carry out Viterbi traceback computing and soft information trace-back operation, export soft information 11r and hard decision.58 pairs of symbol-modulated are recalled the soft information of processor 57 outputs and are carried out the hard decision modulation, also claim symbol-modulated.Specifically,, then soft information is taken advantage of positive sign,, then soft information is taken advantage of negative sign if hard decision is input as 0 if hard decision is input as 1.Obtain soft output thus.At this moment, if decoding does not also reach predetermined precision, then to do normalization 59 and calculate, as the extrinsic information of next stage iteration input.In addition, in this soft inputting and soft output decoder, also comprise controller 54, it is used to control the contact between above-mentioned each parts.
Viterbi decoder more shown in Figure 3 and SOVA decoder shown in Figure 5 are not difficult to find, the SOVA decoding algorithm than the Viterbi decoding algorithm complexity many.Specifically, contrast BMU unit 31 and 51, the computing formula of SOVA decoder (2) has been Duoed an addition Item ± Z/2 than the computing formula (1) of Viterbi decoder.When realizing with circuit, this division arithmetic can bring quantization error.The absolute value Mdiff of difference that Viterbi decoder also will calculate two accumulative total path metric values of each state more is compared in contrast ACS unit 32 and 52, SOVA decoder.
In the prior art, BMU unit and ACS unit are all at Viterbi decoding algorithm.This BMU and ACS cellular construction based on Viterbi decoding can not be done special optimization process to the addition Item Z/2 in the SOVA decoding algorithm, soft information and normalization etc.
Therefore, need the BMU and the ACS unit of Viterbi decoder be improved, make it eliminate the quantization error that addition Item Z/2 brings, and reduce and calculate the required clock cycle, to satisfy the high speed requirement of SOVA decoding.
An object of the present invention is, a kind of decoder that is used for Turbo code is provided, it can reduce construction unit and eliminate the quantization error that addition Item Z/2 brings.
Another object of the present invention is, a kind of decoder that is used for Turbo code is provided, and it can reduce construction unit, eliminate the quantization error that addition Item Z/2 brings, and reduces the clock cycle.
A further object of the present invention is, a kind of coding/decoding method that is used for Turbo code is provided, and it can eliminate the quantization error that addition Item Z/2 brings, and reduces the clock cycle.
Another purpose of the present invention is, a kind of coding/decoding method that is used for Turbo code is provided, and it can reduce construction unit, eliminate the quantization error that addition Item Z/2 brings, and reduces the clock cycle.
To achieve these goals, according to one aspect of the present invention, provide a kind of decoder that is used for Turbo code, it comprises:
The branch metric calculation unit is used to calculate the branch path metric value from certain state of certain node to certain state of next node;
Add than selecting computing unit, it comprises:
Add than selecting computation subunit, be used for to a plurality of branched measurement values add up, comparison and selection operation, calculate the absolute value of the difference of cumulative metrics value under each state, cumulative metrics value, and select routing information;
The normalization arithmetic element is used to receive from adding than the cumulative metrics value under each state that selects subelement, and the cumulative metrics value is carried out the normalization computing; And
Maximum rating tolerance detecting unit is used for comparison through normalized cumulative metrics value, therefrom selects the maximum likelihood state with largest cumulative metric, recalls starting point so that provide;
Path memory cell is used to store described adding than the described routing information that selects computing unit to provide;
The state measurement memory cell is used to store described adding than the described accumulative total path metric value that selects computing unit to provide;
The difference memory cell is used to store the described absolute value that adds than the difference of two accumulative total path metric values of the current state of selecting computing unit to calculate;
Recall processing unit, according to described maximum likelihood state, carry out the Viterbi traceback computing, and according to from the routing information of path memory and poor from the accumulative total path metric value of difference memory, carry out the computing of parallel backtracking simultaneously of many parallel routes, and export soft information and hard decision;
Symbol modulation is used for the described soft information of recalling processor output is carried out the hard decision modulation, exports soft output; And
Control circuit, it links to each other with above-mentioned each unit, is used to control the contact between these unit;
In addition, described branch metric calculation unit is used to calculate i branched measurement value, 2
N-1≤ i＜2
N+1The bit number that n is exported when importing a bit for the Turbo code sub-encoders, a wherein said i branched measurement value can be extrapolated described adding than selecting needed all the other branched measurement values of computation subunit by asking opposite number computing and recovery operation, and described branch metric calculation unit offers described adding than selecting computing unit with the lowest order of a described i branched measurement value and prior information Z;
Described adding: processing unit than selecting computing unit also to comprise, be used to receive described i branched measurement value that described branch metric calculation unit provides and the lowest order of described prior information Z, according to the lowest order of described Z, calculate the opposite number of a described i branched measurement value, obtain 2
n-i branched measurement value, and described reckoning is obtained with described receive altogether 2
nIndividual branched measurement value offers described adding than selecting computation subunit;
Described add than select computation subunit carry out described add than selection operation before, with receive described 2
nIndividual branched measurement value returns to the number that actual operation needs.
According to another aspect of the present invention, a kind of coding/decoding method that is used for the Turbo code decoder is provided, it comprises the following steps: this method
I the branch path metric value of calculating from certain state of certain node to certain state of next node, 2
N-1≤ i＜2
N+1, the bit number that n is exported when being bit of the sub-decoder of Turbo code input, a wherein said i branched measurement value is by asking opposite number computing and recovery operation to extrapolate to add all the other branched measurement values than actual needs in the selection operation process;
The lowest order of prior information Z is provided;
According to the lowest order of described Z, calculate the opposite number of a described i branched measurement value, obtain 2
n-i branched measurement value;
2 of i branched measurement value that obtains according to described calculation procedure and the acquisition of described reckoning step
n-i branched measurement value recovers all branched measurement values that actual operation needs;
All branched measurement values that described recovering step is obtained add up, comparison and selection operation, calculate the absolute value of the difference of cumulative metrics value each state under, cumulative metrics value, and the selection routing information;
The cumulative metrics value is carried out the normalization computing;
Relatively, therefrom select maximum likelihood state with largest cumulative metric through normalized cumulative metrics value;
Store described routing information, described accumulative total path metric value, and the absolute value of the difference of two accumulative total path metric values of current state;
According to described maximum likelihood state, carry out the Viterbi traceback computing, and poor according to described routing information and described accumulative total path metric value, carry out the computing of parallel backtrackings simultaneously of many parallel routes, and export soft information and hard decision;
The soft information of described output is carried out the hard decision modulation, export soft output.
For above-mentioned decoder, under the cdma2000 motion, n=3, the branch metric calculation unit calculates 4 branched measurement values.For example:
BMa=R
0+R
1+R
2+Z/2,
BMb=R
0-R
1+R
2+Z/2,
BMc=R
0-R
1-R
2+Z/2,
BMd=R
0+R
1-R
2+Z/2，
Wherein, BMa-BMd is the branched measurement value that calculates, R
0, R
1And R
2Be respectively the information that decoder receives, Z is a prior information.
And under the WCDMA motion, n=2, the branch metric calculation unit calculates 2 branched measurement values.For example:
BMa=R
0+R
1+Z/2,
BMb=R
0-R
1+Z/2。
Wherein, BMa and BMb are the branched measurement values that calculates, R
0, R
1Be respectively the information that decoder receives, Z is a prior information.
In one embodiment of the invention, the normalization arithmetic element comprises many parallel normalization computing circuits, and every normalization computing circuit all comprises a subtracter and a state measurement register.Wherein subtracter is used for the current cumulative metrics value under the corresponding state is deducted the value that previous moment is stored in any one state measurement register, and the state measurement register is used for storage through normalized cumulative metrics value.
In another embodiment of the present invention, the normalization arithmetic element comprises: a plurality of subtracters and a plurality of state measurement register, wherein subtracter is used for the cumulative metrics value under the corresponding state is deducted any one cumulative metrics value of current time, and the state measurement register is used for storage through normalized cumulative metrics value.
In yet another embodiment of the present invention, maximum rating tolerance detecting unit is a comparator.
In the present invention, BMU unit by using state transitions feature is reduced the number of the number of original calculative branched measurement value, and the lowest order of prior information Z is provided.Branched measurement value through reducing the number of that ACS unit by using BMU unit provides and the lowest order of Z are negated or supplement to the sign bit in the branch metric calculation formula, thereby derive remaining branched measurement value.The ACS unit uses parallel organization to calculate cumulative metrics value, Mdiff information and routing information, has reduced the clock cycle.In addition, the ACS unit carries out the normalization computing, thereby has dwindled circuit scale by the cumulative metrics value under each state being deducted a certain cumulative metrics value of previous moment or current time, has reduced the clock cycle.
Below in conjunction with accompanying drawing, preferred embodiment of the present invention is described.Accompanying drawing has:
Fig. 1 is a kind of structure of Turbo code encoder;
Fig. 2 is the structure chart of RSC sub-encoders in the Turbo code encoder;
Fig. 3 is the structure chart of Viterbi decoder.
Fig. 4 is the structure chart of Turbo code decoder;
Fig. 5 is the structure chart of siso decoder device in the Turbo code decoder shown in Figure 4.
Fig. 6 A is a circuit diagram, illustration according to the branch metric calculation unit of first embodiment of the invention.
Fig. 6 B is a circuit diagram, illustration according to the branch metric calculation unit of second embodiment of the invention.
Fig. 7 A is a circuit diagram, illustration adding according to third embodiment of the invention than selecting computing unit.
Fig. 7 B is a circuit diagram, illustration adding according to fourth embodiment of the invention than selecting computing unit.
Describing in detail before branch metric calculation of the present invention unit and Jia Bi select computing unit, at first analyzing the state exchange situation of sub-encoders shown in Figure 2.
| Current state | NextState | |
| (the state number/K that is input as 0 0,K 1,K 2) | (the state number/K that is input as 1 0,K 1,K 2) | |
| ????0 | ????0/-1-1-1 | ????4/111 |
| ????1 | ????4/-1-1-1 | ????0/111 |
| ????2 | ????5/-11-1 | ????1/1-11 |
| ????3 | ????1/-11-1 | ????5/1-11 |
| ????4 | ????2/-111 | ????6/1-1-1 |
| ????5 | ????6/-111 | ????2/1-1-1 |
| ????6 | ????7/-1-11 | ????3/11-1 |
| ????7 | ????3/-1-11 | ????7/11-1 |
The digital 0-7 of description status corresponds respectively to 8 binary condition 000-111 of three shift registers in the tabulation; K
0, K
1And K
2Be respectively information bit X and two check bit Y to encoder output
0And Y
1Modulation result.For example, as shown in Figure 2, if current state is 0, input information is 0, so state transitions to 0.Encoder is correspondingly exported: X=0, Y
1=0, Y
2=0.Because K
0, K
1And K
2Be X, Y
1And Y
2Modulation result, so they are respectively K
0=-1, K
1=-1, K
2=-1.
At first, the relation between each row in the analytical table.For current state 0 and 1, when importing identical routing information, its corresponding (K
0, K
1, K
2) be identical.Specifically, when being input as 0, both (K
0, K
1, K
2) be all (1 ,-1 ,-1), and be input as at 1 o'clock, both (K
0, K
1, K
2) be all (1,1,1).For current state 2 and 3,4 and 5, and 6 and 7, be not always the case.Therefore, at 16 groups of (K
0, K
1, K
2) in, half is arranged is repetition.The calculating of branched measurement value can reduce half.
Secondly, the relation between each row in the analytical table.Same current state is because the different routing information (0 or 1) of input is transferred to different states, but corresponding (K
0, K
1, K
2) opposite number each other.For example, when being input as 0, state 0 is transferred to state 0, at this moment K
0, K
1, K
2Be respectively (1 ,-1 ,-1).When being input as 1, state 0 is transferred to state 4, at this moment K
0, K
1, K
2Be respectively (1,1,1).These two groups of numerals are opposite number each other.For remaining current state 1-7, situation all is like this.Therefore, 8 groups of (K behind above-mentioned reducing by half
0, K
1, K
2) in, half can be derived by second half, and the calculating of branched measurement value can reduce half again.
At last, analyze the sign bit of Z/2.Because regulation is got-Z/2 when being input as 0, when being input as 1, gets+Z/2, so the symbol of Z/2 and K
0Symbol identical.Therefore, for routing information 0 and 1, not only corresponding two groups of data (K
0, K
1, K
2) also opposite number each other of opposite number, and corresponding Z each other/2 sign bits.
The above analysis as seen, and is for 16 branched measurement values, actual just passable as long as calculate 4 branched measurement values.The coefficient of these 4 branched measurement values can be: (1,1,1,1), (1 ,-1,1,1), (1,1 ,-1,1), (1 ,-1 ,-1,1).Other branched measurement value can obtain by asking opposite number, and the back is described in detail again.
Fig. 6 A is a circuit diagram, illustration according to the BMU unit 51 of first embodiment of the invention.This BMU unit be under the cdma2000 motion shown in Figure 2, code check is 1/3 RSC sub-encoders structure.As shown in the figure, BMU unit 51 comprises four adders 61 and three subtracters 62.Its annexation makes input signal R
0, R
1, R
2With Z after through two timeticks, form four branched measurement value BMa, BMb, BMc, BMd.Be not difficult to find out that four branched measurement values are respectively:
BMa=R
0+R
1+R
2+Z/2,
BMb=R
0-R
1+R
2+Z/2,
BMc=R
0-R
1-R
2+Z/2,
BMd=R
0+ R
1-R
2+ Z/2, their coefficient is consistent with the coefficient of four branched measurement values that above-mentioned analysis obtains.The lowest order of four branched measurement value BMa, BMb, BMc, BMd and Z that BMU unit 51 will calculate offers next stage ACS unit.
Fig. 6 B also is a circuit diagram, illustration according to the BMU unit 51 of second embodiment of the invention.This BMU unit be under the WCDMA motion, code check is 1/2 RSC sub-encoders structure.Because encoder does not have Y under the WCDMA motion
1Output is so the BMU unit of present embodiment only need calculate two branched measurement values.Shown in Fig. 6 B, BMU unit 51 comprises two adders 61 and a subtracter 62.Its annexation makes input signal R
0, R
1With Z after through two timeticks, form two branched measurement value BMa and BMb.These two branched measurement values are respectively:
BMa=R
0+R
1+Z/2,
BMb=R
0-R
1+Z/2，
Their coefficient is corresponding to (1,1,1) and (1 ,-1,1).Two branched measurement value BMa that BMU unit 51 will calculate and the lowest order of BMb and Z offer next stage ACS unit.
Because the BMU unit has reduced the number of the branched measurement value of Practical Calculation, so the ACS unit is adding than before selecting calculating, the branched measurement value that must provide according to upper level BMU unit is earlier extrapolated the branched measurement value of being reduced the number of.Because the coefficient of the branched measurement value of need calculating and the coefficient that has obtained branched measurement value be opposite number each other, so be easy to expect ask remaining branched measurement value by complementary operation.
But, it should be noted that comprise in the branch metric calculation formula (2) addition Item+Z/2 or-Z/2.Usually, calculate Z/2 and can realize that a high position is expanded with sign bit by Z is moved to right one.As long as it is just passable that this displacement method takes dislocation to connect in circuit.Yet, in technical solution of the present invention,, can go wrong if supplement obtains [(Z/2)] by being shifted then to Z.
The SOVA decoder requires the ACS unit to calculate the absolute value Mdiff of the difference of cumulative metrics value.Specifically, the ACS unit can relate to such computing: Z/2-[-(Z/2) when calculating the difference of two cumulative metrics values].If Z is an even number, calculate according to the mode of above-mentioned displacement supplement so, the result does not have error.If but Z is an odd number, compares with floating point arithmetic so, right-shift operation can make Z/2 loss 0.5.Z=1 for example is if calculate Z/2=0 by the mode of moving to right.And when calculating subtrahend [(Z/2)], because divided by 2 before the supplement sign indicating number, so-(Z/2)=0.Like this, Z/2-[-(Z/2)]=0.But, if press floating point arithmetic, Z/2=0.5 ,-(Z/2)]=-0.5, the result should be Z/2-[-(Z/2)]=1.This has just produced error.
For this reason, be the situation of odd number for Z, the present invention adopts the complementary operation method to calculate.Because odd number Z is after divided by 2, loss 0.5, and to after the Z/2 negate ,-(Z/2) also lose 0.5, so calculate Z/2-[-(Z/2) by complementary operation] can not give branched measurement value in the ACS module relatively cause error.Still be example with Z=1, through right-shift operation, Z/2=0.Because 0 radix-minus-one complement is-1, thus [(Z/2)]=-1, Z/2-[-(Z/2)]=1.This operation result with floating number is identical, does not cause the loss of fixed-point data.If but dual numbers Z also adopts complementary operation, so because Z/2 does not lose, after the Z/2 negate ,-(Z/2) can lose 1 on the contrary, so should still use complementary operation.
For the parity according to Z adopts different compute modes, BMU of the present invention unit offers the ACS unit with the lowest order of Z.The lowest order of ASC unit judges Z is 0 or 1, then according to judged result decision with supplement or negate opposite number-BM of Branch Computed metric BM.
In addition, on circuit design complementary operation simpler than complementary operation, so adopt this method can reduce the clock cycle of ACS unit.
Fig. 7 A is a circuit diagram, illustration according to the ACS unit 52 of third embodiment of the invention.In the cdma2000 motion, ACS unit 52 comprises processing unit 520, ACS subelement 521, normalization arithmetic element 522 and maximum rating tolerance detecting unit 523.
4 branched measurement value BMa, BMb, BMc and BMd that processing unit 520 receives that upper level BMU unit 51 provide and the lowest order of Z.Processing unit 520 is also asked the opposite number of BMa, BMb, BMc and BMd except BMa, BMb, BMc and BMd itself directly exported to the ACS subelement 521 according to the lowest order of Z, calculate other four branched measurement values.Specifically, when the lowest order of control signal Z is 0, calculate the opposite number of unit 71 by supplement reckoning BMa, BMb, BMc and BMd.When the lowest order of control signal Z is 1, calculate the opposite number of unit 71 by reckoning BMa, BMb, BMc and the BMd that negate.Here, the realization circuit of complementary operation and complementary operation can be constructed according to concrete design philosophy.Four branched measurement values that reckoning obtains also offer ACS subelement 521.
ACS subelement 521 is made up of 8 parallel ACS branch units ACS0-ACS7.At first, these 8 ACS branch units ACS0-ACS7 8 branched measurement values that will receive revert to 16 branch metrics.Then, calculate the absolute value Mdiffa～Mdiffh of the difference of corresponding cumulative metrics value SM0～SM7, routing information Pb0～Pb7 and cumulative metrics value.Then, cumulative metrics value SM0～SM7 is offered normalization arithmetic element 522.Also path P b0-Pb7 is offered path memory 53, the absolute value Mdiffa-Mdiffh of the difference of cumulative metrics value is offered difference memory 56 (referring to Fig. 5).
Because in the SOVA algorithm, the cumulative metrics value is signed number, therefore when doing normalization, do not need to look for maximum or minimum value in the cumulative metrics value.Although be the mean value that the cumulative metrics value under each state is deducted maximum and minimum value in theory, make all cumulative metrics values be evenly distributed in the positive and negative interval, but in preferred embodiment of the present invention, the normalization computing is any one the cumulative metrics value that the cumulative metrics value under each state was deducted a last moment.Deduct certain cumulative metrics value in a moment arbitrarily, can save in the general Viterbi decoder is circuit scale and the clock cycle of asking the largest cumulative metric to increase when the normalization computing.By Fig. 7 A as seen, the normalization computing of present embodiment only needs the clock cycle of a subtraction.Specifically, normalization arithmetic element 522 comprises 8 parallel normalization computing circuits, and every circuit comprises a subtracter 73 and a state measurement register 74.Subtracter 73 is two-input subtracters, and it deducts the value of state measurement register 74a in the previous moment storage with the cumulative metrics value of current time under each state.Then, the result is stored into respectively among the corresponding state measurement register 74a-74h.
Maximum rating tolerance detecting unit 523 is made of comparator 75, it compares the content SM0-SM7 that is stored among the state measurement register 74a-74h, therefrom select that state with largest cumulative metric, be maximum likelihood state, recall processor so that the initial state that conduct is recalled offers.
Above-mentioned method for normalizing can also further be simplified.Fig. 7 B illustration adding according to fourth embodiment of the invention than the circuit diagram that selects computing unit 52.In this embodiment, except normalization arithmetic element 522, remaining part is all identical with the 3rd embodiment.By Fig. 7 B as seen, the normalization computing here is the cumulative metrics value SM0 that the cumulative metrics value under each state is deducted current time.Can save state measurement register 74a and one road corresponding subtracter 73a like this.Compare with the 3rd embodiment, circuit scale further dwindles, and the clock cycle does not increase.
In sum, utilize the coding/decoding method of decoder of the present invention, can reduce construction unit, reduce the clock cycle, and eliminated the quantization error that addition Item Z/2 brings.For example, for the cdma2000 motion, the BMU unit need calculate 16 branched measurement values originally, can reduce to 4 branched measurement values by simplifying.For the WCDMA motion, original calculative 16 branched measurement values in BMU unit can be simplified 2.The lowest order of 4 of providing according to BMU in ACS unit or 2 branched measurement values and prior information Z, sign bit in the branch metric calculation formula is negated or supplement, thereby return to 16 branched measurement values, and eliminated the quantization error that priori signal Z/2 brings in the SOVA decoding.In the normalization step of ACS unit, the cumulative metrics value under each state is deducted a certain cumulative metrics value of previous moment or current time, reduced clock cycle and circuit scale.
Though embodiments of the invention are based on the coding/decoding method of Turbo code encoder in cdma2000 and the WCDMA motion and RSC sub-encoders thereof, thought set forth in the present invention and circuit structure also belong within the rights protection scope of the present application in the deriving variation under other modes.
In first embodiment, the BMU unit is designed to the compute sign position and is (1,1,1,1), (1 ,-1,1,1), (1,1 ,-1,1), the branched measurement value of (1 ,-1 ,-1,1).But the invention is not restricted to this.The BMU cell design can also be become be used for the compute sign position and be (1 ,-1 ,-1 ,-1), (1,1 ,-1 ,-1), (1 ,-1,1 ,-1), the branched measurement value of (1,1,1 ,-1), perhaps any four can be used as the branched measurement value of calculating the basis.
In a second embodiment, the BMU unit is designed to the branched measurement value of compute sign position for (1,1,1) and (1 ,-1,1).But the invention is not restricted to this.The BMU cell design can also be become be used for the branched measurement value of compute sign position for (1 ,-1 ,-1) and (1,1 ,-1), perhaps any two can be used as the branched measurement value of calculating the basis.
In the 3rd embodiment, the normalization computing in the ASC computing unit is that each cumulative metrics value is all deducted the value of state measurement register 74a in the previous moment storage.But the invention is not restricted to this.The normalization computing can all deduct each cumulative metrics value any one value in the previous moment storage among the state measurement register 74a-74h.
In the 4th embodiment, the normalization computing in the ASC computing unit is the cumulative metrics value SM0 that the cumulative metrics value under each state is all deducted previous moment.But the invention is not restricted to this.The normalization computing can all deduct the cumulative metrics value under each state any one cumulative metrics value SM0-SM7 of current time.
Claims (15)
1. decoder that is used for Turbo code, it comprises:
The branch metric calculation unit is used to calculate the branch path metric value from certain state of certain node to certain state of next node;
Add than selecting computing unit, it comprises:
Add than selecting computation subunit, be used for to a plurality of branched measurement values add up, comparison and selection operation, calculate the absolute value of the difference of cumulative metrics value under each state, cumulative metrics value, and select routing information;
The normalization arithmetic element is used to receive from adding than the cumulative metrics value under each state that selects subelement, and the cumulative metrics value is carried out the normalization computing; And
Maximum rating tolerance detecting unit is used for comparison through normalized cumulative metrics value, therefrom selects the maximum likelihood state with largest cumulative metric, recalls starting point so that provide;
Path memory cell is used to store described adding than the described routing information that selects computing unit to provide;
The state measurement memory cell is used to store described adding than the described accumulative total path metric value that selects computing unit to provide;
The difference memory cell is used to store the described absolute value that adds than the difference of two accumulative total path metric values of the current state of selecting computing unit to calculate;
Recall processing unit, according to described maximum likelihood state, carry out the Viterbi traceback computing, and according to from the routing information of path memory and poor from the accumulative total path metric value of difference memory, carry out the computing of parallel backtracking simultaneously of many parallel routes, and export soft information and hard decision;
Symbol modulation is used for the described soft information of recalling processor output is carried out the hard decision modulation, exports soft output; And
Control circuit, it links to each other with above-mentioned each unit, is used to control the contact between these unit;
It is characterized in that described branch metric calculation unit is used to calculate i branched measurement value, 2
N-1≤ i＜2
N+1The bit number that n is exported when importing a bit for the Turbo code sub-encoders, a wherein said i branched measurement value can be extrapolated described adding than selecting needed all the other branched measurement values of computation subunit by asking opposite number computing and recovery operation, and described branch metric calculation unit offers described adding than selecting computing unit with the lowest order of a described i branched measurement value and prior information Z;
Described adding: processing unit than selecting computing unit also to comprise, be used to receive described i branched measurement value that described branch metric calculation unit provides and the lowest order of described prior information Z, according to the lowest order of described Z, calculate the opposite number of a described i branched measurement value, obtain 2
n-i branched measurement value, and described reckoning is obtained with described receive altogether 2
nIndividual branched measurement value offers described adding than selecting computation subunit;
Described add than select computation subunit carry out described add than selection operation before, with receive described 2
nIndividual branched measurement value returns to the number that actual operation needs.
2. decoder as claimed in claim 1 is characterized in that, under the cdma2000 motion, and n=3, and described branch metric calculation unit calculates 4 branched measurement values.
3. branch metric calculation as claimed in claim 1 unit is characterized in that, under the WCDMA motion, and n=2, and described branch metric calculation unit calculates 2 branched measurement values.
4. branch metric calculation as claimed in claim 2 unit is characterized in that, described four branched measurement values are respectively:
BMa=R
0+R
1+R
2+Z/2,
BMb=R
0-R
1+R
2+Z/2,
BMc=R
0-R
1-R
2+Z/2,
BMd=R
0+R
1-R
2+Z/2，
Wherein, BMa-BMd is the branched measurement value that calculates, R
0, R
1And R
2Be respectively the information that decoder receives, Z is a prior information.
5. branch metric calculation as claimed in claim 3 unit is characterized in that, described two branched measurement values are respectively:
BMa=R
0+R
1+Z/2,
BMb=R
0-R
1+Z/2。
Wherein, BMa and BMb are the branched measurement values that calculates, R
0, R
1Be respectively the information that decoder receives, Z is a prior information.
6. decoder as claimed in claim 1, it is characterized in that, described normalization arithmetic element comprises many parallel normalization computing circuits, every the normalization computing circuit all comprises a subtracter and a state measurement register, wherein subtracter is used for the current cumulative metrics value under the corresponding state is deducted the value that previous moment is stored in any one state measurement register, and the state measurement register is used for storage through normalized cumulative metrics value.
7. decoder as claimed in claim 1, it is characterized in that, described normalization arithmetic element comprises: a plurality of subtracters and a plurality of state measurement register, wherein subtracter is used for the cumulative metrics value under the corresponding state is deducted any one cumulative metrics value of current time, and the state measurement register is used for storage through normalized cumulative metrics value.
8. decoder as claimed in claim 1 is characterized in that, described maximum rating tolerance detecting unit is a comparator.
9. a coding/decoding method that is used for the Turbo code decoder is characterized in that it comprises the following steps:
I the branch path metric value of calculating from certain state of certain node to certain state of next node, 2
N-1≤ i＜2
N+1, the bit number that n is exported when being bit of the sub-decoder of Turbo code input, a wherein said i branched measurement value is by asking opposite number computing and recovery operation to extrapolate to add all the other branched measurement values than actual needs in the selection operation process;
The lowest order of prior information Z is provided;
According to the lowest order of described Z, calculate the opposite number of a described i branched measurement value, obtain 2
n-i branched measurement value;
2 of i branched measurement value that obtains according to described calculation procedure and the acquisition of described reckoning step
n-i branched measurement value recovers all branched measurement values that actual operation needs;
All branched measurement values that described recovering step is obtained add up, comparison and selection operation, calculate the absolute value of the difference of cumulative metrics value each state under, cumulative metrics value, and the selection routing information;
The cumulative metrics value is carried out the normalization computing;
Relatively, therefrom select maximum likelihood state with largest cumulative metric through normalized cumulative metrics value;
Store described routing information, described accumulative total path metric value, and the absolute value of the difference of two accumulative total path metric values of current state;
According to described maximum likelihood state, carry out the Viterbi traceback computing, and poor according to described routing information and described accumulative total path metric value, carry out the computing of parallel backtrackings simultaneously of many parallel routes, and export soft information and hard decision;
The soft information of described output is carried out the hard decision modulation, export soft output.
10. coding/decoding method as claimed in claim 9 is characterized in that, described calculation procedure comprises calculates 4 branched measurement values.
11. coding/decoding method as claimed in claim 9 is characterized in that, described calculation procedure comprises calculates 2 branched measurement values.
12. coding/decoding method as claimed in claim 10 is characterized in that, described 4 branched measurement values are:
BMa=R
0+R
1+R
2+Z/2,
BMb=R
0-R
1+R
2+Z/2,
BMc=R
0-R
1-R
2+Z/2,
BMd=R
0+R
1-R
2+Z/2，
Wherein, BMa-BMd is the branched measurement value that calculates, R
0, R
1And R
2Be respectively the information that decoder receives, Z is a prior information.
13. coding/decoding method as claimed in claim 11 is characterized in that, described 2 branched measurement values are:
BMa=R
0+R
1+Z/2,
BMb=R
0-R
1+Z/2。
Wherein, BMa and BMb are the branched measurement values that calculates, R
0, R
1Be respectively the information that decoder receives, Z is a prior information.
14. coding/decoding method as claimed in claim 9 is characterized in that, described normalization step comprises any one the cumulative metrics value that each current cumulative metrics value is deducted previous moment.
15. coding/decoding method as claimed in claim 9 is characterized in that, described normalization step comprises any one the cumulative metrics value that each cumulative metrics value is deducted current time.
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| CNB001155946A CN1155161C (en) | 2000-05-08 | 2000-05-08 | Tebo code decoder and its decoding method |
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| CN101911502A (en) * | 2008-01-04 | 2010-12-08 | 高通股份有限公司 | Decoding scheme using a-priori information about transmitted messages |
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| CN101639686B (en) * | 2007-06-20 | 2014-06-04 | 爱方有限责任公司 | System and method for interfacing device |
| CN101217285B (en) * | 2007-12-28 | 2010-09-29 | 宁波中科集成电路设计中心有限公司 | A Viterbi decoder adaptable with DRM standard |
| CN101911502A (en) * | 2008-01-04 | 2010-12-08 | 高通股份有限公司 | Decoding scheme using a-priori information about transmitted messages |
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| WO2012034398A1 (en) * | 2010-09-15 | 2012-03-22 | 中兴通讯股份有限公司 | Method and device for implementing viterbi decoding |
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