CN1323101A - Generation method and generator for pseudo-random noise sequence with fast sliding phase - Google Patents
Generation method and generator for pseudo-random noise sequence with fast sliding phase Download PDFInfo
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- CN1323101A CN1323101A CN01105254A CN01105254A CN1323101A CN 1323101 A CN1323101 A CN 1323101A CN 01105254 A CN01105254 A CN 01105254A CN 01105254 A CN01105254 A CN 01105254A CN 1323101 A CN1323101 A CN 1323101A
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Abstract
The shift register state of PN sequence with N continuous "0" states as initial value and generating period of 2 to the power n is written into memory in order, the counter is then started, and the shift register outputs PN sequence by using N continuous "0" states as initial time. While needing sliding, the sum of counted value and sliding phase data is used to address so as to take memory content and feed it into the shift register and required PN sequence is output in the next clock period. The generator includes PN sequence forming circuit, period lengthening circuit, memory and phase sliding control circuit.
Description
The present invention relates to base band processing device and manufacture method thereof in a kind of code division multiple access (CDMA) communication system, specifically, is a kind ofly can generate that to add long period be 2
NPN (pseudo noise) sequencer, this PN sequencer comprises that one-period is 2
N-1 longest linear PN sequencer, it adds long circuit by a sequence and connects " 0 " to the N-1 in the PN sequence and increase to N and connect " 0 ", and making cycle of this PN sequence extend is 2
N, more usefully, this PN sequencer can be realized phase slip fast under the control of input signal.
No matter be the forward channel or the transmitting terminal of backward channel in cdma communication system at present, in order to guarantee the orthogonality of I (homophase series), Q (orthogonal family) channel, the cycle of all having used is 2
NThe PN sequence channel is carried out four expansions mutually, therefore, in order to catch the channel that transmitting terminal is sent effectively and quickly, correctly solve channel information at receiving terminal, also must have one group also to be 2 with corresponding, cycle of transmitting terminal
N, and the may command phase place PN sequence of sliding fast carry out relevant with the channel data that receives, in relevant process, can slide fast to the phase place of local PN sequence as required, thereby give security for correctly solving each channel so that obtain the maximum relevant apace with the data that receive.
In existing P N sequencer, the method that has utilization that shift register states at different levels are carried out mask obtains the PN sequence of the desired number of phases of having slided, see the disclosed (title: " having fast offset adjustment, length and be the pn sequence generator of 2 power " of Patent Office of the People's Republic of China, applicant: Qualcomm Inc, the patent No.: CN93103556), have the following disadvantages though its disclosed technical scheme has advantages such as can realize that the PN sequence phase slides fast and the used resource of circuit is less:
1) phase place of Chan Shenging slidably the PN sequence come out through logical circuit, have bigger phase delay inevitably;
2) initial state that is used to generate the longest linear shift register sum counter of PN sequence in the circuit has strict corresponding relationship, and corresponding relation is complicated, must be in advance through complicated calculating;
3) used more logical circuit in the circuit, and the logical relation more complicated.
The objective of the invention is to overcome the deficiency of PN sequencer of the slidably phase place of above-mentioned patent, the slidably new method and apparatus of the PN sequence of phase place of a kind of generation is provided.
Technical solution of the present invention is:
Utilize the RAM memory technology that the various states of the shift register that generates the PN sequence are stored in advance by the time sequencing that the PN sequence takes place, the state value in the corresponding PN initial moment of sequencer of the zero-address cell value of memory, follow the tracks of the phase shifts number of PN sequence then synchronously by the counting output of a N digit counter, this counter also begins to count from the initial moment of PN sequencer, when the phase slip order is effective, the count value of counter must add the number of phases that needs slip, the N bit output of counter is used for memory is carried out addressing simultaneously, when the memory read signal is effective with the state value of this address location to shift register set, with the PN sequence that obtains fast sliding.
As mentioned above, but the generation method of the PN sequence of fast sliding phase of the present invention, and its step comprises:
(1) proper polynomial or the recurrence multinomial generation cycle according to the PN sequence is 2
N-1 longest linear PN sequence,
(2) cycle of above-mentioned longest linear PN sequence is added grow to 2
N,
(3) with N position bit wide, 2
N2 of the RAM memory stores shift register that the position is long
NIndividual state, and with the state of N the shift register of company when " 0 " of output as initial state, this initial state is deposited in the zero-address space of this RAM memory, afterwards, the virtual condition that occurs with clock by this shift register successively along with the operation of clock is stored in this RAM memory with the ascending order of address space
(4) count from zero with the clock cycle constantly with the initial state of a N digit counter, and the control PN sequence phase slip data value of the output valve of this N digit counter and input carried out add operation at above-mentioned shift register,
(5) under the asserts signal of reading useful signal and this shift register of above-mentioned RAM memory acts on simultaneously, state value in the output valve of this N digit counter RAM storage address pointed is placed in this shift register, like this, this shift register is just exported the PN sequence of the designated phase of having slided when the rising edge of next clock arrives.
The cycle to 2 of this longest linear of said lengthening PN sequence
N, be to connect " 0 " to its N-1 of PN Sequence Detection, when last connected " 0 " output, allowing the clock of register stop one-period increased by one " 0 " output, made N-1 to connect " 0 " and become N even " 0 ", thereby, make the cycle of this PN sequence increase to 2
N
But according to the made phase place of the generation method of the PN sequence of above-mentioned fast sliding phase of the present invention PN sequencer slidably, it comprises that a PN bit sequence forms circuit, a counter, and characteristics are: also have:
A. a PN sequence period adds long circuit, its have two relatively inputs respectively with this PN sequence form the output of circuit and one in addition the set condition output be connected; Its output then joins with the Enable Pin of this PN sequence formation circuit;
B. a PN sequence phase Sliding Control circuit, its input that contains N bit slip phase data that n connection peripheral control unit send into, corresponding positions is with the NAND gate of the input that is connected the slip phase control signal, connect the adder of the output of the output of this NAND gate and this counter respectively, the output of this adder is connected with the input of this counter, and the Enable Pin of this counter is subjected to the control of peripheral control unit;
C. a RAM memory, its address bus is connected with the output of this adder, and its data/address bus hangs on the system data bus and is connected with data assemblings (LOAD DATA) end that this PN sequence forms circuit;
Above-mentioned PN sequence period adds long circuit and comprises comparator, d type flip flop and another d type flip flop and two input nand gates that are connected with circuit successively; This PN sequence forms circuit and then comprises N level shift register and insert XOR gate between the register of corresponding positions according to PN sequence signature polynomial equation.
The present invention compares with the existing slidably PN sequencer of phase place has substantial progress:
1) phase place of the present invention slidably the PN sequence be directly to come through sequence circuit output, therefore, phase delay is less;
2) corresponding relation of the initial state of shift register sum counter is very simple, and that need only fix is a kind of, just must not rechange after setting;
3) logical relation of circuit is simple.
Accompanying drawing of the present invention is simply described as follows:
Fig. 1 is that longest linear PN sequence of the present invention forms circuit theory diagrams.
Fig. 2 is slidably phase place PN sequencer circuit theory diagrams of the present invention.
Fig. 3 is a PN sequencer circuit sequence schematic diagram of the present invention.
Longest linear PN sequence formed schematic block circuit diagram when Fig. 4 was another embodiment of the present invention N=4.
Table 1 illustrates the slidably internal circuit cell signal state value of phase place PN sequencer of the present invention.
According to Fig. 1-Fig. 4 and table 1, provide two embodiment of the present invention below:
The generation phase place that the present invention proposes is the method for PN sequence slidably, may further comprise the steps:
1) proper polynomial or the recurrence multinomial generation cycle according to the PN sequence is 2
N-1 longest linear PN sequence,
2) cycle 2 of the above-mentioned longest linear PN sequence of lengthening
N-1 is 2
N, detect N-1 and connect " 0 ", when last connects " 0 " output, allow the clock of shift register stop one-period, so just can increase by one " 0 " output, make N-1 even " 0 " become N even " 0 ", also make the cycle of this sequence increase to 2
N,
3) with N position bit wide, 2
N2 of the RAM memory stores shift register that the position is long
NIndividual state, the state of shift register is an initial state when connecting " 0 " with N of output, this state is deposited in the zero-address space of memory, afterwards, along with virtual condition that shift register occurs with the clock ascending order stored into memory with address space is pressed in the operation of clock successively
4) counted from zero with the clock cycle constantly by the initial state of a N digit counter at shift register, the slip data value that the output valve of this N digit counter can be slided with the control PN sequence phase of input carries out add operation,
5) read under the effect of useful signal and shift register asserts signal at the RAM memory space, state value in the address of the RAM memory that the output valve of this N digit counter is pointed is placed in the shift register, and the PN sequence of the designated phase of having slided when the rising edge of next clock arrives appears on the output port.
Manufacture slidably PN sequence device of two phase places according to said method of the present invention, one is N=15, and another is N=4.
Following elder generation is 2 with N=15, generation cycle
15-1 PN sequencer is that example is described in further detail.
Figure 1 shows that N=15, generation cycle are 2
15-1 PN sequence forms the circuit theory diagrams of circuit.Be that a longest linear shift sequence with 15 grades of shift registers forms circuit among the figure, because N=15, so the cycle of the PN sequence that this circuit produces is 2
15-1=32767.Be easy to from figure find out that the proper polynomial equation of this longest linear shift sequence generator is:
PN=X
15+X
13+X
9+X
8+X
7+X
5+1????(1)
This PN sequence forms circuit 10 by one group of shift register 12
1-12
15With the XOR gate 14 of placing according to the proper polynomial equation
1-14
5Connection forms, and wherein register 12
1-12
4 Output link register 12 respectively
2-12
5Input, register 12
6 Output link register 12
7Input, register 12
10-12
12 Output link register 12 respectively
11-12
13Input, register 12
14 Output link register 12
15Input, register 12
5, register 12
7-12
9With register 12
13Output link XOR gate 14 respectively
1-14
5An input, register 14
1-14
5 Output link register 12 respectively
6, register 12
8-12
10With register 12
14Input, register 12
15Output, the PN sequence output that forms circuit 10 just feedbacks, as register 12
1Input signal, XOR gate 14
1-14
5Another input by register 12
15Provide, this PN sequence forms the output of circuit 10 as output bus 18, and signal q[15:1 is provided].
Shift register 12
1-12
15Another the group input link to each other with bus 16 (system data bus), when its set useful signal (LOAD ENABLE) is effective, be used for receiving direct set data from the memory space output of RAM memory, these registers also have an input signal SYS-EN, and it is a shift register 12
1-12
15Enable signal, have only as SYS-EN (enabling) when signal is effective shift register 12
1-12
15Just work.
The PN sequence forms the registers at different levels 12 in the circuit 10
1-12
15In the shifting function undertaken by predetermined logic of signal be under the effect of unified clock signal (not drawing among the figure), to carry out, this PN sequence forms the output of circuit 10 except that the output as bus 18, what have also is input to XOR gate 14
1-14
5Produce the input signal of next stage relevant register, when enable signal (SYS-EN) is effective, these registers 12 at different levels
1-12
15Input just under the effect of clock signal, begin action.
Figure 2 shows that the circuit theory diagrams that can generate PN sequencer with fast phase slip.The PN sequence period adds long circuit 20 ' and forms circuit 10 with linear PN sequence and link to each other among the figure, and the PN sequence period adds long circuit 20 ' and comprises the comparator 20, d type flip flop 21,22 and two inputs that connect with circuit successively and 23.The output bus 18 that linear PN sequence forms circuit 10 is linked an input of comparator 20, each state value of its internal displacement register when a fix N bit value of another input termination output 17 of comparator 20, this numerical value are exactly these PN sequence formation circuit 10 N-2 companies of output " 0 ".The input of d type flip flop 21 is linked in the output of comparator 20, the output of this d type flip flop 21 is linked the input of another d type flip flop 22, the output of this d type flip flop 22 is linked an input with door 23, its another output also links to each other with input with door 23, and two inputs are linked the Enable Pin (SYS-EN) 19 that this PN sequence forms circuit 10 with the output of door 23.
The output (PN-OUT) that linear PN sequence forms circuit 10 adds under the effect of long circuit 20 ' at the PN sequence period, its the longest company " 0 " section is increased to N by N-1, make the number that comprises " 0 " and " 1 " in the PN sequence equate like this, have the long company in N position " 1 " section in the PN sequence simultaneously and connect " 0 " section.
Data on the output bus 18 of Fig. 2 neutral line PN sequence formation circuit 10 and both given data " 0010...0 " comparisons, show that when the two is equal this linearity PN sequence forms circuit 10 and exported N-2 even " 0 ", also allow this moment next state " 0100...0 " to occur, when state " 0100...0 " when appearing at output bus 18, this moment is by d type flip flop 21,22 and two inputs enable (SYS-EN) invalidating signal with door 23 array outputs, the register (being made of trigger) that linear PN sequence forms in the circuit 10 keeps a clock cycle constant, in other words, make state " 0100...0 " two clock cycle occur, so just " a 0 " value is inserted into this PN sequence and forms in N-1 the company " 0 " among the output PN-OUT of circuit 10 and gone.
It should be noted that state " 0010...0 " is a numerical value through drawing after calculating in advance, it just is N-1 shift register group 12 that connects " 0 " to occur
1-12
15Preceding state, compare if change the state value that an other class value goes to form on the output bus 18 of circuit 10 with linear PN sequence into, then its output PN-OUT will obtain full of prunes output.
Constitute PN sequence phase Sliding Control circuit 30 ' with door 31, adder 32 sum counters 30 among Fig. 2.With door 31 two inputs are arranged, the N Bit data (SHIFT-NUMBER) that requires PN sequencer phase slip that the reception peripheral control unit is sent, another input receives the slip data useful signal (ADD-EN) of peripheral control unit input.Though only drawn one and door 31 among Fig. 2, be actually expression N and door 31 are arranged, each is connected the not coordination of N Bit data with door 31, and respectively with slip data useful signal (ADD-EN) with, link an input of adder 32 with the output of door 31, another input of this adder 32 receives from the N Bit data on the output 33 of counter 30, and the output 34 of this adder 32 is linked the address bus (COUNTER NUMBER) of memory 40 on the one hand, feeds back to the input of counter 30 on the other hand again.
The dateout of this counter 30 (COUNTER OUT) is sent to goes to participate in sum operation in the adder 32, with the N bit slip phase place of door 31 input data only slip phase control signal (ADD-EN) effectively the time (high level) just be output in the adder 32 and pass through and add 1 and (be contained in the counter circuit, do not draw) output signal on the output 33 of counter 30 of counting carries out sum operation, addition result directly outputs on the address bus of memory 40, at slip phase control signal (ADD-EN) between dynamic stage, input and door 31 slip phase place input data and ADD-EN useful signal with after be zero, do not change the output valve of counter 30 in adder 32, this hour counter 30 is by adding 1 counting rule counting normally.
It is noted that, effective duration of slip phase control signal (ADD-EN) should be not more than a clock cycle of counter 30, and should keep correct sequential relationship with clock signal, hold mode is stable before promptly should arriving at the rising edge of clock, and detailed sequential relationship is seen Fig. 3.
The address bus of memory 40 receives the N bit output from adder 32 outputs 34, data/address bus is a bidirectional bus, CS is as the chip selection signal of memory 40, memory 40 also has two input signal READ-EN (reading useful signal) and WRITE-EN (with imitating signal), WRITE-EN sum counter 30 is together going to store in the 2N of the shift register in the PN sequencer 10 12 the state write memory 40 when initializes memory, when needs allow the phase slip of output signal (PN-OUT) of PN sequencer 10, earlier the count value that the data that will slide are made counter 30 by bus SHIFT NUMBER relatively with currency (back) increase (minimizing) SHIFT NUMBER number forward, make READ-EN effective, the value of the output of counter 30 storage address unit pointed just is output on the input data bus 16 of PN sequencer 10 like this, data when the rising edge of next clock arrives on the data/address bus 16 are placed into the shift register in the PN sequencer 10, and the PN sequence of having slided just appears on the output (PN-OUT) of PN sequencer 10.
Be example below again with N=4, when counter 30 just count slide when full order effectively and the slip phase data when being 8 lengthening PN sequence form the course of work of circuit 10 '.Table 1 has been listed the count value in the counter 30 in the circuit, the PN sequence forms shift register 12 in the circuit 10 '
1-12
4State value and PN sequence output valve at sequenced corresponding relation, in memory 40 storage state value also with shift register 12
1-12
4By the value unanimity of counting output, Fig. 3 is the sequential relationship of each coherent signal.
The defined feature polynomial equation is as shown in Equation (2):
PN=X
4+X
3+1????(2)
Corresponding side circuit as shown in Figure 4.
We notice from table 1, and the PN sequence forms shift register 12 in the circuit 10 '
1-12
4State " 0100 " two clock cycle have appearred, this be since the cycle add long circuit 20 ' at shift register 12
1-12
4When being in " 0100 ", comparator 20 detects two input values and equates, these comparator 20 output high level, and this high level is being delayed time a clock cycle through d type flip flop 21,22 with door 23 back, export a low level that continues a clock cycle width, made shift register 12
1-12
4Enable signal (SYS-EN) is just invalid when having exported state " 0010 ", just state " 0010 " has been kept a clock cycle, like this, two clock cycle have appearred in state " 0010 " altogether, just the position that occurs 3 " 0 " in the PN sequence has continuously been increased by one " 0 " more, made the cycle of PN sequence become 16.
From table 1, it can also be seen that, the phase slip data can place on the bus SHIFT NUMBER in advance, it is also inoperative when set useful signal (ADD-EN) is invalid, have only that SHIFT NUMBER just is added on the output valve of counter 30 when ADD-EN is high level, this is engraved under the situation of memory 40 read signals effective (unlisted in the table), the address appears on the data/address bus 16 of memory 40 for the content " 1101 " of " 1000 " in the memory 40, when input shift register 12
1-12
4Rising edge clock be placed into shift register 12 when arriving
1-12
4In, the sequential of expression said process is seen Fig. 3.
Table 1
| The phase slip data | The phase slip control signal | Counter status | The shift register state | Storage address | Memory content | ??PN- ??OUT |
| ?0000 | ????0 | ????0 | ?1000 | ?0000 | ?1000 | ????1 |
| ?0000 | ????0 | ????1 | ?1001 | ?0001 | ?1001 | ????1 |
| ?0000 | ????0 | ????2 | ?1011 | ?0010 | ?1011 | ????1 |
| ?0000 | ????0 | ????3 | ?1111 | ?0011 | ?1111 | ????1 |
| ?0000 | ????0 | ????4 | ?0111 | ?0100 | ?0111 | ????0 |
| ?0000 | ????0 | ????5 | ?1110 | ?0101 | ?1110 | ????1 |
| ?0000 | ????0 | ????6 | ?0101 | ?0110 | ?0101 | ????0 |
| ?0000 | ????0 | ????7 | ?1010 | ?0111 | ?1010 | ????1 |
| ?1000 | ????0 | ????8 | ?1101 | ?1000 | ?1101 | ????1 |
| ?1000 | ????0 | ????9 | ?0011 | ?1001 | ?0011 | ????0 |
| ?1000 | ????0 | ????10 | ?0110 | ?1010 | ?0110 | ????0 |
| ?1000 | ????0 | ????11 | ?1100 | ?1011 | ?1100 | ????1 |
| ?1000 | ????0 | ????12 | ?0001 | ?1100 | ?0001 | ????0 |
| ?1000 | ????0 | ????13 | ?0010 | ?1101 | ?0010 | ????0 |
| ?1000 | ????0 | ????14 | ?0100 | ?1110 | ?0100 | ????0 |
| ?1000 | ????0 | ????15 | ?0100 | ?1111 | ?0100 | ????0 |
| ?1000 | ????1 | ????8 | ?1101 | ?1000 | ?1101 | ????1 |
| ?1000 | ????0 | ????9 | ?0011 | ?1001 | ?0011 | ????0 |
| ?1000 | ????0 | ????10 | ?0110 | ?1010 | ?0110 | ????0 |
Claims (5)
1. the generation method of a pseudo-random noise sequence with fast sliding phase, its step comprises:
(1) proper polynomial or the recurrence multinomial generation cycle according to the PN sequence is 2
N-1 longest linear PN sequence,
(2) cycle of above-mentioned longest linear PN sequence is added grow to 2
N,
(3) with N position bit wide, 2
N2 of the RAM memory stores shift register that the position is long
NIndividual state, and with the state of N the shift register of company when " 0 " of output as initial state, this initial state is deposited in the zero-address space of this RAM memory, afterwards, the virtual condition that occurs with clock by this shift register successively along with the operation of clock is stored in this RAM memory with the ascending order of address space
(4) count from zero with the clock cycle constantly with the initial state of a N digit counter, and the control PN sequence phase slip data value of the output valve of N digit counter and input carried out add operation at above-mentioned shift register,
(5) under the asserts signal of reading useful signal and this shift register of above-mentioned RAM memory acts on simultaneously, state value in the output valve of this N digit counter RAM storage address pointed is placed in this shift register, like this, this shift register is just exported the PN sequence of the designated phase of having slided when the rising edge of next clock arrives.
2. the generation method of pseudo-random noise sequence with fast sliding phase according to claim 1 is characterized in that, the cycle to 2 of this longest linear PN (pseudo noise) sequence of said lengthening
NBe to connect " 0 " to its N-1 of PN Sequence Detection, when last connected " 0 " output, allowing the clock of register stop one-period increased by one " 0 " output, made N-1 to connect " 0 " and become N even " 0 ", made the cycle of this PN sequence increase to 2
N
3. a phase place of making by the generation method of the described pseudo-random noise sequence with fast sliding phase of claim 1 pseudo-random noise sequence generator slidably, comprise that a N bit linear PN sequence forms a circuit (10) and a counter (30), it is characterized in that also having:
A. a PN sequence period adds long circuit (20 '), its have two relatively inputs form the output (18) of circuit (10) and one with this PN sequence respectively other be connected by set condition value output (17); Its output then joins with the Enable Pin (19) of this PN sequence formation circuit (10);
B. a PN sequence phase Sliding Control circuit (30 '), it contains the NAND gate (31) of the input of the N bit slip phase data corresponding positions that n connection peripheral control unit send into and the input that is connected the slip phase control signal, connects the adder (32) of the output (33) of the output of this NAND gate (31) and this counter (30) respectively, the output (34) of this adder (32) is connected with the input (35) of this counter (30), and the Enable Pin of this counter (30) is subjected to the control of peripheral control unit;
C. a RAM memory (40), its address bus (41) is connected with the output (34) of this adder (32), and its data/address bus (42) hangs over that system data bus (16) is gone up and is connected with the data assembling end of this PN sequencer (10).
4. phase place according to claim 3 is pseudo-random noise sequence generator slidably, it is characterized in that said PN sequence period adds long circuit (20 ') and comprises comparator (20), d type flip flop (21), d type flip flop (22) and two input nand gates (23) that are connected with circuit successively.
5. phase place according to claim 3 is pseudo-random noise sequence generator slidably, it is characterized in that said PN sequence forms circuit (10) and comprises N level shift register and insert XOR gate between the register of phase place according to PN sequence signature polynomial equation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103440119A (en) * | 2013-07-08 | 2013-12-11 | 中国航空无线电电子研究所 | M sequence generator-based primitive polynomial pseudo-random sequence generator |
| CN104426651A (en) * | 2013-08-30 | 2015-03-18 | 上海复旦微电子集团股份有限公司 | Data processing method and device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101562592B (en) * | 2009-05-22 | 2013-03-20 | 哈尔滨工业大学 | Method for integrating phase factor based on memory unit |
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2001
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103440119A (en) * | 2013-07-08 | 2013-12-11 | 中国航空无线电电子研究所 | M sequence generator-based primitive polynomial pseudo-random sequence generator |
| CN103440119B (en) * | 2013-07-08 | 2016-03-23 | 中国航空无线电电子研究所 | A kind of primitive polynomial pseudo-random sequence generator based on m sequencer |
| CN104426651A (en) * | 2013-08-30 | 2015-03-18 | 上海复旦微电子集团股份有限公司 | Data processing method and device |
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