CN1322549C - 深沟渠电容器以及电阻之同时形成 - Google Patents
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Abstract
一种小型电阻系利用与形成一DRAM单元之一沟渠电容器所使用之步骤相同的许多步骤而加以形成于一集成电路之中,特别是在掺杂该基板以形成该电容器之底部平板的步骤之后,于该沟渠内部沉积一重掺杂之锗层,再于该沟渠中沉积具有所需电阻率之多晶硅,然后,移除该锗层并留下足够在该沟渠底部形成一欧姆接触的锗层。
Description
技术领域
本发明所属之领域系为集成电路加工,包括具有电阻之电路。
背景技术
当一电路需要一电阻时,传统之加工系会使用一多晶硅条、或者是在基板中之一植入区域,而尺寸以及掺杂的量系会加以设定以产生该所需的电阻值。但这两种方法系皆为平面的,并且需要实质的芯片区域,以及额外的加工步骤,才能产生一不同于多晶硅互连或源极以及漏极之电阻率的电阻率。
随着IC尺寸的缩减,一平面电阻所需要的额外面积变得更是一种负担。
美国专利第6,281,068 B1号系揭示一种在一特殊聚合物的帮助之下,于一深沟渠电容器中形成一埋藏平板的方法。
而在文章“Germanium as a versatile material for low-temperature micromachining”,Biao Li et al,Journal ofmicroelectromechnical systems,vol.8,no.4,December1999,p 366 to p 372中,有关锗薄层的特质系有所研究。
发明内容
本发明系相关于一种形成铅直电阻的方法,其系使用在一DRAM中用以形成一深沟渠电容器的步骤。
本发明之特色在于,在一深沟渠中使用一锗衬层,而其系可选择性地加以移除,以在位于该沟渠中之一铅直电阻构件与该基板之间进行绝缘,但却同时能与该沟渠之底部进行欧姆接触。
附图说明
第1图:其系显示根据本发明而加以架构之一电阻的部分概要、部分绘制形式之一剖面图;
第2图:其系显示在程序中,主要步骤之部分概要、部分绘制形式的一剖面图;
第3图:其系显示被架构为与第1图之该电阻平行的一电容器的部分概要、部分绘制形式之一剖面图;以及
第4图:其系表示根据本程序而加以架构的图式形式的一电阻组。
具体实施方式
现在,请参阅第1图以及第2图,其系显示根据本发明而部分架构之电阻的剖面图,其系标示以符号100,并系形成于基板10之中。该基板10典型地系包括一半导体材质,例如,单晶硅,并且,系可包括其它导电层或其它半导体组件,举例而言,例如,晶体管或二极管。或者,该基板10亦可二者择一地包括化合物半导体,例如,砷化镓(GaAs)、磷化铟(InP)、硅/锗(Si/Ge)、或碳化硅(SiC)。
一衬垫氮化物112系显示为沉积覆盖于该基板10之上,该衬垫氮化物112系可包括,举例而言,100至300nm的氮化硅。而一可选择地氧化层12亦可被沉积于该氮化物112之下,以降低应力效应(stresseffects)。晶圆100系利用传统的微影技术而加以图案化,并且加以蚀刻以形成通过氮化物112且穿透基板10的深沟渠114,以到达一单元深度,深沟渠114的例子系为大约深6μm,直径200nm,或是深10μm,直径100nm,并且其将取决于使用时的特殊基础原则。
在一预备步骤中,在该DRAM单元数组中之该沟渠电容器的埋藏平板(buried plate)系藉由下列步骤而加以形成。(i)将一剂量的As离子植入该沟渠的底部,而在回火之后,这将会形成区域30,并且,藉由将N+之已As掺杂之玻璃沉积于该沟渠之中且将其加热以使该As离子扩散至该基板10之中,而形成区域30。而形成区域30的另一方法是气相掺杂,例如,于高温时注入砷化三氢(arsine)气体,并将该砷化三氢气体扩散进入硅侧壁之中,以形成一高度掺杂的区域30。接着,(ii)n-掺杂层20(称为N-带)系藉由将一剂量之N-型离子植入P-型基板之晶圆表面下大约1μm的深度而加以形成。此埋藏平板(形成自区域20以及30)系进行延伸以接触一至少两的沟渠组,并且系透过基板的导电性以及透过到达一上升至该基板表面之一连接的可选择低阻抗路径(未显示),而与一电源供给终端(通常是接地)相联系。
一N+锗层55(5nm至50nm厚)系已经被沉积于该沟渠之内壁之上,依次,一N-掺杂多晶硅的栓60系被加以沉积,以使该沟渠被具有正确电阻率的材质所填满,以形成具有所需电阻值的电阻。
现在,请参阅第2图,由于Ge层55系为导电的,因此,其系于一计时的蚀刻中加以回蚀,而留下以号码55标示之一部份于该底部,而此会于该埋藏平板30以及该电阻60之积体(bulk)之间形成一欧姆接触,至于留下来的开放空间则在第2图中以号码52标示。在第1图中,空间52系被习知的任何介电质45,例如,氧化物、氮化物、或氮化氧化物(nitrided oxide),所加以填满,一例子就是CVD氮化物。举例而言,该Ge蚀刻可以是利用SF6/H2/CF4电浆的一RIE(Beolwick et al.,IBM Technical Disclosure Bulletin1992)、或是利用KOH(Carms,et al.J.Electrochemical Soc.142,4,p1260,10:1)或HNO3(B.Li et al.,J.MicroelectromechanicalSystems,8,4p366)之有较佳选择性(600∶1)的一湿蚀刻。在另一例子中,因为在该Ge以及该多晶硅60之间的蚀刻率乃是相当大,因此,对于多晶硅60或是对该基板10而言,皆不会有重大的损害。于第2图中所显示之步骤的结尾,电阻100系在其底部与该埋藏平板进行接触,并且,其系具有能够与其它电路组件接触的一顶层表面。
在一较佳实施例中,一DRAM数组之该等电容器的该等深沟渠系与该等电阻同时形成,这是因为该深沟渠乃是一缓慢且昂贵的程序。如果需要的话,该等电阻的该等沟渠系可以与该等电容器于不同的时间进行蚀刻(或者,若是没有DRAM数组在一特别之芯片上时),但是更经济的是同时蚀刻该等沟渠,并且,若有需要的话,于不同的时间填满该等电容以及该等电阻。若是内部电容器平板之电阻率必须大大地不同于该电阻材质60的电阻率时,则可能需要不同之充填,此亦将需要在该沟渠中之该锗层有相反的极性(p-型)。
现在,请参阅第3图,其系显示相对应之DRAM单元。蚀刻该沟渠以及形成该埋藏平板的预备步骤将是相同的,但是,需要用来将该电阻连接至地的该欧姆接触却不能容许出现在该电容器中,另一方面,在该电容器中,该Ge层不能被剥除,因为该已掺杂之多晶硅中心栓将会掉落下来并使该电容器短路,据此,在该Ge衬层被沉积至该电容器中之前,一薄的(28nm)热氧化层52系加以形成,对该电阻以及该电容器两者都一样,该Ge衬层55系加以沉积并形成凹处。
接着,在该电容器的一分开步骤中,一热处理系于压力低于100micro-Torr的真空中、温度范围介于450℃至700℃之间,执行5至10分钟,而在此热处理期间,该Ge衬层将与该氧化物进行反应,以形成GeO 57,而其系会绝缘该电容器的底部部分。对该电阻以及该电容器而言,剩下的该空间52系会被以相同方法进行填满,与第1图以及第3图一样留下介电质45。氧化物52的厚度将进行设定,因此,符合该电容器之漏需求(leakage requirement)的一GeO层57系会加以形成,但是,并不需要所有的Ge皆进行反应,举例而言,一厚度2.5nm至25nm的氧化物即足够用于Ge的既定厚度范围。
在第3图的上部,系具有一习知DRAM单元结构的概要代表图,传送晶体管(pass transistor)82系利用埋藏的带漏极84以及源极86(buried strap-drain and source)而存取该DRAM单元,一绝缘覆盖83则会保护内部平板62远离电接触。
可选择地,相同的DRAM型态传送晶体管可以被形成于该电阻100之顶部,第4图系举例说明对于如此之一排列的可能使用。一具n个电阻的电阻组,其电阻404-1至404-n并联连接于节点405以及接地之间,每一电阻系具有相同的值,R。若需要一电阻值R时,则仅一晶体管404-1会被开启,若需要一电阻值R/2时,则两晶体管会被开启,外部的接触(或是内部的软件)系使得电路设计者可以替净电阻选择一值(或者是允许最后的使用者选择一值)。
这些电阻的其它使用对熟习此技艺之人而言,将是非常的显而易见,例如,将两电阻串联连接,其中一在一p井中伴随着该埋藏平板连接至接地,而另一在一n井中伴随着该埋藏平板连接至该电源供给,这将使得在该两电阻之间的连接节点可以被设定在一中间电压。
接下来的表格系举例说明一较佳实施例,其中,仅属于该电阻的步骤系位于左边栏,而仅属于该电容器的步骤则位于右边栏。
电阻 | 电容器 |
准备该基板 | |
蚀刻该沟渠 | |
形成该埋藏平板(于该沟渠之底部植入As、沉积已As掺杂之玻璃、将As扩散进入该基板、剥除该玻璃) | |
薄的热氧化物 | |
沉积N+Ge | |
填充N+掺杂之多晶硅,平面化 | |
于计时蚀刻中移除,于底部留下一已定义之Ge层 |
于沟渠底部形成Ge氧化物 | |
在Ge先前的位置中沉积介电质 | |
(可选择地-形成氧化颈层、埋藏带、传送晶体管) | 形成氧化颈层、埋藏带、传送晶体管 |
于底部欧姆接触 | 于底部电容器绝缘 |
在此表格中,该用词“准备该基板”系代表预备步骤,例如,衬垫氧化物、衬垫氮化物、临界植入等。
当本发明已经藉由一单一实施例而加以叙述时,熟习此技艺之人将可以了解,本发明系可以在不脱接下来之权利要求的精神以及范围的情形下,以各式的改变形式而加以实行。
Claims (7)
1.一种于一半导体基板(10)中形成至少一铅直的电阻(100)的方法,其包括下列步骤:
准备该基板(10);
于该基板中蚀刻一沟渠;
于该沟渠下部的外侧形成一埋藏导电平板(30);
其特征在于:
沉积具有一第一极性型态的一已掺杂锗层(55)于该沟渠内壁以及底部;
将电阻材质(60)沉积于该沟渠的范围之内,并与该已掺杂锗层(55)相接触;以及
依该电阻材质(60)选择性地移除该已掺杂锗层(55)并留下该已掺杂锗层(55)的一底部部分,以作为该电阻材质(60)以及该埋藏平板(30)间的一欧姆接触,藉此,该电阻材质(60)作为电阻(100)的积体,且该电阻(100)系于其顶部表面具有一第一接触,并且具有一第二接触连接至该埋藏平板(30)。
2.根据权利要求1所述的方法,其中:
该至少一电阻(100)系包括一至少两电阻(100)的电阻组;以及
更进一步包括下列步骤:
植入一具有该第一极性型态导电材质的水平层(20),且延伸该至少两电阻(100)的埋藏平板(30)接触,藉此,该第二接触共同接触该至少两电阻(100)的电阻组。
3.根据权利要求2所述的方法,其中:
该依该电阻材质(60)选择性地移除该已掺杂锗层(55)的步骤,系分别地执行于该电阻组的一第一以及一第二次组之上,藉此,于该第一次组中的该已掺杂锗层(55)的一底部部分,会有与该第二次组的该已掺杂锗层(55)的一底部部分不同的一铅直延伸,并因此,该第一次组的每一构件具有与该第二次组的构件不同的一电阻值。
4.一种于一半导体基板(10)中同时形成一铅直的电阻(100)组以及一铅直的电容器组的方法,其包括下列步骤:
准备该基板(10);
于该基板(10)中蚀刻一沟渠组,该沟渠组包括一电阻次组,以形成该电阻(100)组,以及一电容器次组,以形成该电容器组(30、57、62);
于该沟渠组下部的外侧形成一埋藏导电平板(30);
于该电容器次组内壁以及底部形成一氧化层;
于该沟渠组内壁以及底部沉积一已掺杂锗层(55);
将电阻材质(60、62)沉积于该沟渠组的范围之内,并与该已掺杂锗层(55)相接触;
依该电阻材质选择性地移除该已掺杂锗层(55),并于该沟渠组中留下该已掺杂锗层(55)的一底部部分,藉此,该电阻材质(60)作为电阻(100)的积体,且该电阻(100)于其顶部表面具有一第一接触,以及一第二接触,其透过该电阻材质(60)以及该埋藏平板间的一欧姆接触而连接至该埋藏平板;
于一真空中加热该基板(10),藉此,于该电容器次组中该底部部分的锗层与该氧化层进行反应,以形成一绝缘维持构件(57);以及
以一介电质(45)填充该移除该已掺杂锗层(55)步骤后所剩下之一空间组(52),藉以形成该电阻(100)组以及该电容器组(30、57、62)。
5.根据权利要求4所述的方法,其更包括下列步骤:
植入一具有该第一极性型态导电材质的水平层(20),且延伸与该电容器次组的至少两构件的埋藏平板(30)接触,藉此,使该第二接触共同接触该电容器次组的该至少两构件。
6.根据权利要求4所述的方法,其更包括下列步骤:
植入具有该第一极性型态导电材质的水平层(20),且延伸与该电阻次组的至少两构件的埋藏平板(30)接触,藉此,使该第二接触共同接触该电阻次组的该至少两构件。
7.根据权利要求4所述的方法,其更包括下列步骤:
所述依该电阻材质(60、62)选择性地移除该已掺杂锗层(55)的步骤,分别地执行于该电阻次组的至少一第一以及一第二构件之上,藉此,于该第一构件中的该已掺杂锗层(55)的一底部部分会具有与该第二构件的该已掺杂锗层(55)的一底部部分不同的一铅直延伸,并因此,使该第一构件与该第二构件具有不同的电阻值。
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US10/016,016 US6528383B1 (en) | 2001-12-12 | 2001-12-12 | Simultaneous formation of deep trench capacitor and resistor |
US10/016,016 | 2001-12-12 |
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EP (1) | EP1468441A1 (zh) |
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US7084483B2 (en) * | 2004-05-25 | 2006-08-01 | International Business Machines Corporation | Trench type buried on-chip precision programmable resistor |
US7560761B2 (en) * | 2006-01-09 | 2009-07-14 | International Business Machines Corporation | Semiconductor structure including trench capacitor and trench resistor |
US8546243B2 (en) | 2011-05-24 | 2013-10-01 | International Business Machines Corporation | Dual contact trench resistor and capacitor in shallow trench isolation (STI) and methods of manufacture |
CN116648772A (zh) * | 2021-12-22 | 2023-08-25 | 华为技术有限公司 | 芯片及其形成方法、电子设备 |
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US5554870A (en) * | 1994-02-04 | 1996-09-10 | Motorola, Inc. | Integrated circuit having both vertical and horizontal devices and process for making the same |
US6093968A (en) * | 1996-06-26 | 2000-07-25 | Micron Technology, Inc. | Germanium alloy contact to a silicon substrate |
US6281068B1 (en) * | 1998-04-30 | 2001-08-28 | International Business Machines Corporation | Method for buried plate formation in deep trench capacitors |
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US5567644A (en) * | 1995-09-14 | 1996-10-22 | Micron Technology, Inc. | Method of making a resistor |
US6417063B1 (en) * | 2000-06-22 | 2002-07-09 | Infineon Technologies Richmond, Lp | Folded deep trench capacitor and method |
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2001
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- 2002-12-12 EP EP02795177A patent/EP1468441A1/en not_active Withdrawn
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US5554870A (en) * | 1994-02-04 | 1996-09-10 | Motorola, Inc. | Integrated circuit having both vertical and horizontal devices and process for making the same |
US6093968A (en) * | 1996-06-26 | 2000-07-25 | Micron Technology, Inc. | Germanium alloy contact to a silicon substrate |
US6281068B1 (en) * | 1998-04-30 | 2001-08-28 | International Business Machines Corporation | Method for buried plate formation in deep trench capacitors |
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US6528383B1 (en) | 2003-03-04 |
WO2003050855A1 (en) | 2003-06-19 |
CN1602540A (zh) | 2005-03-30 |
TWI251292B (en) | 2006-03-11 |
TW200303595A (en) | 2003-09-01 |
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