CN1319880A - Reduction of iverse short channel effect - Google Patents
Reduction of iverse short channel effect Download PDFInfo
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- CN1319880A CN1319880A CN 01112163 CN01112163A CN1319880A CN 1319880 A CN1319880 A CN 1319880A CN 01112163 CN01112163 CN 01112163 CN 01112163 A CN01112163 A CN 01112163A CN 1319880 A CN1319880 A CN 1319880A
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- germanium
- region
- diffusion
- neutral dopant
- dopant
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Abstract
The invention represents a FET capable of reduction of inverse short channel effect, and further represents a method for making the same. The germanium is implanted into the entire semiconductor substrate, whose intensity and amount constitutes peak ion concentration regions under the source and drain electrodes of the FET. The germanium can be injected before the formation of grid and source and drain electrodes to reduce the inverse short channel effect which can be normally observed within the FET. In normal, the inverse short channel effect happened in the FET will not be negative effected by the germanium implanting.
Description
Relate generally to semiconductor device of the present invention relates to the reverse short channel effects that occurs in the semiconductor device particularly.
The trend that reduces its characteristic size in the semiconductor integrated circuit has produced channel length and has approached 0.05 micron device.But, along with reducing of length of effective channel (Leff), the conductance of raceway groove oppositely and gate voltage one thresholding (threshold) voltage one that conduction takes place be increased on the theoretical expection level.Fig. 1 represents this increase of voltage, or reverse short channel effects (RSCE), and this generally is a kind of effect of occurring of not wishing in fact.Dotted line among Fig. 1 is illustrated in desirable channel conductivity energy in the device of being with grid.
Along with reducing of channel length threshold voltage tend to higher this trend on the contrary can be oppositely on a bit at certain, at this moment threshold voltage sharply descends.Threshold voltage this reduces to be called as short-channel effect (SCE) suddenly.Traditionally, along with taking measures to reduce RSCE, then SCE can degenerate, and this is a undesirable secondary effect.
RSCE thinks that generally the edge of source electrode and drain electrode causes owing to threshold energy boron in n type metal oxide semiconductor field-effect transistor (NMOSFET) is deposited in, and also normally the distribution of uneven boron is caused in the channel region of FET because cross in short channel simultaneously.Once used in channel region to replenish and inject P type ion and attempt to prevent RSCE to reduce in the influence of the accumulation of channel region boron.
Another kind of once the use with the technology that reduces the RSCE among the FET is to inject germanium in the source electrode of FET and drain region.The cross section of representing NFET among Fig. 2 at 10 places has generally added the germanium implantation region 22 of shallow-layer therein in the zone of source electrode 18 and drain electrode 20.P type silicon chip 12 contains a grid 14 that is distributed on the gate oxide 15 and between sidewall spacers 16.Source electrode 18 and drain electrode 20 respectively have a shallow-layer germanium implantation region 22, and they are used for preventing RSCE and form.
But, be used for reducing the procedure of processing that the routine techniques of RSCE need add, and can cause unwanted subsidiary effect device performance.Needed in present technique is to make a kind of method that can not be subjected to the semiconductor device of RSCE influence.
The present invention is a kind of semiconductor device, comprise a semiconductor chip, be arranged in said on-chip first diffusion region, be arranged in said on-chip second diffusion region, be arranged in the channel region between said first diffusion region and second diffusion region, be arranged on the said semiconductor chip and on said channel region and with the equitant gate oxide in said first diffusion region and said second diffusion region, be arranged in the gate electrode on the said gate oxide, and being arranged in whole said on-chip neutral dopant diffusion injection region, there is a peak value enrichment region diffuse dopants injection region, said center under said first diffusion region and said second diffusion region.
The process of making said device is included on the semiconductor chip of first conductivity types and forms an oxide layer, cover type inject a kind of neutral dopant to said substrate to form the neutral dopant injection region, on said oxide layer, form gate electrode, inject source electrode and drain region to said substrate, its degree of depth is less than the place that said germanium implantation region reaches peak concentration.
Now will with only as an example mode and the present invention is described with reference to appended illustration, these figure only are exemplary rather than restrictive, and wherein components identical is all pressed identical numeral number in each figure, in these figure,
Fig. 1 is the diagram that shows reverse short channel effects and short-channel effect;
Fig. 2 is the sectional view of FET, shows that germanium conventional in leakage and source electrode injects body;
Fig. 3 is the sectional view that is covered with the wafer of oxide layer when Ge-doped;
Fig. 4 is the sectional view of wafer after doping of Fig. 3;
Fig. 5 is the sectional view of wafer after grid generation and source and drain electrode doping of Fig. 4;
Fig. 6 is the diagram that shows relative concentration of dopant among the embodiment of FET;
Fig. 7 sectional view that to be FET carry out when gate electrode generates on oxide layer when germanium injects;
Fig. 8 shows that its RSCE of FET with germanium implantation region reduces but the diagram that do not have corresponding SCE to degenerate.
Semiconductor device described herein has neutral dopant and injects, germanium for example, and below source and drain region the formation peak concentration.The injection region of germanium was preferably injected before source, leakage and grid generate, and also was possible but inject after source, leakage and grid generate.The device of gained, it can be a FET, can not be subjected to reverse short channel effects, and this injection can not cause the deterioration of short-channel effect.Though what these figure and following explanation disclosed for clarity is the invention of a kind of NFET embodiment, persons skilled in the art will be sure of that the present invention also is same being suitable for for other semiconductor device with grid-control diffusion region.For example, just can form PFET by the reverse of doping polarity to the NFET type.
With reference now to Fig. 3,, a NFE1 has the silicon area 12 of P type, utilizes the conventional method deposition or the oxide layer 23 of having grown thereon.P type silicon area 12 can be the monocrystal wafer that mixes, and for example is used in the wafer that NFET uses, or also can is the trap that is injected formed P type silicon by the ion of n type silicon, for example will be used in the NFET part in the CMOS application.Oxide layer 23 generally is to use from about 0.04 to about 0.06 micron original depth to form, and preferred thickness is about 0.05 micron.P type silicon area 12 can be doped to initial concentration about 1 * 10 with the such P type dopant of for example boron
17To 2 * 10
18Individual atom/centimetre
3, preferably about 3 * 10
17Atom/centimetre
3
The injection region of neutral dopant is preferably injected so that in the following peak value neutral dopant concentration of wafer formation in source and bottom, drain diffusion injection region having under enough energy, above said diffusion injection region be to inject in afterwards the step.Though any neutral dopant for example silicon or germanium can be used, germanium is preferred neutral dopant.In one embodiment, injected germanium so that be about 0.10 to about 0.50 micron in the degree of depth and located to form a peak value, the wherein preferred degree of depth is about 0.15 to about 0.30 micron, and the especially desirable degree of depth is about 0.20 to about 0.25 micron.The last peak concentration of germanium is about 10
19Cm
-3To about 10
21Cm
-3Be desirable, especially desirable concentration is about 10
20Germanium concentration on P type silicon area 12 surfaces is preferably about 10
17Cm
-3To about 10
19Cm
-3, especially desirable concentration is about 10
18Cm
-3Germanium concentration can change between the peak concentration on the surface of P type silicon area 12 in any way, but the preferably variation of logarithmic (for example seeing Fig. 6).In order to form the injection region of germanium with the correct degree of depth and concentration, germanium ion can be used, for example from about 230 to 270 kiloelectron-volts (keV) about 10
13Cm
-2To about 10
16Cm
-2Inject, preferably about 245 to 255 kiloelectron-volts about 10
14Cm
-2To about 10
15Cm
-2Inject.
Fig. 4 is illustrated in the cross section that injects the later NFET of germanium.The aforesaid distance of distance " X " expression from P type silicon area surface to the germanium implantation region peak concentration.Dotted line 26 expression germanium inject the degree of depth of peak concentration.Germanium concentration all reduces along both direction from peak concentration 26 beginnings.Distance " X " can be the resulting value of suitable germanium concentration any source from NFET, leakage and the channel region, but value described above is preferably arranged.
With reference now to Fig. 5,, shown in here is in grid generation and source and the drain electrode later NFET that mixes.The formation of grid is to realize that with the technology of knowing grid 14 can be the grid of polysilicon.Before generating grid, make last figure on the oxide layer 23 and obtain the gate oxide that thickness is about 4 to 11 nanometers through being etched with.And then form polysilicon layer, form through needle drawing and etching and have thickness and be about 100 polysilicon gates 14 to about 200 nanometers.
In case generated grid 14, just can mix to the diffusion region of source electrode 18 and drain electrode 20.With the impurity of n type ion being carried out in source electrode 18 and drain electrode 20 injects and just can obtain being about 10
19To 10
21Ion concentration, preferred concentration is about 10
20The injection degree of depth in source electrode 18 and drain electrode 20 districts is preferably less than about 0.15 micron, and the especially desirable degree of depth is less than about 0.1 micron.The sidewall spacers 16 that contains oxide or nitride can form on the limit of grid 14 optionally.So that generate the second injection region (not shown) at source electrode 18 and drain electrode 20.
In this stage, the germanium injectant is diffused into source electrode 18, drain electrode 20 and in source electrode 18 and the raceway groove between 20 of draining.Anneal to activate the lattice structure of dopant and recovery silicon chip.Annealing can be carried out between about 1200 degrees centigrade about 600.After annealing, the manufacturing that can finish NFET with the metallization and the passivating technique of routine.
Fig. 6 represents the ion concentration in each zone of NFET.Reach as mentioned above as shown in Figure 6, the peak value of germanium injects the degree of depth and preferably forms deeplyer than the injection degree of depth of source electrode and drain electrode at wafer.Among the said in the above NFET, the injectant of source and drain electrode is the ion of n type, and the wafer ion is a P type ion.Above the concentration and the degree of depth said and that be shown among Fig. 6 be exemplary, person skilled in the art person will appreciate that, other doping content and to inject the degree of depth all be possible and within the scope of the present invention.
Importantly, germanium can inject in any stage in the NFET manufacture process before forming source electrode and drain electrode.For example, germanium can inject before forming oxide layer 23 or after forming gate electrode 14.Fig. 7 represents that the implantation step of germanium has formed the back at grid 14 and realized.Go in order germanium to be injected in the channel region of grid below 14 effectively, germanium ion must inject at a certain angle, as shown in Figure 7, the energy of injection and dosage will be regulated the angle of injecting with compensation.The injection region of germanium also can utilize injection technique shown in Figure 7 to inject after source electrode 18 and drain electrode 20 have formed and before or after sidewall spacers 16 forms.
On P type substrate, carry out cover type and inject and to have stoped the accumulation of boron and the inconsistency of raceway groove, thereby reduced RSCE,, can reduce percent 15 or more at least according to the technology of device.Fig. 8 is a diagram, and it is contrasted to the short channel threshold voltage of the NFET of injection germanium of the present invention and the conventional NFET that does not have germanium to inject.The NFET that band injects germanium is illustrated by the broken lines.Reverse short channel effects has reduced to the desirable level that germanium injects NFET that approaches.But band germanium injects short-channel effect is degenerated.
Above-mentioned NFET has the advantage that reduces reverse short channel effects significantly and other key characteristic of short-channel effect or NFET device is degenerated.Single germanium implantation step can easily the germanium injection be included in standard N FET and the CMOS application is gone.
Though represented to close and narrated preferred embodiment, can carry out various modifications and substitute and do not deviate from the spirit and scope of the present invention to it.Therefore, should be appreciated that the present invention just narrates as a kind of explanation, and explanation that is disclosed and embodiment should not think the restriction to claim here.
Claims (41)
1. improvement in making the method for semiconductor device, this semiconductor device have in grid that forms on the semiconductor chip and the diffusion region that forms in semiconductor chip, and this improvement comprises:
The neutral dopant cover type is injected in the said semiconductor chip, and its energy dose is enough to said neutral dopant is injected into the degree of depth of its degree of depth greater than said diffusion region.
2. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, and said implantation step injects said germanium before being included in and forming said diffusion region.
3. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, and said implantation step injects said germanium before being included in and forming said grid.
4. the method for claim 1, it is characterized in that wherein said neutral dopant is a germanium, said implantation step comprises that this dosage was enough to prevent crossing diffusion at the dopant for the dopant in said each diffusion region between said each diffusion region in the said semiconductor chip in the heating period of said step with such dosage injection germanium.
5. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, and said semiconductor device is FET.
6. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, and said each diffusion region is that the diffusion region is leaked in the source.
7. the method for claim 1 is characterized in that wherein said grid is a polysilicon.
8. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, and said semiconductor chip is a silicon.
9. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, and said germanium is injected in the said semiconductor chip to form from about 0.10 to about 0.50 micron dark peak value enrichment region.
10. the method for claim 9 is characterized in that wherein said germanium is injected in the said semiconductor chip to form from about 0.15 to about 0.30 micron dark peak value enrichment region.
11. the method for claim 10 is characterized in that wherein said germanium is injected in the said semiconductor chip to form from about 0.20 to about 0.25 micron dark peak value enrichment region.
12. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, said germanium is injected into and makes its peak concentration is about 10
19To 10
21Individual germanium ion cm
-3
13. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, said germanium is injected into and makes its peak concentration is about 10
20Individual germanium ion cm
-3
14. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, said injection is carried out later at the said grid of formation.
15. the method for claim 1 is characterized in that wherein said neutral dopant is a germanium, said injection is carried out after forming said diffusion region.
16. the method for claim 1 is characterized in that wherein said neutral dopant is a silicon.
17. a semiconductor device comprises:
A semiconductor chip;
Be arranged in said on-chip first diffusion region;
Be arranged in said on-chip second diffusion region;
Be arranged in the channel region between said first diffusion region and said second diffusion region;
Be arranged on the said semiconductor chip on said channel region and with the overlapping gate oxide in said first diffusion region and said second diffusion region;
Be arranged in the gate electrode on the said gate oxide; And
Be arranged in whole said on-chip neutral dopant diffusion injection region, said neutral dopant diffusion injection region has the peak value enrichment region under said first diffusion region and said second diffusion region.
18. the device of claim 17 it is characterized in that wherein said neutral dopant diffusion injection region is a germanium, and said semiconductor device is FET.
19. the device of claim 17 is characterized in that wherein said neutral dopant diffusion injection region is a germanium, and said first diffusion region and said second diffusion region are source electrode and drain diffusion regions.
20. the device of claim 17 it is characterized in that wherein said neutral dopant diffusion injection region is a germanium, and said grid is a polysilicon.
21. the device of claim 17 it is characterized in that wherein said neutral dopant diffusion injection region is a germanium, and said semiconductor chip is a silicon.
22. the device of claim 17 is characterized in that wherein said neutral dopant diffusion injection region is a germanium, and the peak value enrichment region of said germanium diffusion injection region be from about 0.10 to about 0.50 micron dark.
23. the device of claim 22, the peak value enrichment region that it is characterized in that wherein said germanium diffusion injection region for from about 0.15 to about 0.30 micron dark.
24. the device of claim 23, the peak value enrichment region that it is characterized in that wherein said germanium diffusion injection region for from about 0.20 to about 0.25 micron dark.
25. the device of claim 17 it is characterized in that wherein said neutral dopant diffusion injection region is a germanium, and the peak value enrichment region of said germanium diffusion injection region is about 10
19To about 10
21Individual germanium ion cm
-3
26. the device of claim 25 is characterized in that the peak value enrichment region of wherein said germanium diffusion injection region is about 10
20Individual germanium ion cm
-3
27. the device of claim 17 is characterized in that wherein said neutral dopant diffusion injection region is a germanium, and the thickness of said gate insulator is about 4 to about 11 nanometers.
28. the device of claim 17 is characterized in that wherein said neutral dopant diffusion injection region is a germanium, and the thickness of said grid is about 100 to about 200 nanometers.
29. the device of claim 17 is characterized in that wherein said neutral dopant diffusion injection region is a silicon.
30. make a kind of method of FET, comprising:
On the semiconductor chip of first kind of conductivity-type, form an oxide skin(coating);
Cover type injects the neutral dopant ion to form the neutral dopant injection region in said substrate;
On said oxide skin(coating), form gate electrode; And
Inject source electrode and drain region on said substrate, its degree of depth is less than the degree of depth that the peak value enrichment region appears in said neutral dopant injection region.
31. the method for claim 30, it is characterized in that wherein said neutral dopant ion is a germanium, and said cover type implantation step comprises that with such dosage injection germanium this dosage is enough to preventing spreading excessively at the dopant between said source and said drain region on the said substrate for the dopant in said source electrode and the drain region during the heating period of said process.
32. the method for claim 30 it is characterized in that wherein said neutral dopant ion is a germanium, and said grid is a polysilicon.
33. the method for claim 30 it is characterized in that wherein said neutral dopant ion is a germanium, and said semiconductor chip is a silicon.
34. the method for claim 30 is characterized in that wherein said neutral dopant ion is a germanium, and said germanium be injected in the said semiconductor chip with form said peak value enrichment region for from about 0.10 to about 0.50 micron dark.
35. the method for claim 34 is characterized in that wherein said neutral dopant ion is a germanium, and said germanium be injected in the said semiconductor chip with form said peak value enrichment region for from about 0.15 to about 0.30 micron dark.
36. the method for claim 35, it is characterized in that wherein said germanium be injected in the said semiconductor chip with form said peak value enrichment region for from about 0.20 to about 0.25 micron dark.
37. the method for claim 30 is characterized in that wherein said neutral dopant ion is a germanium, and the Cmax that said germanium injects is about 10
19To about 10
21Individual germanium ion cm
-3
38. the method for claim 37 is characterized in that the peak concentration that wherein said germanium injects is about 10
20Individual germanium ion cm
-3
39. the method for claim 30 is characterized in that wherein said neutral dopant ion is a germanium, and the injection of said cover type is carried out after said grid forms.
40. the method for claim 30 is characterized in that wherein said neutral dopant ion is a germanium, and the injection of said cover type is carried out after said diffusion region forms.
41. the method for claim 30 is characterized in that wherein said neutral dopant ion is a silicon.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000095027A JP4510990B2 (en) | 2000-03-30 | 2000-03-30 | Paint composition and water-based paint, and blending method thereof |
| JP09/539527 | 2000-03-30 |
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| Publication Number | Publication Date |
|---|---|
| CN1319880A true CN1319880A (en) | 2001-10-31 |
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|---|---|---|---|
| CN 01112163 Pending CN1319880A (en) | 2000-03-30 | 2001-03-29 | Reduction of iverse short channel effect |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100414708C (en) * | 2002-11-26 | 2008-08-27 | 斯班逊有限公司 | Method of producing a laterally doped channel |
| CN110911282A (en) * | 2018-09-18 | 2020-03-24 | 无锡华润微电子有限公司 | Method for manufacturing N-channel semiconductor component and N-channel semiconductor component |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006036992A (en) * | 2004-07-29 | 2006-02-09 | Sk Kaken Co Ltd | Water borne coating and coating method |
| JP5288679B2 (en) * | 2005-03-25 | 2013-09-11 | 株式会社カネカ | Contamination resistance imparting composition, coating composition, and coating film obtained from the coating composition |
| JP5288680B2 (en) * | 2005-03-31 | 2013-09-11 | 株式会社カネカ | Water-based coating composition and coating film obtained from the coating composition |
| JP5086530B2 (en) * | 2005-06-27 | 2012-11-28 | エスケー化研株式会社 | Paint composition |
| JP5086548B2 (en) * | 2005-09-02 | 2012-11-28 | エスケー化研株式会社 | Paint composition |
| JP4937556B2 (en) * | 2005-09-08 | 2012-05-23 | エスケー化研株式会社 | Paint composition |
| JP5043555B2 (en) * | 2007-08-08 | 2012-10-10 | 株式会社カネカ | Curable composition |
| JP5215724B2 (en) * | 2008-05-12 | 2013-06-19 | 株式会社カネカ | Resin composition for water-based paint |
| JP5486882B2 (en) * | 2009-09-08 | 2014-05-07 | 株式会社カネカ | Water-based resin composition for paint |
| JP5667849B2 (en) * | 2010-11-19 | 2015-02-12 | 株式会社カネカ | Aqueous resin composition |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61125471A (en) * | 1984-11-20 | 1986-06-13 | Takemoto Oil & Fat Co Ltd | Method for coating aqueous high polymer liquid on hydrophobic solid surface |
| IT1197812B (en) * | 1986-09-16 | 1988-12-06 | Ausimont Spa | COMPOSITION BASED ON FLUORINATED POLYMERS IN WATER DISPERSION, CONTAINING ALCOXYLSILANS, FOR THE COATING OF METAL SURFACES |
| JPH06330026A (en) * | 1993-05-24 | 1994-11-29 | Aisin Seiki Co Ltd | Solution for forming water-repelling coating film |
| JP3437672B2 (en) * | 1995-03-27 | 2003-08-18 | 鐘淵化学工業株式会社 | Resin composition for water-based paint and method for forming coating film excellent in stain resistance |
| JP3423830B2 (en) * | 1996-02-16 | 2003-07-07 | 鐘淵化学工業株式会社 | Resin composition for water-based paint and method for forming coating film excellent in stain resistance |
| JP2001159099A (en) * | 1999-11-29 | 2001-06-12 | Jsr Corp | Wallpaper-coating composition and wallpaper |
-
2000
- 2000-03-30 JP JP2000095027A patent/JP4510990B2/en not_active Expired - Fee Related
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100414708C (en) * | 2002-11-26 | 2008-08-27 | 斯班逊有限公司 | Method of producing a laterally doped channel |
| CN110911282A (en) * | 2018-09-18 | 2020-03-24 | 无锡华润微电子有限公司 | Method for manufacturing N-channel semiconductor component and N-channel semiconductor component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP4510990B2 (en) | 2010-07-28 |
| JP2001279160A (en) | 2001-10-10 |
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