CN1318864A - Polycrystalline modular device - Google Patents

Polycrystalline modular device Download PDF

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Publication number
CN1318864A
CN1318864A CN 00105879 CN00105879A CN1318864A CN 1318864 A CN1318864 A CN 1318864A CN 00105879 CN00105879 CN 00105879 CN 00105879 A CN00105879 A CN 00105879A CN 1318864 A CN1318864 A CN 1318864A
Authority
CN
China
Prior art keywords
insulating substrate
modular device
polycrystalline
double
described polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN 00105879
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Chinese (zh)
Inventor
陈庆丰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BEIJING PULUO QIANGSHENG SEMICONDUCTOR Co Ltd
Original Assignee
BEIJING PULUO QIANGSHENG SEMICONDUCTOR Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BEIJING PULUO QIANGSHENG SEMICONDUCTOR Co Ltd filed Critical BEIJING PULUO QIANGSHENG SEMICONDUCTOR Co Ltd
Priority to CN 00105879 priority Critical patent/CN1318864A/en
Publication of CN1318864A publication Critical patent/CN1318864A/en
Pending legal-status Critical Current

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Abstract

The polycrystalline modular device has several units electrically connected on insulating chip. The main structure includes terminals for partial or all connecting wires, the conducting layer formed in partial surface of insulating chip ends, the directly insertion to package and printed circuit board without socket and soldering connection. The available package is mainly single in-line one and may have double in-line one. The present invention adopts vertical assembly with small package area, and may have different structure and various application circuits.

Description

Polycrystalline modular device
Existing encapsulation category is that single-row straight cutting is encapsulated as the master with " SIP " all, and promptly enclosed chip one side flushes a plurality of terminals and the inner packing forms that electrically connects such as d1~dm of arrangement, and the enclosed chip area that it takies is very huge;
Again, general insulating substrate must utilize a lead frame, is assembled on this enclosed chip, so spent cost is higher during production, the time is longer, does not have very much an economic benefit;
Therefore how providing a kind of polycrystalline modular device that addresses the above problem, is for exciting this case inventor's invention motivation.
In view of this, this case inventor is engaged in the relevant industries many years of experience and constantly ponders over research with it, and the present invention is born, and its primary and foremost purpose is to provide a kind of polycrystalline modular device, has also solved the shortcoming of original technology simultaneously;
The present invention is the device that a plurality of unit electrically connect on insulating substrate, its primary structure is: in this polycrystalline grain module, binding post is adopted in the part or all of wiring of this unit, and form conductive layer at the part surface of this insulating substrate end, and do not need to utilize lead frame and can directly insert in the printed circuit board (PCB) of enclosed chip and enclosed chip, and with the bonding structure of scolding tin, thereby cost of the present invention is declined to a great extent, and weight also alleviates relatively.
Existing encapsulation (Package) is based on " SIP " (SINGLE IN LINE PACKAGE), promptly single-row straight cutting encapsulation; The present invention not only is " SIP ", and the double-sided metal that utilizes this end can realize simply that " DIP " (DOUBLE IN LINE PACKAGE) is dip, it can obtain double number of pins at bonding portion, so the effect that stereo-unit distributes, realizes multiple unit density, reduces the enclosed chip area is promptly reached in invention;
And the present invention utilizes scolding tin to be bonded to the two sides of the enclosed chip of multiple wiring, makes the present invention reach the effect of reduced volume;
In addition, the present invention is vertical assembling, and its area that takies the encapsulation substrate reduces to below 1/10, is very beneficial for the miniaturization of this encapsulation substrate;
As mentioned above,, make the present invention be easy to construct multiple structure, and can construct the wider application circuit of scope simply fast from the simplification of basic structure again.
For conveniently understanding content of the present invention and the effect that can reach, now cooperating the graphic instantiation of enumerating, be described in detail as follows:
1, insulating substrate
2, enclosed chip
3, resin
4, scolding tin
5, binding post
6, crystal grain
7, terminals
8, printed wire
B, C, D, E.. unit
A, separator
B, base stage
C, the employed epitaxial loayer of collector region
D, buried regions
E, dark collector electrode doped layer
F, emitter-base bandgap grading
A, multiple distribution substrate illustrate first figure it (A) and are single-row straight cutting encapsulation schematic diagram.First figure it (B) is a schematic diagram of the present invention.First figure it (A-1) is the vertical profile floor map of first figure (A).First figure it (B-1) is the vertical profile floor map of first figure (B).Second figure is a binding post electrode unit schematic diagram.The 3rd figure it (A) is that the present invention and other unit are assemblied in the floor map on the enclosed chip simultaneously.The side cutaway view that the 3rd figure it (B) is the 3rd figure (A).The insulating substrate that the 4th figure it (A) is the two sides device element amplifies example.The 4th figure it (B) is the example that the part of it (A) insulating substrate of the 4th figure engages one another with enclosed chip.The whole printed wire schematic diagrames of single face that the 5th figure it (A) is an insulating substrate.The single face that the 5th figure it (B) is an insulating substrate is the printed wire schematic diagram partly.The 6th figure it (A) is general crystal grain profile.The 6th figure it (B) bonds to insulation substrate partial schematic diagram for crystal grain with scolding tin.The 6th figure it (C) bonds to multiple distribution substrate schematic diagram for crystal grain with scolding tin.
See also shown in first figure, wherein first figure (A) can be called " SIP " (SINGLE IN LINE PACKAGE), and promptly single-row straight cutting encapsulates, and flushes the d1~d of arrangement for one of enclosed chip side mEtc. a plurality of terminals and the inner packing forms that electrically connects; It is dip that first figure (B) can be described as " DIP " (DOUBLE IN LINE PACKAGE), for enclosed chip 2 by the terminal e1~e that electrically connects m, see through mechanical separation and form pectination, and this terminal surfaces and inside can have independently and electrically connects;
Figure one (A) is compared with (B), and (B) manys the terminals of twice than (A) from the above; With in the present invention,, can effectively dwindle the area of this enclosed chip because of vertically being assemblied on the enclosed chip;
In addition, figure one (A-1) is compared with (B-1): unit C (A-1) electrically connects terminal d1~d mJoint is the single face structure, so it also is the single face structure; And (B-1) see through insulating substrate 1 printing electrode or adopt multiple printed circuit board (PCB), its terminal e1~e for two-sided design mCan draw from this insulating substrate 1 two sides, and unit C (B-1) also can construct on this insulating substrate 1 two sides, promptly reach stereo-unit and distribute, realize multiple unit density, reduce the effect of enclosed chip area.
See also shown in second figure, wherein protrusion is binding post 5 electrode units, and d1~d mBe to be the electrode of individual layer, bilayer or alloys such as scolding tin with gold, silver, copper.
See also shown in the 3rd figure (A), wherein B, C, D, E respectively are the configuration of cells example of assembling on the enclosed chip 2, wherein the 3rd figure (B) is the side cutaway view of the 3rd figure (A), and as application examples of the present invention, the E that sees through A figure, B figure makes comparisons, but intuition finds that the area of its shared enclosed chip 1 significantly reduces.
See also shown in the 4th figure (A) this unit b1~b m, unit d1~d mFor binding post 5 structure is arranged, and be assemblied in the both sides of insulating substrate 1, wherein with this unit b1~b m, unit d1-d m Binding post 5 and 1 of insulating substrate fill the good resin 3 of heat conduction, can make this unit reach the heat radiation favorable effects; Unit c1~c again mFor no binding post structure and with this unit b1~b m, unit d1~d mBe assemblied in the both sides of insulating substrate 1 equally;
See also shown in the 4th figure (B), wherein insulating substrate 1 two sides divides other absolute electrode to utilize scolding tin 4 to bond to this enclosed chip 2, even double-sided electrode also needn't all adopt absolute electrode certainly.
See also shown in the 5th figure (A), in the distribution part of insulating substrate 1, wherein this single face is all or part of has done printed wire 8, and has reached extra fin effect; See also shown in the 5th figure (B), in actual use, the thickness of general printing path 8 has only half, and can not make specific fin, during if not specific use, certainly is suitable for.
See also shown in the 6th figure, wherein shown in the 6th figure (A), wherein a represents that isolation, b are that base stage, c are that the employed epitaxial loayer of collector region, d are that buried regions, e are that dark collector electrode doped layer, f are emitter-base bandgap grading, g1~g mBe binding post 5;
See also shown in the 6th figure (B), it is the 6th figure (A) crystal grain 6 binding post 5g1~g mUtilize scolding tin 4 to be bonded to partial enlarged drawing on the insulating substrate 1;
Again, see also shown in the 6th figure (C), it is the crystal grain 6 shown in the 6th figure (A), utilizes scolding tin 4 to be bonded to the two sides of the multiple distribution substrate A of enclosed chip, makes the present invention reach the effect of reduced volume.For progressive of the present invention and practicality are described, now advantage is listed below:
1, insulating substrate can not need lead frame directly to be assembled on the enclosed chip, so cost is declined to a great extent and weight saving.
2, insulating substrate can vertically be assemblied on the enclosed chip, so the enclosed chip area is significantly reduced.
3, can make the present invention reach the effect of reduced volume in the multiple wiring in insulating substrate two sides.
4, see through in the insulating substrate, partly or all cover metal level, make the present invention reach simple and convenient and effective heat radiation.
5, see through insulating substrate and be printing electrode of two-sided design or adopt multiple printed circuit board (PCB), promptly reach the effect that stereo-unit distributes, realizes multiple unit density, reduces the enclosed chip area.
6, owing to need not bond technology, so make the present invention be easy to a large amount of productions, produce and shorten the same period.
7, tool industrial utilization.
8, tool practicality.
The above only is the present invention's preferred embodiments, utilizes the present invention such as.The variation that technology and method are done all should be contained in the invention interest field.

Claims (10)

1, the present invention provides a kind of polycrystalline modular device, is the device that a plurality of unit electrically connect on insulating substrate; It is characterized in that:
Its pin adopt international standards and construct on insulating substrate the unit all or partly electrode form and draw binding post, and for electrically connecting between this insulating substrate and enclosed chip the end is processed, make it can be directly used in the structure of enclosed chip at this insulating substrate end single or double formation pin metal level and in conjunction with above-mentioned pin;
2, the described polycrystalline modular device of claim 1, but this insulating substrate layer multiple stratification wherein;
3, the described polycrystalline modular device of claim 1 wherein electrically connects the adding insulating barrier on this insulating substrate, can carry out multiple wiring;
4, the described polycrystalline modular device of claim 1, wherein this insulating substrate can connect by single or double with the metal level that electrically connects of enclosed chip;
5, the described double-sided metallic of claim 4, it can be used as two pins and uses by two insulation;
6, the described double-sided metallic of claim 4, its comprehensively single or double use;
7, the described polycrystalline modular device of claim 1, certain one side of this insulating substrate wherein, as using as electric wiring with its reverse side, the thickness of its conducting metal is difference partly or entirely;
8, the described polycrystalline modular device of claim 1, wherein space (space) between the insulating substrate of this binding post electrode and cell surface considers heat conducting factor, can carry out suitable insulant and fill;
9, the described polycrystalline modular device of claim 1, wherein the single face of this insulating substrate can partly or entirely be used as the density cooling application;
10, the described polycrystalline modular device of claim 1, wherein this insulating substrate can be at surface mounted component.
CN 00105879 2000-04-18 2000-04-18 Polycrystalline modular device Pending CN1318864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 00105879 CN1318864A (en) 2000-04-18 2000-04-18 Polycrystalline modular device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 00105879 CN1318864A (en) 2000-04-18 2000-04-18 Polycrystalline modular device

Publications (1)

Publication Number Publication Date
CN1318864A true CN1318864A (en) 2001-10-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN 00105879 Pending CN1318864A (en) 2000-04-18 2000-04-18 Polycrystalline modular device

Country Status (1)

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CN (1) CN1318864A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103123903A (en) * 2012-10-25 2013-05-29 南通康比电子有限公司 Bridge rectifier DIP (Double In-line Package) brush coating process
US11629257B2 (en) 2016-07-26 2023-04-18 Ppg Industries Ohio, Inc. Particles having surfaces functionalized with 1,1-di-activated vinyl compounds
US11634524B2 (en) 2016-07-26 2023-04-25 Ppg Industries Ohio, Inc. Acid-catalyzed curable coating compositions containing 1,1 di-activated vinyl compounds and related coatings and processes

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103123903A (en) * 2012-10-25 2013-05-29 南通康比电子有限公司 Bridge rectifier DIP (Double In-line Package) brush coating process
US11629257B2 (en) 2016-07-26 2023-04-18 Ppg Industries Ohio, Inc. Particles having surfaces functionalized with 1,1-di-activated vinyl compounds
US11634524B2 (en) 2016-07-26 2023-04-25 Ppg Industries Ohio, Inc. Acid-catalyzed curable coating compositions containing 1,1 di-activated vinyl compounds and related coatings and processes

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C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C06 Publication
PB01 Publication
ASS Succession or assignment of patent right

Owner name: NINGBO PULUOQIANGSHENG SEMICONDUCTOR CO., LTD.

Free format text: FORMER OWNER: NONE

Effective date: 20021219

Owner name: SHAOXING KEQIANG SEMICONDUCTOR CO., LTD.

Free format text: FORMER OWNER: BEIJING KEQIANG SEMICONDUCTOR CO.,LTD.

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20021219

Address after: 312000 Wang Jieyue, 158 East painted Hill Road, Shaoxing Economic Development Zone, Zhejiang

Address after: 315040, Hong Zhu, No. 57, Nanjing Road, Jiangdong District, Zhejiang, Ningbo

Applicant after: Shaoxing strong Semiconductor Co., Ltd.

Co-applicant after: Ningbo proletarian Johnson Semiconductor Co., Ltd.

Address before: 100029, Beijing, Chaoyang District outside the stability of the door outside the Ancient Village No. 2 C seat

Applicant before: Beijing strong Semiconductor Co., Ltd.

C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication