CN1317832A - Dual-heterojunction CaAsSb/Inp transistor and its preparing process - Google Patents
Dual-heterojunction CaAsSb/Inp transistor and its preparing process Download PDFInfo
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- CN1317832A CN1317832A CN 01115034 CN01115034A CN1317832A CN 1317832 A CN1317832 A CN 1317832A CN 01115034 CN01115034 CN 01115034 CN 01115034 A CN01115034 A CN 01115034A CN 1317832 A CN1317832 A CN 1317832A
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Abstract
A dual-heterojuction CaAsSb/InP transistor is composed of collector, base and emitter. Its substrate is semi-insulating Inp monocrystal. Said collector consists of N-InGaAs on substrate and low-doped N-InP. Said base is P-GaAsSb. Said emitter is composed of N-InP or AIInAs and N-InGaAs ohm contact layer. Its advantages are good repeatability and excellent performance. It can be used for microwave and light communications.
Description
The present invention relates to a kind of GaAsSb/InP double heterojunction transistor structure, and adopt metal organic chemical vapor deposition technology (MOVCD) to prepare the method for carbon doped p-type base GaAsSb/InP high performance microwave transistor material.
Metal organic chemical vapor deposition (Metal Organic Chemical Vapor Deposition-MOCVD) is the advanced technology of preparing that nearest three more than ten years progressively develops the semiconductor epitaxial material that improves, compare with traditional VPE and LPE technology, it can accurately control thickness, the component of epitaxial loayer, can be used to grow ultra-thin layer dissimilar materials, as quantum well, superlattice etc., become one of important technology of preparing of semiconductor epitaxial material." energy band engineering " of based semiconductor theory, " wave function engineering ", " lattice engineering " etc. are laid a good foundation for the high performance semiconductor device structure of design.InP compares with Si with GaAs, has high electron saturation velocities, is the ideal material of preparation high speed transistor.Based on the heterojunction transistor (Heterojunction Bipolar Transistor-HBT) of InP substrate is fastest transistor at present, simultaneously it also with the substrate compatibility of present optic communication device, it is integrated to be easy to photoelectric device.Famous TRW, the RFMD company of the U.S. planned it is applied to communication system of future generation, carries out large-scale production.According to transistorized operation principle, its device architecture can be designed by energy band engineering.Early eighties has proposed the AlGaAs/GaAs HBT based on the GaAs substrate, utilize energy band engineering that the relation of being with between emitter region and the base is optimized, InGaP/GaAs, GeSi/Si heterojunction transistor have appearred, the former device material growth and prepared process have reached 6 inches production in enormous quantities stages on the substrate, have been used for present mobile phone communication system.Along with the requirement more and more higher to communication speed, high speed HBT has become the focus of present development.For this reason, except the characteristics of giving full play to material itself, utilize energy band engineering that the entire device structure (emitter region-base-collector region) of HBT is carried out overall system design and necessitate.HBT based on the InP substrate generally adopts InP/InGaAs/InP to be respectively emitter region, base and collector region device architecture at present.Analyze as can be known from the angle of energy band engineering, though this device architecture has been optimized emitter junction, its collector junction existing problems.Electronics needs tunnelling to pass through InGaAs/InP heterojunction boundary potential barrier when the base is transmitted into collector region, and device performance is affected.
GaAsSb/InP's can be with being II type heterostructure: the conduction band of GaAsSb is positioned at 180 meV on the InP conduction band, its valence band is lower than InP valence band 736 meV, there are not electronic barrier in GaAsSb base and InP collector region interface, the electronics that transmits by the base with diffusion motion has higher energy at the InP collector region, launch (ballistically) in the trajectory mode, high-speed transfer is to collector electrode.The valence band energy difference of 736 meV is arranged between InP emitter region and the GaAsSb base simultaneously, and so high potential barrier forms effective restriction to the hole of base, can stop hole diffusion, tunnelling to enter the emitter region, reduces base-emitter region recombination current.Therefore GaAsSb/InP is the ideal material system that is used for making HBT, foretells that in theory InP/GaAsSb/InPHBT has the excellent microwave performance.Be collector region owing to having adopted InP simultaneously, the puncture voltage of HBT also improves greatly.
The objective of the invention is to overcome the shortcoming of prior art, a kind of high performance GaAsSb/InP double heterojunction transistor and preparation method thereof is provided.
The objective of the invention is to be achieved through the following technical solutions:
The structure of GaAsSb/InP double heterojunction transistor of the present invention is made up of following three parts: collector region, base and emitter region, as shown in Figure 1.Substrate adopts semi-insulated InP (indium phosphide) single-chip, and collector region is by the N that is grown on the substrate
+-InGaAs and low-doped N
--InP forms, and the base is by P
+-GaAsSb forms, and the emitter region is by N
--InP or AlInAs and N
+-InGaAs ohmic contact layer is formed.
Above-mentioned ohmic contact layer is In
0.53Ga
0.47As is doped to the n type, and dopant is Si or S, concentration 1～3 * 10
19Cm
-3, thickness is 200nm.Fig. 2 illustrates the relation of several frequently seen semi-conductive energy gap and lattice constant, as seen, when Sb=0.5, GaAsSb and InP lattice match, when the content of In near 0.53 the time, InAlAs and InGaAs and InP substrate lattice coupling.
InP makes collector region, and thickness is 100～500nm, and doping content is 1～5 * 10
16Cm
-3The base is GaAs
0.5Sb
0.5, being doped to the p type, dopant is C, doping content 3～5 * 10
19Cm
-3, thickness is 10～49nm; The emitter region is by InP or AlInAs, and thickness is 50～100nm, and doping content is 1～5 * 10
17Cm
-3, dopant is Si or S.
The preparation method of GaAsSb/InP double heterojunction transistor of the present invention is as follows:
The preparation of GaAsSb/InP double heterojunction transistor mainly is the preparation of material.Organometallic Chemistry vapour phase epitaxy (MOVCD) method is adopted in the preparation of material, and the required source material of epitaxial growth is trimethyl aluminium (TMAl), trimethyl indium (TMIn), triethyl-gallium (TEGa), tert-butyl group arsenic (TBAs) or AsH
3, phosphine (PH
3) or tert-butyl group phosphorus (TBP) and trimethylantimony (TMSb) or antimony triethyl (TESb), n type doped source is two silane (Si
2H
6) or H
2S; The growth temperature of material is 500～650 ℃, and growth pressure is 50～150Torr, and the speed of growth is 1 μ m/h, and GaAsSb is the core of transistor material.
Transistor base GaAs
0.5Sb
0.5In the preparation of material, as the carbon of p-type dopant from CCl
4Or CBr
4
In the above-mentioned transistor preparation methods, inserting a thin layer at the p-n junction interface is intermediate layer, with the difficulty that solves the material growth.
In the above-mentioned transistor preparation methods, gas conversion from InP to GaAsSb, the InGaAs that inserts 2～10 atomic monolayers in the middle of InP and GaAsSb is an intermediate layer, after the InP growth is finished, close one second of In, In, Ga, As three enter reative cell simultaneously subsequently, close In, Ga source again, use H
2Purged one second; Then Sb, Ga source enter, the growth of beginning GaAsSb.
In the above-mentioned transistor preparation methods, the interface conversion of the heterojunction system from GaAsSb to InP, adopting the InGaAs of 2～10 atomic monolayers is intermediate layer, after GaAsSb growth is finished, turn off one second of Ga source, turn off one second of Sb source subsequently, with bradyauxesis InGaAs to 2～10 atomic monolayer, turn off the As source, feed the P source, finish the interfacial gases conversion to InP by GaAsSb.
In the above-mentioned transistor preparation methods, interfacial gases conversion from GaAsSb to AlInAs, adopting the InGaAs of 2～10 atomic monolayers is intermediate layer, after GaAsSb growth is finished, turn off one second of Ga source, turn off one second of Sb source subsequently, with bradyauxesis InGaAs to 2～10 atomic monolayer, turn off the As source, feed the P source, finish the interfacial gases conversion to InP by GaAsSb.After lnGaAs middle transition layer growth was finished, AlInAs then grew.
The high-quality GaAsSb/InP HBT of the present invention's preparation has low cut-in voltage, its device can be worked under small voltage, thereby reduce the power consumption of circuit, if this device is used for present mobile communication circuit, then under the situation that does not change battery performance, the continuous type time of mobile phone will be multiplied, and by charging in present two, three days once, be expected to bring up to one, biweekly.Therefore the HBT that uses material system of the present invention to make is that most promising next-generation mobile phone is suitable for one of device.
Below in conjunction with description of drawings and embodiment the present invention is further elaborated.
Fig. 1 is the structure chart of heterojunction transistor, and wherein (a) is the structural representation of transistor, (b) the concrete structure figure of heterojunction transistor.
Fig. 2 is the relation of common semi-conductive energy gap and lattice constant.Wherein, abscissa is a lattice constant, and ordinate is the energy gap width.As seen from the figure, when Sb=0.5, GaAsSb and InP lattice match are when the content of In AlInAs and InGaAs and InP substrate lattice coupling near 0.53 time.
The high-resolution X-ray diffraction curve of Fig. 3 GaAsSb layer.Wherein, abscissa is the angle of diffraction, and ordinate is an intensity.The curve solid line is a measurement result among the figure, and dotted line is an analog result.Measurement result and analog result are consistent, and the illustrative material quality is very good.
Fig. 4 GaAs
0.5Sb
0.5The luminescence generated by light spectrogram.Wherein, abscissa is a photon energy, and ordinate is an intensity.
The growth rate of Fig. 5 GaAsSb, Sb content, hole concentration and CCl
4The relation of flow, wherein abscissa is the flow of carbon tetrachloride gas, ordinate: last figure is a growth rate, and middle figure is the content of Sb in the solid film, and figure below is a carrier concentration.
The relation of hole mobility, resistivity and free hole concentration among Fig. 6 GaAsSb.Wherein, abscissa is a free hole concentration, and ordinate is: the left side is an average resistivity, carrier mobility when the right is 300 ° of K.
Embodiment 1.InP/GaAs
0.5Sb
0.5/ InP double heterojunction transistor (DHBT)
InP is the InP/GaAs of emitter and collector
0.5Sb
0.5/ InP double heterojunction transistor (DHBT) comprises that doping content is 2 * 10
16Cm
-3Thickness is the InP collector electrode of 300nm, and doping content is 4 * 10
19Cm
-3Thickness is the GaAs of 40nm
0.5Sb
0.5Base stage, doping content are 3 * 10
17Cm
-3Thickness is the InP emitter of 1500nm, and contains 50nm InP layer (3 * 10
19Cm
-3) and 300nm InGaAs layer (3 * 10
19Cm
-3) emitter junction.For 5 * 12 μ m
2DHBT, the current factor of emitter and base stage is respectively 1.00 and 1.05, this explanation emitter/base and collector electrode/base stage heterojunction have very high quality.J
C=1A/cm
2Switching voltage be V
BE=0.4V, the collector current cut-in voltage is reduced to V
CE.OFF=0.015eV.This has InP/GaAs
0.5Sb
0.5The current gain of the double heterojunction transistor (DHBT) of/InP structure surpasses 50, and puncture voltage is greater than BV
CEO=6-8V, current gain cutoff frequencies f
TSurpass 75GHz.
Epitaxial loayer is at H
2Flow is to grow in 6 liters/minute the horizontal reative cell.The source material that uses is trimethyl aluminium (TMAl), trimethyl indium (TMIn), triethyl-gallium (TEGa), tert-butyl group arsenic (TBAs), tert-butyl group phosphorus (TBP) and trimethylantimony (TMSb), and doped source is Si
2H
6, CCl
4Growth temperature is 600 ℃, and growth pressure is 100Torr, and the speed of growth of InP is 1 μ m/h, undoped GaAs
0.5Sb
0.5The speed of growth be 1.3 μ m/h.Substrate is InP's (100) crystal face, for ease of the gas circuit conversion, inserts the InGaAs boundary layer of a thickness less than 10nm.V/III ratio is 2, for the undoped GaAsSb of InP lattice match, the distribution coefficient of Sb is 0.9.This helps GaAs
1-xSb
xIn Composition Control.Along with the ratio increase of V/III, distribution coefficient reduces.
Under above-mentioned growth conditions, on the InP substrate, obtained the GaAs of mirror-like
0.5Sb
0.5, thickness is the GaAs of 70nm
0.5Sb
0.5The roughness root mean square on surface is 5nm, but the surface obviously forms texture.After the InP above the GaAsSb grew into 100nm, surperficial texture disappeared and can be observed atomic steps.Fig. 3 does not detect the sign that is separated for the thickness that InP goes up growth is high-resolution X-ray diffraction (XRD) curve of GaAsSb (004) crystal face of 70nm.The peak width of XRD is consistent with the result who obtains by the X-ray diffraction theory.This explanation has obtained high-quality GaAsSb.By the Fourier interferometer characteristics of luminescence under the low temperature is measured, obtained the GaAs that InP goes up growth
0.5Sb
0.5Halfwidth be 7.7meV, as shown in Figure 4.This result is consistent with the optimum that molecular beam epitaxial growth obtains, and is present best result.
Fig. 5 is growth rate, Sb content, hole concentration and the CCl of GaAsSb
4The relation of flow.Be lower than 8 * 10 in hole concentration
19Cm
-3The time, hole concentration and CCl
4Flow is linear.CCl
4Influence to the speed of growth increases the weight of with its flow increase, and the speed of growth of heavily doped layer is reduced to half of non-impurity-doped layer.When hole concentration 8 * 10
19Cm
-3During the left and right sides, As is a large amount of enrichments in the GaAsSb layer.Carried out the hole concentration of Hall effect measures by Van der Paul standard sample.Undoped GaAs
0.5Sb
0.5Layer is the p type, and its hole concentration is 5 * 10
16Cm
-3Along with CCl
4Deposition, hole mobility reduces, and surpasses 1 * 10 when mixing
19Cm
-3The time, this value is reduced to 30cm
2/ Vs, as shown in Figure 6.
Embodiment 2.InP/GaAs
0.5Sb
0.5/ InP double heterojunction transistor (DHBT), as described in embodiment 1, different is that the employed source material of MOCVD epitaxial growth is trimethyl aluminium (TMAl), trimethyl indium (TMIn), triethyl-gallium (TEGa), AsH
3, PH
3And antimony triethyl (TESb), n type doped source is H
2S, P type doped source is CBr
4Growth temperature is 620 ℃, and growth pressure is 110Torr.
Claims (8)
1. a GaAsSb/InP double heterojunction transistor is made up of emitter region, base and collector region, and substrate adopts semi-insulated indium phosphide single crystal wafer, it is characterized in that, collector region is by the N that is grown on the substrate
+-InGaAs and low-doped N
--InP forms, and the base is by P
+-GaAsSb forms, and the emitter region is by N
--InP or AlInAs and N
+-InGaAs ohmic contact layer is formed.
2. GaAsSb/InP double heterojunction transistor as claimed in claim 1 is characterized in that ohmic contact layer is In
0.53Ga
0.47As is doped to the n type, and dopant is Si or S, concentration 1-3 * 10
19Cm
-3, thickness is 200nm.
3. GaAsSb/InP double heterojunction transistor as claimed in claim 1 is characterized in that InP makes collector region, and thickness is 100～500nm, and doping content is 1～5 * 10
16m
-3The base is GaAs
0.5Sb
0.5, being doped to the p type, dopant is C, doping content 3-5 * 10
19Cm
-3, thickness is 10～49nm; The emitter region is made up of InP or AlInAs, and thickness is 50～100nm, and doping content is 1～5 * 10
17Cm
-3, dopant is Si or S.
4. the preparation method of the described GaAsSb/InP double heterojunction of claim 1 transistor, it is characterized in that, each distinguishes material is to adopt the preparation of Organometallic Chemistry vapour phase epitaxy (MOVCD) method, the required source material of epitaxial growth is trimethyl aluminium (TMAl), trimethyl indium (TMIn), triethyl-gallium (TEGa), tert-butyl group arsenic (TBAs) or AsH
3, phosphine (PH
3) or tert-butyl group phosphorus (TBP) and trimethylantimony (TMSb) or antimony triethyl (TESb), n type doped source is two silane (Si
2H
6) or H
2S, base GaAsSb material p-type dopant is a carbon, comes from CCl
4Or CBr
4Doped source, the growth temperature of material are 500-650 ℃, and growth pressure is 20-200Torr, and the speed of growth is 1 μ m/h.
5. the preparation method of GaAsSb/InP double heterojunction transistor as claimed in claim 4 is characterized in that, inserts a thin layer at the p-n junction interface.
6. the preparation method of GaAsSb/InP double heterojunction transistor as claimed in claim 4, it is characterized in that, gas conversion from InP to GaAsSb, the InGaAs that inserts 2-10 atomic monolayer in the middle of InP and GaAsSb is an intermediate layer, after the InP growth is finished, close one second of In, In, Ga, As three enter reative cell simultaneously, close In, Ga source subsequently, use H
2Purged one second; Then Sb, Ga source enter, the growth of beginning GaAsSb.
7. the preparation method of GaAsSb/InP double heterojunction transistor as claimed in claim 4, it is characterized in that, the interface conversion of the heterojunction system from GaAsSb to InP, adopting the InGaAs of 2-10 atomic monolayer is intermediate layer, after the GaAsSb growth is finished, turn off one second of Ga source, turn off one second of Sb source subsequently,, turn off the As source with bradyauxesis InGaAs to 2-10 atomic monolayer, feed the P source, finish the interfacial gases conversion to InP by GaAsSb.
8. the preparation method of GaAsSb/InP double heterojunction transistor as claimed in claim 4, it is characterized in that, interfacial gases conversion from GaAsSb to AlInAs, adopting the InGaAs of 2～10 atomic monolayers is intermediate layer, after the GaAsSb growth is finished, turn off one second of Ga source, turn off one second of Sb source subsequently,, turn off the As source with bradyauxesis InGaAs to 2～10 atomic monolayer, feed the P source, finish the interfacial gases conversion to InP by GaAsSb.After InGaAs middle transition layer growth was finished, AlInAs then grew.
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|---|---|---|---|
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|---|---|---|---|
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| CN1170322C CN1170322C (en) | 2004-10-06 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552284B (en) * | 2008-04-02 | 2010-08-25 | 中国科学院微电子研究所 | npn type InGaAs/InP DHBT epitaxial layer structure |
| CN101989838B (en) * | 2009-08-05 | 2012-06-27 | 中国科学院微电子研究所 | Stable network structure of InP DHBT W band power amplifier monolithic integrated circuit |
| CN102646703A (en) * | 2012-05-07 | 2012-08-22 | 中国电子科技集团公司第五十五研究所 | Epitaxial structure of single crystal indium phosphide (InP) group compound semiconductor film |
| CN106952951A (en) * | 2017-03-17 | 2017-07-14 | 中国科学院微电子研究所 | Method for manufacturing InP-based heterojunction bipolar transistor |
-
2001
- 2001-06-06 CN CNB011150343A patent/CN1170322C/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552284B (en) * | 2008-04-02 | 2010-08-25 | 中国科学院微电子研究所 | npn type InGaAs/InP DHBT epitaxial layer structure |
| CN101989838B (en) * | 2009-08-05 | 2012-06-27 | 中国科学院微电子研究所 | Stable network structure of InP DHBT W band power amplifier monolithic integrated circuit |
| CN102646703A (en) * | 2012-05-07 | 2012-08-22 | 中国电子科技集团公司第五十五研究所 | Epitaxial structure of single crystal indium phosphide (InP) group compound semiconductor film |
| CN102646703B (en) * | 2012-05-07 | 2014-12-10 | 中国电子科技集团公司第五十五研究所 | Epitaxial structure of single crystal indium phosphide (InP) group compound semiconductor film |
| CN106952951A (en) * | 2017-03-17 | 2017-07-14 | 中国科学院微电子研究所 | Method for manufacturing InP-based heterojunction bipolar transistor |
| CN106952951B (en) * | 2017-03-17 | 2019-11-15 | 中国科学院微电子研究所 | Method for manufacturing InP-based heterojunction bipolar transistor |
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| Publication number | Publication date |
|---|---|
| CN1170322C (en) | 2004-10-06 |
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