CN1316694A

CN1316694A - Integrated instrument for designing ASIC chip, analoging by combining software with hardware and testing it

Info

Publication number: CN1316694A
Application number: CN 00113352
Authority: CN
Inventors: 陈书明; 卢光兆; 孙永节; 余再祥; 韩龙; 孙绪红; 曾少杰; 胡军; 陈怒兴; 陈海燕; 胡世平; 金杰
Original assignee: National University of Defense Technology
Current assignee: National University of Defense Technology
Priority date: 2000-04-03
Filing date: 2000-04-03
Publication date: 2001-10-10
Anticipated expiration: 2020-04-03
Also published as: CN1128408C

Abstract

An integrated instrument for simulating the design of ASIC chip by cooperation of software and hardware and testing the ASIC chip is disclosed, which is composed of the simulating and testing software and the instrument hardware. Its advantages include high simulating level and ensuring the successful rate of ASIC chips, and integrated both functions.

Description

Asic chip design software and hardware cooperation simulation and the integrated instrument of testing

The present invention relates to the integrated instrument (hereinafter to be referred as mould survey instrument) of ASIC (special IC) chip design carrying out software and hardware cooperation simulation with test.

Along with the raising of asic chip integrated level and the enhancing of function, the simplation verification to ASIC in the design process of ASIC is had higher requirement.Because have only the success ratio that could guarantee its throwing sheet to it through sufficient simplation verification.Software simulator (for example, the Verilog of the U.S.) in the commercial electronic design automation (EDA) at present is the main tool of asic chip being carried out simplation verification.Yet the software simulation tool that utilizes EDA company to provide can run into the trouble that software modeling brings in the ASIC dummy run phase.Because the key of software simulation is to obtain soft model accurately, but not all ASIC can both carry out software modeling easily.For example, high performance microprocessor often because data deficiencies or docking port agreement are understood not exclusively correct or the chip buied and user manual are inconsistent etc., all can cause the very big difficulty of software modeling; And EDA company does not generally provide the soft model of high-performance microprocessor yet.Thereby utilize existing software simulator that simplation verification is carried out in ASIC design significant limitation to be arranged, particularly be difficult to realize the simplation verification of higher level.Because the simulation to the ASIC design is abundant inadequately, the success ratio that also just is difficult to guarantee effectively to throw sheet.

One of purpose of the present invention is to carry out software and hardware cooperation simulation, this method organically is joined together the ASIC that is designing as soft model and die type (as high-performance microprocessor), the code of the soft model (being ASIC) in the simulation and actual die type are moved together, save in the software simulator and will carry out software modeling and many restrictions of bringing corresponding die type.Because other raising of inert stage (as: architecture level, plate level, ASIC level) makes that simulation is more abundant, so that can more effectively guarantee to throw the success ratio of sheet.Two of purpose of the present invention is to utilize this instrument that the ASIC after producing is tested, and this has not only checked the quality of production of ASIC, has also removed the overhead that needs to buy or develop special testing apparatus from, and an instrument is dual-purpose, saves cost.

Technical scheme of the present invention is: mould is surveyed instrument and is made up of software and hardware cooperation simulation and Test Application software (hereinafter to be referred as application software) and mould survey instrument hardware.Application software comprises: simulation application software and Test Application software, and they operate under the unix environment of workstation; Hardware is made up of the parallel bus interface, main frame, adapter three parts that are installed on the workstation.Main frame comprises: master controller MS, clock controller CC, memory controller MC, input pattern memory IPM, output mode memory OPM, input pin electric circuit IPE, output pin electric circuit OPE.Parallel bus interface links to each other with master controller MS by interface cable; MS passes to CC with the clock instruction of application software, makes it produce the work clock of corresponding clock sequence as main frame; MS also passes to IPM with input mode vector IPattern, with the memory operational order of application software (as, memory write, read, burst, address code etc.) pass to MC, make it produce corresponding command sequence IPM or OPM carried out corresponding memory operation.When MC carries out burst operation, read the mode speed of work clock (promptly with) with burst and from IPM, the IPattern vector of reading delivered to continuously that IPE carries out level translation and the I/O direction is handled (for non-difference channel), by stube cable this IPattern vector is acted on the die type that is installed on the adapter or the input pin of ASIC then, its output pin also links to each other with OPE by stube cable.When IPM carried out burst and reads, the mode that OPM then writes with burst will be kept in the sequence address of oneself through the OPattern vector that OPE carries out after the level translation.MS also can will be kept at OPattern among the OPM according to the instruction of application software and read by interface cable and parallel bus interface and give application software.

The die type is melted in the present invention and soft model is an one, integrates simulation and test, and other simplation verification of each grade and the test problem that press for solution for ASIC in designing provide a kind of unified solution.Mould is surveyed instrument and is adopted workstation parallel bus formula centralized control, and compact conformation is simple; But (wherein: pattern memory depth vector can extend to 8M, 16M from 4M for mode memory depth vector, I/O number of pins and the electric flexible configuration of different pins; The I/O number of pins can diffuse into 192 * 8=1536 from 192; At present the die type is supported that the pin of LVCMIS, HSTL is electric, ASIC is supported that the pin of LVCMOS and LVDS is electric); Work clock divides two kinds of external clock and onboard clocks, and the onboard clock frequency adjustable (scope: 150Khz ~ 60Mhz); The clock delay time is adjustable (scope: 0ns ~ 41.3ns); The pumping signal level is adjustable (scope :-1v ~ 6v); Z (high resistant) sample circuit and timing metering circuit are arranged.

If use the present invention to simulated or the frequency of operation of tested ASIC within nominal value range, then be accurately simulation or accurately test; If simulated or the frequency of operation of tested ASIC greater than 60Mhz, then be functional simulation or functional test.

Description of drawings:

Fig. 1 surveys instrument main frame pie graph for mould;

Fig. 2 is the application software process flow diagram;

Among the figure: 1-parallel bus interface 2-interface cable

3-master controller MS 4-clock controller CC

5-storage controller MC 6-input pattern memory IPM

7-input pin electric circuit IPE 8-adapter

9-output pin electric circuit OPE 10-output mode memory OPM

11-main frame 12-stube cable

The invention will be further described below in conjunction with accompanying drawing:

As shown in Figure 1: parallel bus interface 1 links to each other with master controller MS 3 by interface cable 2; Master controller MS 3 passes to clock controller CC 4 with the clock instruction of application software, makes it produce the work clock of corresponding clock sequence as main frame 11; Master controller MS 3 also passes to input mode vector IPattern input pattern memory IPM 6, with the memory operational order of application software (as, memory is write, is read, burst, address code etc.) pass to storage controller MC 5, make it produce corresponding command sequence input pattern memory IPM 6 or output mode memory OPM 10 carried out corresponding memory operation.When storage controller MC 5 carries out burst operation, read the mode speed of work clock (promptly with) with burst and from input pattern memory IPM 6, the IPattern vector of reading delivered to continuously that input pin electric circuit IPE 7 carries out level translation and the I/O direction is handled (for non-difference channel), by stube cable 12 this IPattern vector is acted on the die type that is installed on the adapter 8 or the input pin of ASIC then, its output pin also links to each other with output pin electric circuit OPE 9 by stube cable 12.When input pattern memory IPM 6 carried out burst and reads, the mode that 10 of output mode memory OPM write with burst will be kept in the sequence address of oneself through the OPattern vector that output pin electric circuit OPE 9 carries out after the level translation.Master controller MS 3 also can will be kept at OPattern among the output mode memory OPM10 according to the instruction of application software and read by interface cable 2 and parallel bus interface 1 and give application software.

As shown in Figure 2: select earlier suitable adapter to lay die type (simulation) or measured piece (test), adapter is connected to mould survey instrument main frame after, write the Shell file of adapter, comprise .DEV .PKG .ADP .DLY .TCK etc.; If analog form then calls simulation application software and carries out the preparation of simulated environment, initialization and the analog configuration that mould is surveyed instrument; Start simulation application software and software simulator then and work together, ASIC is carried out software and hardware cooperation simulation, and, analyze for the deviser with waveform display simulation result.If test mode is then called Test Application software and is carried out the preparation of test environment, initialization and the test configurations that mould is surveyed instrument; Start test function then, measured piece is tested, and report test result, analyze for the deviser with the form of file.

Claims

1, a kind of to ASIC---the integrated instrument (be called for short mould and survey instrument) of dedicated IC chip design carrying out software and hardware cooperation simulation and test is characterized in that: mould is surveyed instrument and is made up of software and hardware cooperation simulation and Test Application software and mould survey instrument hardware.

2, mould as claimed in claim 1 is surveyed instrument, it is characterized in that software and hardware cooperation simulation and Test Application software comprise: simulation application software and Test Application software.

3, mould as claimed in claim 1 is surveyed instrument, it is characterized in that hardware is made up of the parallel bus interface (1), main frame (11), adapter (8) three parts that are installed on the workstation.

4, survey instrument as claim 1 or 3 described moulds, it is characterized in that main frame comprises: master controller MS (3), clock controller CC (4), memory controller MC (5), input pattern memory IPM (6), output mode memory OPM (10), input pin electric circuit IPE (7), output pin electric circuit OPE (9).