CN1314202C - Gain circuit and A/D conversion circuit of sharing operational amplifier and application - Google Patents
Gain circuit and A/D conversion circuit of sharing operational amplifier and application Download PDFInfo
- Publication number
- CN1314202C CN1314202C CNB2004100347757A CN200410034775A CN1314202C CN 1314202 C CN1314202 C CN 1314202C CN B2004100347757 A CNB2004100347757 A CN B2004100347757A CN 200410034775 A CN200410034775 A CN 200410034775A CN 1314202 C CN1314202 C CN 1314202C
- Authority
- CN
- China
- Prior art keywords
- circuit
- signal
- group
- analog signal
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention discloses a shared operational amplifier which is used in circuits of the pipeline type architecture. The circuits in all levels of the pipeline type architecture use the shared operational amplifier by turn according to the preset time sequence. The shared operational amplifier comprises an operational amplification circuit, a multiplexing circuit and a demultiplexing circuit, wherein the multiplexing circuit is used for determining in which stage a signal group to be amplified in the circuits can be coupled to the operational amplification circuit, and the demultiplexing circuit is used for sending the amplified signal group back to the circuit in the corresponding stage.
Description
Technical field
The present invention relates to a kind of operational amplifier, and be particularly related to the shared operational amplifier of a kind of pipeline (pipeline) framework.
Background technology
In many electronic circuits, usually be applied to the technology of pipeline (pipeline) framework, so that handle signal step by step.Need in the part pipelined circuits to dispose an operational amplification circuit respectively with the gain signal in circuit at different levels.Often can find only just to use operational amplification circuit if analyze the utilization rate of each operational amplification circuit in part-time, then be idle state At All Other Times.For more clearly demonstrating aforementioned circumstances, will be example below with image sensor (image sensor).
The more and more built-in camera function of electronic product, for example mobile phone, PDA(Personal Digital Assistant) and toys etc.For adapting to various different demands, especially at the demand of running gear, we need the image sensor of low power consumption and high image quality.Figure 1A is the block diagram of typical image sensor.Please refer to Figure 1A, typical image sensor comprises pel array (pixel array) 110, row driver and voltage generator (row driver ﹠amp; Voltage reference) 120 pixel sampling circuit (sample ﹠amp; Hold column circuit) 130, gain circuitry (gain stage) 140 and A/D conversion circuit (pipeline A/D converter) 150.Row driver and voltage generator 120 provide each row to drive signal 121 and various reference voltage 122 and reference voltage VCL.Each row electrode (not illustrating) receives corresponding row respectively and drives signal 121 in the pel array 110, exports the pixel signal (pixel signal) 111 of each row (column) behind the pel array sensing image according to the sequential of row driving signal 121.Pixel sampling circuit 130 receives simultaneously, takes a sample (sample) and keeps (hold) each pixel signal 111 of going, and will keep wherein each pixel signal with series form (cascade) output pixel signal 131 then in regular turn.Gain circuitry 140 receives and amplifies pixel signal 131 backs and produces pixel signal 141.A/D conversion circuit 150 is generally the pipeline A/D conversion circuit, according to reference voltage 122 the pixel signal 141 of analog form is converted to the pixel signal 151 of digital form, handles and utilization in order to subsequent conditioning circuit (among the figure only with control logic circuit 160 representatives).
Usually in the image sensor as Figure 1A, its gain circuitry 140 and A/D conversion circuit 150 are pipelined circuits, are example at this with gain circuitry 140.Figure 1B is known pipeline gain circuitry.Please refer to Figure 1B, promptly with gain circuitry among Figure 1A 140, wherein for example comprise prime multiplier (-icator) 142 and back stage gain device 143 shown in the figure.Each stage gain device all has sample circuit (144 or 146) and amplifying circuit (145 or 147), earlier with the signal sampling and keep (sample and hold) in sample circuit, then with amplifying circuit this signal that gains.That is to say, when gain circuitry 140 desires are amplified pixel signal 131, prime multiplier (-icator) 142 promptly enters the sampling period and (is called reset cycle again, reset phase) pixel signal 131 is remained among capacitor C 1～C2,143 of this moment back stage gain devices enter gain period (gainphase) and provide the pixel signal 148 that before remains in capacitor C 5～C6 and via operational amplification circuit OP2 gain output pixel signal 141 by sample circuit 146.If above-mentioned action is sense control switch SW 1～SW6 conducting and sense control switch SW 7～SW12 is opened circuit with the circuit diagram explanation, and this moment, operational amplification circuit OP1 was an idle state.The sample circuit 144 of current stage gain device 142 is with after 131 samplings of pixel signal and remaining in wherein, prime multiplier (-icator) 142 promptly enters gain period and provides pixel signal 131 via operational amplification circuit OP1 gain output pixel signal 148 by sample circuit 146, and 143 of back stage gain this moment devices enter reset cycle (sampling also keeps pixel signal 148).If above-mentioned action is with circuit diagram explanation, is sense control switch SW 1～SW6 and opens circuit and make sense control switch SW 7～SW12 conducting, and this moment, operational amplification circuit OP2 was an idle state.Repeat above-mentioned action, gain circuitry 140 can be output as pixel signal 141 with 131 gains of pixel signal.
From the above, operational amplification circuit OP2 is then on the shelf when using operational amplification circuit OP1, otherwise then operational amplification circuit OP1 is then on the shelf when using operational amplification circuit OP2.Generally speaking, for keeping the high gain characteristics of operational amplifier, operational amplifier has a certain size DC power supply usually, and in analog circuit, amplifier is that one of circuit power consumption is originated greatly.With CMOS (Complementary Metal Oxide Semiconductor) field effect effect transistor (CMOS) image sensor is example, generally uses duct type analog-digital converter and gain circuitry, and every grade all possesses an operational amplification circuit, uses operational amplification circuit quantity a lot of.But in fact because sampling and keeping in the sequential on the circuit operation, operational amplification circuit in fact only uses the half period, thus how the half period power consumption.So aforementioned operational amplification circuit waste that will form power supply on the shelf.Moreover each grade circuit all need dispose an operational amplification circuit in the pipelined circuits also influences circuit area and cost.
Summary of the invention
Purpose of the present invention is providing a kind of shared operational amplifier to be applied in the pipelined circuits exactly, provide in the pipelined circuits a plurality of grades of circuit to share this shared operational amplifier in turn, and save power consumption, dwindle circuit area and reduce production costs according to scheduled timing.
A further object of the present invention provides a kind of pipeline gain circuitry, the shared operational amplifier of application of aforementioned and reach the effect of saving power consumption, dwindling circuit area and reducing production costs.
Another purpose of the present invention provides a kind of pipeline A/D conversion circuit, the shared operational amplifier of application of aforementioned and reach the effect of saving power consumption, dwindling circuit area and reducing production costs.
The present invention proposes a kind of shared operational amplifier, is applied in the circuit of pipelined architecture.This pipelined architecture comprises a plurality of grades of circuit, and circuit at different levels use this shared operational amplifier in turn according to scheduled timing.Shared operational amplifier comprises operational amplification circuit, duplex circuit and separates duplex circuit.Operational amplification circuit receives and amplifies the first signal group, and the second corresponding signal group of output.Duplex circuit has a plurality of input groups and an output group, according to scheduled timing select in turn each input group one of them and selecteed input group is coupled to the output group, each input group be coupled to respectively corresponding circuit at different levels one of them to receive the 3rd signal group of each grade circuit, the output group is coupled to operational amplification circuit to export the first signal group.Separate duplex circuit and have input group and a plurality of output group, according to scheduled timing select in turn the output group one of them and the input group is coupled to selecteed output group, the input group more is coupled to operational amplification circuit receiving the second signal group, each output group couple respectively corresponding circuit at different levels one of them to export a plurality of the 4th signal groups.
Shared operational amplifier of the present invention can be applied to the reading circuit of image sensor.This image sensor for example is CMOS (Complementary Metal Oxide Semiconductor) field effect effect transistor (CMOS) image sensor.
The present invention proposes a kind of gain circuitry with a pipelined architecture in addition, in order to receiving and to amplify the first signal group, and exports the second signal group, and this gain circuitry comprises prime multiplier (-icator), back stage gain device and shared operational amplifier.The prime multiplier (-icator) comprises prime sample circuit and preamplifying circuit.The prime sample circuit received and the first signal group of taking a sample in the period 1, and then the maintenance sampling result is the 3rd signal group.Preamplifying circuit is in reception second round and amplify the 3rd signal group, and exports the 4th signal group.Back stage gain device is coupled to the prime multiplier (-icator), and back stage gain device comprises back level sample circuit and back level amplifying circuit.Back level sample circuit received and the 4th signal group of taking a sample second round, and then the maintenance sampling result is the 5th signal group.Back level amplifying circuit is in the period 1 reception and amplify the 5th signal group, and exports the second signal group.Shared operational amplifier comprises operational amplification circuit, duplex circuit and separates duplex circuit.Operational amplification circuit receives and amplifies the 6th signal group, and the 7th corresponding signal group of output.Duplex circuit is coupled to operational amplification circuit, preamplifying circuit and back level amplifying circuit, in order to receive the 3rd signal group and the 5th signal group, selects the 5th signal group and the 3rd signal respectively in period 1 and second round, and is output as the 6th signal group.Separate duplex circuit and be coupled to operational amplification circuit, preamplifying circuit and back level amplifying circuit, be provided as the second signal group and the 4th signal group in order to receive the 7th signal group and to switch respectively period 1 and second round.
The present invention proposes a kind of A/D conversion circuit with pipelined architecture again, in order to receive first analog signal, and the first corresponding digital signal of output, this A/D conversion circuit comprises prime analog/digital converter, back level analog/digital converter and shared operational amplifier.The prime analog/digital converter comprises prime sampling and change-over circuit and preamplifying circuit.Prime sampling and change-over circuit are second analog signal in period 1 reception and sampling/maintenance first analog signal, the conversion of second analog signal is produced the second corresponding digital signal, and produce the 3rd corresponding analog signal, and then obtain and export the 4th analog signal after second analog signal and the 3rd analog signal subtracted each other according to second digital signal conversion; Wherein second digital signal is the part position signal of first digital signal.Preamplifying circuit is in reception second round and amplify the 4th analog signal, and exports the 5th analog signal.Back level analog/digital converter is coupled to the prime analog/digital converter, and back level analog/digital converter comprises back level sampling and change-over circuit and back level amplifying circuit.Back level sampling and change-over circuit are the 6th analog signal in period 1 reception and sampling/maintenance the 5th analog signal, the conversion of the 6th analog signal is produced the 3rd corresponding digital signal, and produce the 7th corresponding analog signal, and then obtain and export the 8th analog signal after the 6th analog signal and the 7th analog signal subtracted each other according to the 3rd digital signal conversion; Wherein the 3rd digital signal is the part position signal of first digital signal.Back level amplifying circuit is in the period 1 reception and amplify the 8th analog signal, and exports the 9th analog signal.Shared operational amplifier comprises operational amplification circuit, duplex circuit and separates duplex circuit.Operational amplification circuit receives and amplifies the tenth analog signal, and the 11 corresponding analog signal of output.Duplex circuit is coupled to operational amplification circuit, preamplifying circuit and back level amplifying circuit, in order to receive the 4th analog signal and the 8th analog signal, select the 8th analog signal and the 4th analog signal respectively in period 1 and second round, and be output as the tenth analog signal.Separate duplex circuit and be coupled to operational amplification circuit, preamplifying circuit and back level amplifying circuit, be provided as the 9th analog signal and the 5th analog signal in order to receive the 11 analog signal and to switch respectively period 1 and second round.
The present invention for example shares an operational amplifier in adjacent two-stage gain circuitry because of making circuit shared operational amplifier at different levels in the pipelined circuits, therefore can significantly reduce the use amount of operational amplifier.When each operational amplifier of raising utilizes benefit, more can significantly reduce power consumption, also save circuit layout area (reducing cost).
Description of drawings
Figure 1A is the block diagram of typical image sensor;
Figure 1B is known pipeline gain circuitry;
Fig. 2 is the block diagram of a kind of shared operational amplifier of a preferred embodiment of the present invention;
Fig. 3 is a kind of pipeline gain circuitry with shared operational amplifier of another preferred embodiment of the present invention.
Fig. 4 is the pipeline gain circuitry that the another kind of preferred embodiment of the present invention has shared operational amplifier;
Fig. 5 is the block diagram of general pipeline A/D conversion circuit;
Fig. 6 is a kind of pipeline A/D conversion circuit with shared operational amplifier of preferred embodiment of the present invention.
110: pel array
111: row (column) pixel signal
120: row driver and voltage generator
121: row drive signal
122, VCL: reference voltage
130: pixel sampling circuit
131,141,148: the pixel signal
140,142,143,350,360: gain circuitry/multiplier (-icator)
144,146,351,361,451,461: sample circuit
145,147,352,362,452,462: amplifying circuit
150: A/D conversion circuit
151: the digital pixel signal
160: control logic circuit
201～204: the signal group
210,330,611: duplex circuit
220,320, OP1～OP2: operational amplification circuit
230,340,613: separate duplex circuit
306+, 306-, 307-, 307+, 614+, 614-, 615-, 615+, in1+, in1-, in2+, in2-, out1+, out1-, out2+, out2-: signal
310,410,612: shared operational amplifier
330a, 330b: multiplexer
340a, 340b: de-multiplexer
510: change-over circuits at different levels
511: digital signal
520: digital correction circuit
620,630, ADC1, ADC2: analog/digital converter
C1～C8, C31～C38, C61～C68: electric capacity
D1～D4: digital signal
DAC1, DAC2: digital/analog converter
SW1～SW12, SW301～SW312, SW601～SW618: sense control switch
Vin1+, Vin1-, Vin2+, Vin2-, Vref1+, Vref1-, Vref2+, Vref2-: analog signal
Embodiment
Fig. 2 is the block diagram of a kind of shared operational amplifier of illustrating according to a preferred embodiment of the present invention.Please refer to Fig. 2, this shared operational amplifier is applied in the circuit of pipeline (pipeline) framework.Generally speaking, pipelined architecture comprises a plurality of level (stage) circuit, and these grades circuit uses this shared operational amplifier in turn according to scheduled timing.A plurality of signal groups 203 are represented the original signal group that desire is amplified in the circuit at different levels respectively among the figure.Duplex circuit 210 according to scheduled timing select in turn each signal group 203 one of them and selecteed signal group 203 coupled and is output as signal group 201.Operational amplification circuit 220 receives and amplifies signal group 201, and the corresponding signal group 202 of output.Separate duplex circuit 230 according to scheduled timing (corresponding to duplex circuit 210) select in turn its output group one of them, and signal group 202 is coupled to selecteed output group and output signal group 204.A plurality of signal groups 204 are provided by each output group of separating duplex circuit 230 respectively among the figure, are coupled to each respective stages circuit to reach the function of amplifying signal.
Above-mentioned shared operational amplifier for example is applied to the reading circuit of image sensor in present embodiment.And this image sensor for example is CMOS (Complementary Metal Oxide Semiconductor) field-effect transistor (CMOS) image sensor.
For more clearly demonstrating the present invention, lift a preferred embodiment in addition at this.Fig. 3 is a kind of pipeline gain circuitry that illustrates according to another preferred embodiment of the present invention.Please refer to Fig. 3.Present embodiment is an objective for implementation of the present invention with gain circuitry in the CMOS image sensor (for example gain circuitry 140 of Figure 1A), yet be familiar with this operator and should analogize and be applied to the circuit that other has pipeline and amplifier easily, its result also belongs to category of the present invention.Gain circuitry for example comprises prime multiplier (-icator) 350 and back stage gain device 360 in the CMOS image sensor.Each stage gain device all has sample circuit (351 or 361) and amplifying circuit (352 or 362), earlier with the signal sampling and keep (sample and hold) in sample circuit, then with amplifying circuit this signal that gains.That is to say, when desire is amplified pixel signal 131 with the pixel signal 141 after obtaining gain, prime multiplier (-icator) 350 is introduced into the sampling period and (is called reset cycle again, reset phase) pixel signal 131 is remained among capacitor C 31～C32,360 of back stage gain this moment devices are introduced into gain period (gain phase).
When current stage gain device 350 enters reset cycle (that is back stage gain device 360 enters gain period), duplex circuit 330 is selected signal in2+ and signal in2-are coupled to signal 306+ and signal 306-respectively in the shared operational amplifier 310, separates duplex circuit 340 and selects signal out2-and signal out2+ are coupled to signal 307-and signal 307+ respectively.Sense is controlled switch SW 301～SW306 conducting and sense control switch SW 307～SW312 is opened circuit.The sample circuit 351 of prime multiplier (-icator) 350 receives among the pixel signal 131 and the capacitor C 31～C32 that takes a sample/remain in.Back stage gain device 360 provides previous maintenance pixel signal 148 in capacitor C 35～C36 and be output as signal in2+ and signal in2-by sample circuit 361, obtains pixel signal 141 via operational amplification circuit 320 gains and output.
When current stage gain device 350 enters gain period (back stage gain this moment device 360 enters reset cycle), duplex circuit 330 is selected signal in1+ and signal in1-are coupled to signal 306+ and signal 306-respectively in the shared operational amplifier 310, separates duplex circuit 340 and selects signal out1-and signal out1+ are coupled to signal 307-and signal 307+ respectively.Sense control switch SW 301～SW306 opens circuit, and makes sense control switch SW 307～SW312 conducting.Provide the pixel signal of previous sampling to be sent to shared operational amplifier 310 by sample circuit 351, through gaining and being output as pixel signal 148 via signal end in1+ and in1-.Back stage gain this moment device 360 is with sample circuit 361 pixels sampled signals 148.Repeat above-mentioned action, gain circuitry 140 can utilize the present invention that pixel signal 131 is gained and be output as pixel signal 141.
Duplex circuit 330 for example comprises multiplexer 330a and multiplexer 330b in the present embodiment, for example comprises de-multiplexer 340a and de-multiplexer 340b and separate duplex circuit 340.Multiplexer 330a selects signal in1+ and signal in2+ and switches to be coupled to signal 306+.Multiplexer 330b selects signal in1-and signal in2-and switches to be coupled to signal 306-.De-multiplexer 340a selects signal out1-and signal out2-and switches to be coupled to signal 307-.De-multiplexer 340b selects signal out1+ and signal out2+ and switches to be coupled to signal 307+.
Sense control switch is for example implemented with transmission lock (transmission gate) in the present embodiment.Fig. 4 is the another kind of pipeline gain circuitry that illustrates according to preferred embodiment of the present invention.Please refer to Fig. 4, this figure changes the sense control switch of Fig. 3 to transmit lock enforcement and to finish the pipeline gain circuitry.Wherein sample circuit 451, amplifying circuit 452, sample circuit 461, amplifying circuit 462, shared operational amplifier 410 correspond respectively to sample circuit 351, amplifying circuit 352, sample circuit 361, amplifying circuit 362, the shared operational amplifier 310 of the 3rd figure.The partial circuit of sample circuit 451 is integrated mutually with the pixel sampling circuit (please refer to Figure 1A) of previous stage in Fig. 4 left side, thereby reduces component count.The circuit framework of Fig. 4 is similar to the circuit framework of Fig. 3, is familiar with this operator and all can analogizes easily, so all the other parts of not addressing do not repeat them here.
Fig. 5 is the block diagram of general pipeline A/D conversion circuit.The pipeline A/D conversion circuit is connected in series by multistage change-over circuit 510 (9 grades of change-over circuits are for example arranged) and is formed, each level is less figure place (at these for example 2 s') a digital signal 511 with part information translation in the analog signal, is amplified and is passed to next stage change-over circuit 510 and former simulation signal is deducted after the switched part remaining analog signal.The digital signal 511 that change-over circuits 510 at different levels are exported all is coupled to digital correction circuit 520.Numeral revises (digital correction) circuit 520 and receives the digital signal 511 (for example having 12) that change-over circuits 510 at different levels are exported, and the digital signal that is received is given numeric error correction (digital error correction) and convert the output of final digital signal (for example being 10 digital signal) back to.Because this each grade of pipeline A/D conversion circuit all has the feature of sampling/maintenance and gain output, so can use the present invention to reduce the quantity of operational amplifier.
Exemplify a preferred embodiment at this again according to the present invention, be applied to the enforcement example of pipeline A/D conversion circuit with explanation the present invention.Fig. 6 is a kind of pipeline A/D conversion circuit with shared operational amplifier that illustrates according to preferred embodiment of the present invention.Please refer to Fig. 6, wherein analog/digital converter 620 and analog/digital converter 630 are represented adjacent secondary change-over circuit in the pipeline A/D conversion circuits, and analog/digital converter 620 is the prime change-over circuit of analog/digital converter 630.Each grade analog/digital converter all has sampling and change-over circuit (as sampling and change-over circuit 621 or 631 among the figure) and amplifying circuit (as amplifying circuit among the figure 622 or 632).Sampling and change-over circuit are in sampling period (samplingphase) sampling (from the previous stage circuit) analog signal and remain in wherein, simultaneously with this analog signal conversion and output digital signal.Then remaining analog signal gain output after the analog signal that gain period (gain phase) will be taken a sample and change-over circuit kept deducts switched part of amplifying circuit.And when analog/digital converter 620 entered the sampling period, 630 of analog/digital converters were in gain period, otherwise when analog/digital converter 620 entered gain period, 630 of analog/digital converters were in the sampling period.
When analog/digital converter 620 enters the sampling period when (that is analog/digital converter 630 enters gain period), in shared operational amplifier 610, duplex circuit 611 selects signal in2+ and signal in2-to be coupled to signal 614+ and signal 614-respectively, separates duplex circuit 613 and selects signal out2-and signal out2+ to be coupled to signal 615-and signal 615+ respectively.Sense is controlled switch SW 601～SW609 conducting and sense control switch SW 610～SW618 is opened circuit.This moment analog signal (Vin1+ Vin1-) is sampled and remains among capacitor C 61 and the C62.Analog/digital converter ADC1 with analog signal (Vin1+ Vin1-) is converted to, for example, the binary digit signal (D1, D2).Then (D1, (Vref1+, Vref1-), (Vref1+ Vref1-) will provide the reference voltage of capacitor C 61 with C62 in gain period to this analog signal to digital/analog converter DAC1 D2) to be converted to analog signal with digital signal.Analog/digital converter 630 by sampling and change-over circuit 631 provide the analog signal that before remains among capacitor C 65～C66 (in2+, in2-), via operational amplification circuit 612 gains and output obtain analog signal (out2-, out2+).
When analog/digital converter 620 enters gain period (that is analog/digital converter 630 enters the sampling period), in shared operational amplifier 610, duplex circuit 611 selects signal in1+ and signal in1-to be coupled to signal 614+ and signal 614-respectively, separates duplex circuit 613 and selects signal out1-and signal out1+ to be coupled to signal 615-and signal 615+ respectively.Sense control switch SW 601～SW609 opens circuit and makes sense control switch SW 610～SW618 conducting.This moment analog/digital converter 620 by sampling and change-over circuit 621 provide the analog signal that before remains among capacitor C 61～C62 (in1+, in1-), via operational amplification circuit 612 gains and output obtain analog signal (Vin2+, Vin2-).(Vin2+ is Vin2-) and among take a sample/remain in capacitor C 65 and the C66 and analog/digital converter 630 promptly receives analog signal.Analog/digital converter ADC2 with analog signal (Vin2+ Vin2-) is converted to, for example, two digital signal (D3, D4).Then (D3, (Vref2+, Vref2-), (Vref2+ Vref2-) will provide the reference voltage of capacitor C 65 with C66 in gain period to this analog signal to digital/analog converter DAC2 D4) to be converted to analog signal with digital signal.
Shared operational amplifier 610 is similar to the shared operational amplifier 310 of last embodiment in the present embodiment, therefore repeats no more.
Though the present invention with preferred embodiment openly as above, so it is not in order to limiting the present invention, anyly is familiar with this operator, does a little change and retouching without departing from the spirit and scope of the present invention, all belongs to protection scope of the present invention.
Claims (9)
1. a shared operational amplifier is applied in the circuit of a pipelined architecture, and this pipelined architecture comprises most level circuit, and those grades circuit is shared this shared operational amplifier in turn according to a scheduled timing, and this shared operational amplifier comprises:
One operational amplification circuit, in order to receiving and to amplify one first signal group, and one second corresponding signal group of output;
One duplex circuit, have most input groups and an output group, one of them also is coupled to this output group with selecteed this input group to select those input groups in turn according to this scheduled timing, each those input group be coupled to respectively corresponding those grades circuit one of them to receive one the 3rd signal group of each those grades circuit, this output group is coupled to this operational amplification circuit to export this first signal group;
One separates duplex circuit, have an input group and most output groups, one of them also is coupled to this input group selecteed this output group to select those output groups in turn according to this scheduled timing, this input group is coupled to this operational amplification circuit receiving this second signal group, each those output group couple respectively corresponding those grades circuit one of them to export most the 4th signal groups.
2. shared operational amplifier according to claim 1 is characterized in that: be the reading circuit that is applied to an image sensor.
3. shared operational amplifier according to claim 2 is characterized in that: this image sensor is a CMOS (Complementary Metal Oxide Semiconductor) field effect effect transistor image sensor.
4. a gain circuitry has a pipelined architecture, in order to receiving and to amplify one first signal group, and exports one second signal group, and this gain circuitry comprises:
One prime multiplier (-icator) comprises:
One prime sample circuit is used to period 1 reception and this first signal group of taking a sample, and then the maintenance sampling result is one the 3rd signal group;
One preamplifying circuit is used to receive a second round and amplify the 3rd signal group, and exports one the 4th signal group;
One back stage gain device is coupled to this prime multiplier (-icator), and this back stage gain device comprises:
One back grade sample circuit be used to receive and the 4th signal group of taking a sample this second round, and then the maintenance sampling result is one the 5th signal group;
One back grade amplifying circuit is used to this period 1 reception and amplifies the 5th signal group, and exports this second signal group;
One shares operational amplifier, comprising:
One operational amplification circuit, in order to receiving and to amplify one the 6th signal group, and one the 7th corresponding signal group of output;
One duplex circuit, be coupled to this operational amplification circuit, this preamplifying circuit and this back level amplifying circuit, in order to receive the 3rd signal group and the 5th signal group, select the 5th signal group and the 3rd signal respectively in this period 1 and this second round, and be output as the 6th signal group;
One separates duplex circuit, is coupled to this operational amplification circuit, this preamplifying circuit and this back level amplifying circuit, is provided as this second signal group and the 4th signal group in order to receive the 7th signal group and to switch respectively this period 1 and this second round.
5. gain circuitry according to claim 4 is characterized in that: be the reading circuit that is applied to an image sensor.
6. gain circuitry according to claim 5 is characterized in that: this image sensor is a CMOS (Complementary Metal Oxide Semiconductor) field effect effect transistor image sensor.
7. an A/D conversion circuit has a pipelined architecture, in order to receiving one first analog signal, and one first corresponding digital signal of output, this A/D conversion circuit comprises:
One prime analog/digital converter comprises:
Sampling of one prime and change-over circuit, being used to period 1 reception and this first analog signal of sampling/maintenance is one second analog signal, this second analog signal conversion is produced one second corresponding digital signal, and according to one the 3rd corresponding analog signal of this second digital signal conversion generation, and then obtain and export one the 4th analog signal after this second analog signal and the 3rd analog signal subtracted each other, this second digital signal part position signal that is this first digital signal wherein;
One preamplifying circuit is used to receive a second round and amplify the 4th analog signal, and exports one the 5th analog signal;
One back grade analog/digital converter is coupled to this prime analog/digital converter, and this back level analog/digital converter comprises:
One back level sampling and change-over circuit, being used to this period 1 reception and sampling/maintenance the 5th analog signal is one the 6th analog signal, the conversion of the 6th analog signal is produced one the 3rd corresponding digital signal, and according to one the 7th corresponding analog signal of the 3rd digital signal conversion generation, and then obtain and export one the 8th analog signal after the 6th analog signal and the 7th analog signal subtracted each other, wherein the 3rd digital signal is the part position signal of this first digital signal;
One back grade amplifying circuit is used to this period 1 reception and amplifies the 8th analog signal, and exports one the 9th analog signal;
One shares operational amplifier, comprising:
One operational amplification circuit, in order to receiving and to amplify 1 the tenth analog signal, and 1 the 11 corresponding analog signal of output;
One duplex circuit, be coupled to this operational amplification circuit, this preamplifying circuit and this back level amplifying circuit, in order to receive the 4th analog signal and the 8th analog signal, select the 8th analog signal and the 4th analog signal respectively in this period 1 and this second round, and be output as the tenth analog signal;
One separates duplex circuit, be coupled to this operational amplification circuit, this preamplifying circuit and this back level amplifying circuit, be provided as the 9th analog signal and the 5th analog signal in order to receive the 11 analog signal and to switch respectively this period 1 and this second round.
8. A/D conversion circuit according to claim 7 is characterized in that: be the reading circuit that is applied to an image sensor.
9. A/D conversion circuit according to claim 8 is characterized in that: this image sensor is CMOS (Complementary Metal Oxide Semiconductor) field effect effect transistor (CMOS) image sensor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100347757A CN1314202C (en) | 2004-05-12 | 2004-05-12 | Gain circuit and A/D conversion circuit of sharing operational amplifier and application |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100347757A CN1314202C (en) | 2004-05-12 | 2004-05-12 | Gain circuit and A/D conversion circuit of sharing operational amplifier and application |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1697321A CN1697321A (en) | 2005-11-16 |
| CN1314202C true CN1314202C (en) | 2007-05-02 |
Family
ID=35349881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100347757A Expired - Fee Related CN1314202C (en) | 2004-05-12 | 2004-05-12 | Gain circuit and A/D conversion circuit of sharing operational amplifier and application |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1314202C (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2434494B (en) * | 2006-01-24 | 2008-02-06 | Toumaz Technology Ltd | Low noise amplifier |
| CN102025378B (en) * | 2009-09-14 | 2014-06-18 | 晨星软件研发(深圳)有限公司 | Multichannel sigma-delta converting circuit with shared operational amplifier and associated method thereof |
| US8643432B1 (en) | 2012-07-27 | 2014-02-04 | Hong Kong Applied Science & Technology Research Institute Company Ltd. | Op-Amp sharing by swapping trans-conductance cells |
| US9712774B1 (en) * | 2016-01-14 | 2017-07-18 | Omnivision Technologies, Inc. | Method and system for implementing dynamic ground sharing in an image sensor with pipeline architecture |
| CN109787572B (en) * | 2017-11-10 | 2020-12-25 | 比亚迪股份有限公司 | Switched capacitor subtraction device and image sensor with same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1062048A (en) * | 1989-12-05 | 1992-06-17 | 国际商业机器公司 | The multi-path serial register architecture of video RAM |
| US6262626B1 (en) * | 1998-11-12 | 2001-07-17 | U.S. Philips Corporation | Circuit comprising means for reducing the DC-offset and the noise produced by an amplifier |
| CN1365092A (en) * | 2001-01-09 | 2002-08-21 | 皇家菲利浦电子有限公司 | Driver circuit for display device |
| US6512221B2 (en) * | 2001-03-13 | 2003-01-28 | Cmos Sensor, Inc. | Image sensor chip with an integrated operational amplifier and its application in a CIS module |
-
2004
- 2004-05-12 CN CNB2004100347757A patent/CN1314202C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1062048A (en) * | 1989-12-05 | 1992-06-17 | 国际商业机器公司 | The multi-path serial register architecture of video RAM |
| US6262626B1 (en) * | 1998-11-12 | 2001-07-17 | U.S. Philips Corporation | Circuit comprising means for reducing the DC-offset and the noise produced by an amplifier |
| CN1365092A (en) * | 2001-01-09 | 2002-08-21 | 皇家菲利浦电子有限公司 | Driver circuit for display device |
| US6512221B2 (en) * | 2001-03-13 | 2003-01-28 | Cmos Sensor, Inc. | Image sensor chip with an integrated operational amplifier and its application in a CIS module |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1697321A (en) | 2005-11-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100344066C (en) | Variable resolution A/D converter and radio receiver | |
| CN1242608C (en) | Correlation secondary sampling circuit and CMOS image sensor containing the same circuit | |
| US8896738B2 (en) | Solid-state image pickup device and signal processing method therefor | |
| Watabe et al. | A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADCs | |
| CN101719994B (en) | Solid-state image sensor and camera system | |
| CN1652566A (en) | Correlated-double-sampling amplifier in image sensing device | |
| USRE41519E1 (en) | Method and apparatus for operating a CMOS imager having a pipelined analog to digital converter | |
| CN1909378A (en) | Analog-to-digital converter with noise compensation in cmos image sensor | |
| CN101192831B (en) | Digital-to-analog converter | |
| CN1812508A (en) | Column analog-to-digital converter of a cmos image sensor for preventing a sun black effect | |
| CN1835551A (en) | CMOS image transducer | |
| CN100574385C (en) | A kind of analog picture signal processing method and circuit thereof of cmos image sensor | |
| CN1747526A (en) | Read-out circuit of image sensor | |
| CN1314202C (en) | Gain circuit and A/D conversion circuit of sharing operational amplifier and application | |
| CN1925566A (en) | Image sensor with improved sub-sampling | |
| CN1691517A (en) | Analog-digital converter using clock boosting | |
| Kitamura et al. | A 33 Mpixel, 120 fps CMOS image sensor for UDTV application with two-stage column-parallel cyclic ADCs | |
| US6946987B1 (en) | Common operational amplifier and gain circuit and A/D converter using thereof | |
| CN1725504A (en) | Photoelectric converter, image sensor, and signal reading circuit | |
| CN1604478A (en) | Analog-to-digital converter | |
| JP4419681B2 (en) | Solid-state imaging device | |
| CN111182246B (en) | CMS-based CMOS image sensor reading circuit | |
| CN111669526B (en) | CMOS image sensor for improving frame frequency high-speed all-digital data reading | |
| CN105554421B (en) | global pixel nonlinear compensation structure | |
| CN1794588A (en) | Circulation flow line type analog digital converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: LINGYANG INNOVATIVE TECHNOLOGY HOLDING CO., LTD. Free format text: FORMER OWNER: LINGYANG SCIENCE AND TECHNOLOGY CO., LTD. Effective date: 20130124 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20130124 Address after: Hsinchu Science Park, Taiwan, China Road, line 1, No. 3, building A2 Patentee after: Lingyang Innovative Technology Holding Co., Ltd. Address before: Science and Industry Park, Hsinchu County, Taiwan, China, No. 19 Patentee before: Lingyang Science and Technology Co., Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070502 Termination date: 20170512 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |