CN109787572B - Switched capacitor subtraction device and image sensor with same - Google Patents
Switched capacitor subtraction device and image sensor with same Download PDFInfo
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Abstract
The invention discloses a switched capacitor subtraction device and an image sensor with the same, wherein the subtraction device comprises: a first receiving terminal and a second receiving terminal for receiving a first signal and a second signal, respectively; an output terminal; the device comprises a subtraction processing unit, a first signal processing unit and a second signal processing unit, wherein the subtraction processing unit comprises a first operational amplifier, a second operational amplifier and a first subtraction channel, the first subtraction channel is respectively connected with a first receiving terminal, a second receiving terminal and an output terminal, and when the first subtraction channel works in a sampling mode, the first signal and the second signal are simultaneously sampled through the first subtraction channel, the first operational amplifier and the second operational amplifier; when the first subtraction channel operates in the amplification mode, the sampled first signal and second signal are subjected to subtraction processing by the first subtraction channel, the first operational amplifier and the second operational amplifier to generate a first result, and the first result is output through the output terminal. Therefore, the parallel signal subtraction can be processed, and the operation precision of the subtraction device can be improved.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to a switched capacitor subtraction device and an image sensor with the same.
Background
IN the related art, IN the CMOS image sensor, the switched capacitor subtractor for the analog signal is usually inputted by a serial signal, and as shown IN fig. 1-2, the switch K1 is closed, the subtracted Vrst signal is supplied to the IN terminal, the switch K1 is opened, and the subtracted Vsig signal is supplied to the IN terminal, so that the output Vout' + Vsig-Vrst is obtained as the output of the OUT terminal according to the principle of charge conservation.
However, the related art has a problem that the subtraction of two parallel signals cannot be handled, and a transition establishment process of the subtraction number Vrst and the subtracted number Vsig is held in the output result of the subtractor, affecting the readout speed. In addition, the subtracter samples only the subtraction Vrst and not the subtraction Vsig, so that noise in the Vsig signal is all present at the output of the subtracter, and the output of the subtracter is not all data, and the reference voltage Vref' of the reset sampling is inserted in the middle of the data.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. To this end, it is an object of the present invention to propose a switched capacitor subtraction apparatus capable of processing parallel signals and suppressing or even eliminating noise in the signals.
Another object of the present invention is to provide an image sensor.
In order to achieve the above object, an embodiment of an aspect of the present invention provides a switched capacitor subtraction apparatus, including: a first receiving terminal and a second receiving terminal for receiving a first signal and a second signal, respectively; an output terminal; a subtraction processing unit including a first operational amplifier, a second operational amplifier, a first subtraction channel connected to a first receiving terminal, a second receiving terminal, and the output terminal, respectively, wherein the first signal and the second signal are simultaneously sampled by the first subtraction channel, the first operational amplifier, and the second operational amplifier when the first subtraction channel operates in a sampling mode; when the first subtraction channel operates in an amplification mode, the sampled first signal and second signal are subjected to subtraction processing through the first subtraction channel, the first operational amplifier and the second operational amplifier to generate a first result, and the first result is output through the output terminal.
According to the switched capacitor subtraction device provided by the embodiment of the invention, the first signal and the second signal are respectively received through the first receiving terminal and the second receiving terminal, when the first subtraction channel operates in the sampling mode, the first signal and the second signal are simultaneously sampled through the first subtraction channel, the first operational amplifier and the second operational amplifier, when the first subtraction channel operates in the amplification mode, the sampled first signal and the sampled second signal are subjected to subtraction processing through the first subtraction channel, the first operational amplifier and the second operational amplifier to generate the first result, and the first result is output through the output terminal, so that the subtraction of parallel signals can be processed, the transition time between input signals does not need to be saved, and the operational accuracy of the subtraction device is improved. In addition, by sampling the first signal and the second signal simultaneously, not only can noise of the first signal and the second signal be avoided from being contained in the first result, but also common-mode noise of the first signal and the second signal can be eliminated.
In addition, the switched capacitor subtraction apparatus according to the above embodiment of the present invention may further have the following additional features:
according to one embodiment of the present invention, a third receiving terminal and a fourth receiving terminal for receiving a third signal and a fourth signal, respectively; the subtraction processing unit further comprises a second subtraction channel, the second subtraction channel is respectively connected with a third receiving terminal, a fourth receiving terminal and the output terminal, wherein when the second subtraction channel works in a sampling mode, the third signal and the fourth signal are simultaneously sampled through the second subtraction channel, the first operational amplifier and the second operational amplifier; when the second subtraction channel works in an amplification mode, performing subtraction processing on the sampled third signal and fourth signal through the second subtraction channel, the first operational amplifier and the second operational amplifier to generate a second result, and outputting the second result through the output terminal; wherein the second subtraction channel operates in a sampling mode when the first subtraction channel operates in an amplification mode, and the second subtraction channel operates in an amplification mode when the first subtraction channel operates in the sampling mode.
According to one embodiment of the invention, the first operational amplifier has a first non-inverting input, a first inverting input, and an output, the second operational amplifier has a first non-inverting input, a first inverting input, and an output, the first subtraction channel comprises: a first switch, one end of which is connected to the second receiving terminal; a first capacitor having one end connected to the other end of the first switch and a first node, and the other end connected to a first inverting input terminal of the first operational amplifier, wherein a first non-inverting input terminal of the first operational amplifier is connected to a reference voltage supply terminal for supplying a reference voltage; one end of the second switch is connected with the first node, and the other end of the second switch is connected with the output end of the first operational amplifier; one end of the first auxiliary switch is connected with the other end of the first capacitor, and the other end of the first auxiliary switch is connected with the reference voltage supply end; a third switch, one end of which is connected to the first receiving terminal; one end of the fourth switch is connected with the output end of the first operational amplifier; a second capacitor, one end of which is connected to both the other end of the third switch and the other end of the fourth switch, and the other end of which is connected to the first inverting input terminal of the second operational amplifier and has a second node, wherein the first non-inverting input terminal of the second operational amplifier is connected to the reference voltage supply terminal; one end of the second auxiliary switch is connected with the other end of the second capacitor, and the other end of the second auxiliary switch is connected with the reference voltage providing end; a fifth switch and a sixth switch; and one end of the third capacitor is connected with the second node, the other end of the third capacitor is connected with the reference voltage supply end through the fifth switch, the other end of the third capacitor is further connected with the output end of the second operational amplifier through the sixth switch, and the output end of the second operational amplifier is further connected with the output terminal.
According to an embodiment of the present invention, when the first subtraction channel operates in a sampling mode, the first switch, the third switch, the fifth switch, the first sub-switch, and the second sub-switch are controlled to be closed, and the second switch, the fourth switch, and the sixth switch are controlled to be opened, so as to sample the second signal through the first capacitor and sample the first signal through the second capacitor and the third capacitor; when the first subtraction channel works in an amplification mode, the first switch, the third switch, the fifth switch, the first secondary switch and the second secondary switch are controlled to be turned off, and the second switch, the fourth switch and the sixth switch are controlled to be turned on, so that the sampled first signal and second signal are subjected to subtraction processing through the first capacitor, the second capacitor and the third capacitor to generate the first result.
According to an embodiment of the invention, the first result is a difference signal of the sampled first signal and the sampled second signal and the reference voltage is superimposed. According to an embodiment of the invention, the first operational amplifier further has a second non-inverting input terminal and a second inverting input terminal, the second subtraction channel comprises: a seventh switch, one end of which is connected to the fourth receiving terminal; a fourth capacitor, one end of which is connected to the other end of the seventh switch and has a third node, and the other end of which is connected to the second inverting input terminal of the first operational amplifier, wherein the second non-inverting input terminal of the first operational amplifier is connected to a reference voltage supply terminal that supplies a reference voltage; one end of the eighth switch is connected with the third node, and the other end of the eighth switch is connected with the output end of the first operational amplifier; one end of the third auxiliary switch is connected with the other end of the fourth capacitor, and the other end of the third auxiliary switch is connected with the reference voltage supply end; a ninth switch, one end of which is connected to the third receiving terminal; a tenth switch, one end of which is connected to the output end of the first operational amplifier; a fifth capacitor, one end of which is connected to both the other end of the ninth switch and the other end of the tenth switch, and the other end of which is connected to the second inverting input terminal of the second operational amplifier and has a fourth node, wherein the second non-inverting input terminal of the second operational amplifier is connected to the reference voltage supply terminal; one end of the fourth auxiliary switch is connected with the other end of the fifth capacitor, and the other end of the fourth auxiliary switch is connected with the reference voltage supply end; an eleventh switch and a twelfth switch; and one end of the sixth capacitor is connected with the fourth node, the other end of the sixth capacitor is connected with the reference voltage supply end through the eleventh switch, and the other end of the sixth capacitor is further connected with the output end of the second operational amplifier through the twelfth switch.
According to an embodiment of the present invention, when the second subtraction channel operates in a sampling mode, the seventh switch, the ninth switch, the eleventh switch, the third secondary switch, and the fourth secondary switch are controlled to be closed, and the eighth switch, the tenth switch, and the twelfth switch are controlled to be opened, so as to sample the fourth signal through the fourth capacitor and sample the third signal through the fifth capacitor and the sixth capacitor; when the second subtraction channel operates in an amplification mode, the seventh switch, the ninth switch, the eleventh switch, the third secondary switch, and the fourth secondary switch are controlled to be turned off, and the eighth switch, the tenth switch, and the twelfth switch are controlled to be turned on, so that the sampled third signal and fourth signal are subtracted by the fourth capacitor, the fifth capacitor, and the sixth capacitor to generate the second result.
According to an embodiment of the invention, the second result is a difference signal of the sampled third signal and the sampled fourth signal and the reference voltage is superimposed.
In order to achieve the above object, another embodiment of the present invention provides an image sensor, including: an array of pixels; a column readout circuit; the switched capacitor subtraction apparatus is configured to read out a sampling signal of the pixel array through the column readout circuit.
According to the image sensor provided by the embodiment of the invention, the sampling signals of the pixel array are read out through the column readout circuit according to the switched capacitor subtraction device. Thus, the reading speed of the column reading circuit can be increased by the switched capacitor subtraction device, and the image processing capability of the image sensor can be improved.
According to one embodiment of the invention, the image sensor is a one-dimensional image sensor.
Drawings
FIG. 1 is a schematic circuit diagram of a switched capacitor subtractor employing serial input in the related art;
FIG. 2 is a timing diagram illustrating the operation of the switch capacitor subtractor shown in FIG. 1;
FIG. 3 is a block schematic diagram of a switched capacitor subtraction apparatus according to an embodiment of the present invention;
FIG. 4 is a block schematic diagram of a switched capacitor subtraction apparatus according to one embodiment of the present invention;
FIG. 5 is a block schematic diagram of a switched capacitor subtraction apparatus according to another embodiment of the present invention;
FIG. 6 is a circuit schematic of a switched capacitor subtraction apparatus according to one embodiment of the present invention;
FIG. 7 is a circuit schematic of a first channel sampling mode of a switched capacitor subtraction apparatus according to an embodiment of the present invention;
FIG. 8 is a simplified circuit diagram of a first channel sampling mode of a switched capacitor subtraction apparatus according to an embodiment of the present invention;
FIG. 9 is a circuit schematic of a first channel amplification mode of a switched capacitor subtraction apparatus according to an embodiment of the present invention;
FIG. 10 is a simplified circuit diagram of a first channel amplification mode of a switched capacitor subtraction apparatus according to an embodiment of the present invention;
FIG. 11 is a timing diagram illustrating the operation of the switched capacitor subtraction apparatus according to one embodiment of the present invention;
FIG. 12 is a circuit schematic of an operational amplifier of the switched capacitor subtraction apparatus according to one embodiment of the present invention;
FIG. 13 is a block schematic diagram of an image sensor according to an embodiment of the invention; and
fig. 14 is a circuit schematic diagram of an image sensor according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The following briefly introduces a scheme of implementing the subtraction by using serial input in the related art.
As shown in fig. 1, when the switched capacitor subtractor operates in the sampling mode, the switch K1 is closed, i.e. the clock signal CLK is equal to 1, and the node N 'stores the charge Q1' (Vref '-Vrst) · C1'; when the switched capacitor subtractor operates in the amplification mode, the switch K1 is turned off, that is, the clock signal CLK is equal to 0, and the node N ' stores the charge Q2 ' (Vref ' -Vsig) · C1 ' + (Vref ' -Vout ') · C2 '; the charge injected to the node N 'when the switch K1 is turned off can be ignored, and according to the conservation of the charge at the point N', that is, Q1 'is Q2', if the capacitance is the same, that is, C1 'is C2', the following are provided: vout 'is Vref' + Vsig-Vrst, where Vout 'is the calculation result, Vref' is the reference voltage, Vrst is the decrement, and Vsig is the decremented number.
However, as shown in fig. 2, the setup process of the input signal from the decrement Vrst to the decrement Vsig, which may seriously affect the reading speed of the column readout circuit COLBUF by the analog signal processor ASP, may be saved in the output result Vout'; moreover, the switched capacitor subtractor only samples the subtraction Vrst and does not sample the subtraction Vsig, so that all the noise in the subtraction Vsig appears in the calculation result Vout'; moreover, the common technical problem of the switched capacitor subtracter exists, and the reference voltage Vref' is inserted into the output result.
Based on this, the embodiment of the present invention provides a switched capacitor subtraction apparatus.
The switched-capacitor subtraction apparatus and the image sensor of the embodiments of the present invention are described below with reference to the drawings.
Fig. 3 is a block diagram of a switched capacitor subtraction apparatus according to an embodiment of the present invention. As shown in fig. 3 and 5, the switched capacitor subtraction apparatus according to the embodiment of the present invention includes: a first reception terminal inp1, a second reception terminal inm1, an output terminal OUT, and a subtraction processing unit 10.
Wherein the first receiving terminal inp1 and the second receiving terminal inm1 are respectively used for receiving a first signal and a second signal; the subtraction processing unit 10 includes a first operational amplifier OPA1, a second operational amplifier OPA2, and a first subtraction channel line1, the first subtraction channel line1 being connected to the first receiving terminal inp1, the second receiving terminal inm1, and the output terminal OUT, respectively; when the first subtraction channel line1 operates in the sampling mode, the first signal and the second signal are simultaneously sampled through the first subtraction channel line1, the first operational amplifier OPA1, and the second operational amplifier OPA 2; when the first subtraction channel line1 operates in the amplification mode, the sampled first and second signals are subjected to subtraction processing by the first subtraction channel line1, the first operational amplifier OPA1, and the second operational amplifier OPA2 to generate a first result, and the first result is output through the output terminal OUT.
According to an embodiment of the invention, the first result may be a difference signal of the sampled first signal and the sampled second signal and a reference voltage is superimposed.
Specifically, when the first subtraction channel line1 operates in the sampling mode, the first signal and the second signal are simultaneously sampled by the first subtraction channel line1, the first operational amplifier OPA1, and the second operational amplifier OPA 2; when the first subtraction channel line1 operates in the amplification mode, the sampled first and second signals are subjected to subtraction processing by the first subtraction channel line1, the first operational amplifier OPA1, and the second operational amplifier OPA2 to generate a first result, and the first result is output through the output terminal OUT.
Therefore, the switched capacitor subtraction device of the embodiment of the invention can process the subtraction of the parallel signals, does not need to save the transition time between the input signals, and improves the operation precision of the subtraction device. In addition, by sampling the first signal and the second signal simultaneously, not only can noise of the first signal and the second signal be avoided from being contained in the first result, but also common-mode noise of the first signal and the second signal can be eliminated.
According to an embodiment of the present invention, as shown in fig. 4-5, the switched-capacitor subtraction apparatus further comprises: a third receiving terminal inp2 and a fourth receiving terminal inm 2.
Wherein the third receiving terminal inp2 and the fourth receiving terminal inm2 are respectively used for receiving a third signal and a fourth signal; the subtraction processing unit 10 further includes a second subtraction channel line2, the second subtraction channel line2 being connected to the third receiving terminal inp2, the fourth receiving terminal inm2, and the output terminal OUT, respectively, wherein when the second subtraction channel line2 operates in the sampling mode, the third signal and the fourth signal are simultaneously sampled by the second subtraction channel line2, the first operational amplifier OPA1, and the second operational amplifier OPA 2; when the second subtraction channel line2 operates in the amplification mode, the sampled third and fourth signals are subjected to subtraction processing by the second subtraction channel line2, the first operational amplifier OPA1 and the second operational amplifier OPA2 to generate a second result, and the second result is output through the output terminal OUT.
Wherein the first subtraction channel line1 operates in the amplification mode with the second subtraction channel line2 operating in the sampling mode, and the second subtraction channel line2 operates in the amplification mode with the first subtraction channel line1 operating in the sampling mode.
According to an embodiment of the invention, the second result is a difference signal of the sampled third signal and the sampled fourth signal and the reference voltage is superimposed.
It should be noted that, as shown in fig. 5, the subtraction processing unit 10 includes a first subtraction channel line1, a second subtraction channel line2, a first operational amplifier OPA1 and a second operational amplifier OPA2, the first subtraction channel line1 is respectively connected to the first operational amplifier OPA1 and the second operational amplifier OPA2, and the second subtraction channel line2 is respectively connected to the first operational amplifier OPA1 and the second operational amplifier OPA 2; the first and second receiving terminals inp1 and inm1 are connected to a first subtraction channel line1, and the third and fourth receiving terminals inp2 and inm2 are connected to a first subtraction channel line 2.
That is, the switched-capacitor subtraction apparatus of the embodiment of the present invention has the first receiving terminal inp1, the second receiving terminal inm1, the third receiving terminal inp2, and the fourth receiving terminal inm2 at the same time, and is capable of receiving two sets of signals; meanwhile, the switched capacitor subtraction apparatus has a first subtraction channel line1 and a second subtraction channel line2, and can perform subtraction on two sets of signals to obtain a first result and a second result, respectively. When the first subtraction channel line1 works in the amplification mode, the second subtraction channel line2 works in the sampling mode, and when the first subtraction channel line1 works in the sampling mode, the second subtraction channel line2 works in the amplification mode, so that the switched capacitor subtraction device can process two groups of parallel signals through two-channel alternating sampling and operation, the first result and the second result can be output alternately, and the situation that a reference voltage exists in the output result is avoided.
According to one embodiment of the invention, as shown in FIG. 6, the first operational amplifier OPA1 has a first non-inverting input OPA11+, a first inverting input OPA 11-and an output OPA1outThe second operational amplifier OPA2 has a first non-inverting input OPA21+, a first inverting input OPA21-, and an output OPA2outThe first subtraction channel line1 includes: the capacitive touch panel comprises a first switch CP1, a first capacitor C1, a second switch CP2, a first auxiliary switch CK1, a third switch CP3, a fourth switch CP4, a second capacitor C2, a second auxiliary switch CK2, a fifth switch CP5, a sixth switch CP6 and a third capacitor C3.
Wherein, one end of the first switch CP1 is connected to the second receiving terminal inm 1; one end of the first capacitor C1 is connected to the other end of the first switch CP1 and has a first node J1, and the other end of the first capacitor C1 is connected to a first inverting input OPA 11-of the first operational amplifier OPA1, wherein a first non-inverting input OPA11+ of the first operational amplifier OPA1 is connected to a reference voltage supply terminal Vref supplying a reference voltage; one end of the second switch CP2 is connected to the first node J1, and the other end of the second switch CP2 is connected to the output terminal OPA1 of the first operational amplifier OPA1outConnecting; one end of the first sub-switch CK1 is connected to the other end of the first capacitor C1, and the other end of the first sub-switch CK1 is connected to the reference voltage supply terminal Vref; one end of the third switch CP3 is connected to the first receiving terminal inp 1; one terminal of the fourth switch CP4 and the output terminal OPA1 of the first operational amplifier OPA1outConnecting; one end of a second capacitor C2 is connected to the other end of the third switch CP3 and the other end of the fourth switch CP4, and the second capacitor C2 is connected at the other end to a first inverting input OPA 21-of a second operational amplifier OPA2 and has a second node J2, wherein the first non-inverting input OPA21+ of the second operational amplifier is connected to a reference voltage supply terminal Vref; one end of the second sub-switch CK2 is connected to the other end of the second capacitor C2, and the other end of the second sub-switch CK2 is connected to the reference voltage supply terminal Vref; one terminal of the third capacitor C3 is connected to the second node J2, the other terminal of the third capacitor C3 is connected to the reference voltage supply terminal Vref through the fifth switch CP5, and the other terminal of the third capacitor C3 is also connected to the output terminal OPA2 of the second operational amplifier OPA2 through the sixth switch CP6outWherein the output terminal OPA2 of the second operational amplifieroutAnd also to the output terminal OUT.
It should be noted that, as shown in fig. 11, the first switch CP1, the third switch CP3, and the fifth switch CP5 are controlled by the first clock signal, that is, when the first clock signal is at a high level, the first switch CP1, the third switch CP3, and the fifth switch CP5 are closed, and when the first clock signal is at a low level, the first switch CP1, the third switch CP3, and the fifth switch CP5 are closed; and, the second, fourth and sixth switches CP2, CP4 and CP6 are controlled by the second clock signal, that is, the second, fourth and sixth switches CP2, CP4 and CP6 are closed when the second clock signal is at a high level, and the second, fourth and sixth switches CP2, CP4 and CP6 are opened when the second clock signal is at a low level. The first and second sub switches CK1 and CK2 are controlled by the third clock signal, the first and second sub switches CK1 and CK2 are closed when the third clock signal is at a high level, and the first and second sub switches CK1 and CK2 are turned off when the third clock signal is at a low level. As shown in fig. 11, the first clock signal and the third clock signal are simultaneously at a high level, and when the first clock signal and the third clock signal are at a high level, the second clock signal is at a low level.
Further, according to an embodiment of the present invention, as shown in fig. 7, when the first subtraction channel line1 operates in the sampling mode, the first, third, and fifth switches CP1, CP3, and CP5 and the first and second sub-switches CK1 and CK2 are controlled to be closed, and the second, fourth, and sixth switches CP2, CP4, and CP6 are controlled to be opened, so that the second signal is sampled through the first capacitor C1 and the first signal is sampled through the second and third capacitors C2 and C3.
It should be understood that, when the first subtraction channel line1 operates in the sampling mode, the first and third clock signals are both high and the second clock signal is low, i.e., the first, third, and fifth switches CP1, CP3, and CP5 and the first and second sub-switches CK1 and CK2 are controlled to be closed, and the second, fourth, and sixth switches CP2, CP4, and CP6 are controlled to be opened, so that the second signal is sampled through the first capacitor C1 and the first signal is sampled through the second capacitor C2 and the third capacitor C3.
In contrast, as shown in fig. 9, when the first subtraction channel line1 operates in the amplification mode, the first, third, and fifth switches CP1, CP3, and CP5 and the first and second sub-switches CK1 and CK2 are controlled to be turned off, and the second, fourth, and sixth switches CP2, CP4, and CP6 are controlled to be turned on, so that the sampled first and second signals are subjected to subtraction processing by the first, second, and third capacitors C1, C2, and C3 to generate a first result.
That is, when the first subtraction channel line1 operates in the amplification mode, the first and third clock signals are both low level and the second clock signal is high level, that is, the first, third, and fifth switches CP1, CP3, and CP5 and the first and second sub-switches CK1 and CK2 are controlled to be turned off, and the second, fourth, and sixth switches CP2, CP4, and CP6 are controlled to be turned on, so that the sampled first and second signals are subjected to subtraction processing by the first, second, and third capacitors C1, C2, and C3 to generate a first result.
Specifically, when the first subtraction channel line1 operates in the sampling mode, as shown in fig. 8, the circuit of the first subtraction channel line1 can be simplified as follows: the first receiving terminal inp1, the second capacitor C2, the third capacitor C3 and the reference voltage supply terminal Vref are connected in series in sequence, a second node J2 is provided between the second capacitor C2 and the third capacitor C3, the second node J2 is connected to the reference voltage supply terminal Vref, the second receiving terminal inm1, the first capacitor C1 and the reference voltage supply terminal Vref are connected in series in sequence, at this time, the total charge Q1 at the second node J2 is: q1 ═ C2+ (Vref-Vref) · C3 (Vref-inp1(t 1)). Wherein inp1(t1) is the first signal sampled through the first receiving terminal inp1 at time t1, and time t1 is the time when the first clock signal generates a falling edge, i.e., the sampling mode exits.
When the first subtraction channel line1 operates in the amplification mode, as shown in fig. 10, the circuit of the first subtraction channel line1 can be simplified as follows: the other terminal of the first capacitor C1 is connected to the first inverting input OPA 11-of the first operational amplifier OPA1, and one terminal of the first capacitor C1 is connected to the output OPA1 of the first operational amplifier OPA1outOne end of the second capacitor C2 is connected to one end of the first capacitor C1 and the output OPA1 of the first operational amplifier OPA1, respectivelyoutThe other end of the second capacitor C2 is connected to the first inverting input terminal OPA 21-of the second operational amplifier OPA2 and one end of the third capacitor C3, respectively, the other end of the third capacitor C3 is connected to the output terminal OUT, the first non-inverting input terminal OPA11+ of the first operational amplifier OPA1 and the first non-inverting input terminal OPA21+ of the second operational amplifier OPA2 are both connected to the reference voltage supply terminal Vref, and at this time, the output terminal OPA1 of the first operational amplifier OPA1 is connected to the reference voltage supply terminal Vref according to the flip-flop sample-and-hold principleoutThe output signal of (1) is a second signal inm1(t1) sampled through a second receiving terminal inm1 at time t1, the total charge at a second node J2 is Q2 ═ Vref-inm1(t1)) · C2+ (Vref-OUT) · C3, and according to the charge conservation at the node J2, that is, Q1 ═ Q2, if the second capacitor C2 and the third capacitor C3 have equal capacities, that is, C2 ═ C3, the first result OUT1 is: OUT1 ═ Vref + inp1(t1) -inm1(t 1).
Thus, when the first subtraction channel line1 operates in the sampling mode, the first signal and the second signal can be simultaneously sampled by the first subtraction channel line1, the first operational amplifier OPA1, and the second operational amplifier OPA2, and when the first subtraction channel line1 operates in the amplification mode, the first signal and the second signal can be subjected to subtraction processing by the first subtraction channel line1, the first operational amplifier OPA1, and the second operational amplifier OPA2 to generate the first result OUT1, and the first result OUT1 can be output through the output terminal OUT. Similarly, according to an embodiment of the present invention, as shown in fig. 5, the first operational amplifier OPA1 further has a second non-inverting input OPA12+ and a second inverting input OPA12 ", the second operational amplifier OPA2 further has a second non-inverting input OPA22+ and a second inverting input OPA 22", the second subtraction channel line2 includes: a seventh switch CP7, a fourth capacitor C4, an eighth switch CP8, a third sub-switch CK3, a ninth switch CP9, a tenth switch CP10, a fifth capacitor C5, a fourth sub-switch CK4, an eleventh switch CP11, a twelfth switch CP12, and a sixth capacitor C6.
Wherein, one end of the seventh switch CP7 is connected to the fourth receiving terminal inm 2; one end of the fourth capacitor C4 is connected to the other end of the seventh switch CP7 and has a third node J3, and the other end of the fourth capacitor C4 is connected to a second inverting input OPA 12-of the first operational amplifier OPA1, wherein the second non-inverting input OPA12+ of the first operational amplifier OPA1 is connected to a reference voltage supply terminal Vref supplying a reference voltage; one terminal of the eighth switch CP8 is connected to the third node J3, and the other terminal of the eighth switch CP8 is connected to the output terminal OPA1 of the first operational amplifier OPA1outConnecting; one end of the third sub-switch CK3 is connected to the other end of the fourth capacitor C4, and the other end of the third sub-switch CK3 is connected to the reference voltage supply terminal Vref; one end of the ninth switch CP9 is connected to the third receiving terminal inp 2; one terminal of the tenth switch CP10 and the output terminal OPA1 of the first operational amplifier OPA1outConnecting; one end of a fifth capacitor C5 is connected to both the other end of the ninth switch CP9 and the other end of the tenth switch CP10, and the other end of the fifth capacitor C5 is connected to a second inverting input OPA22 "of the second operational amplifier OPA2 and has a fourth node J4, wherein the second non-inverting input OPA22+ of the second operational amplifier OPA2 is connected to the reference voltage supply terminal Vref; one end of the fourth sub-switch CK4 is connected to the other end of the fifth capacitor C5, and the other end of the fourth sub-switch CK4 is connected to the reference voltage supply terminal Vref; one terminal of a sixth capacitor C6 is connected to the fourth node J4, the other terminal of the sixth capacitor C6 is connected to the reference voltage supply terminal Vref through an eleventh switch CP11, and the other terminal of the sixth capacitor C6 is further connected to the output terminal OPA2 of the second operational amplifier OPA2 through a twelfth switch CP12outAre connected.
It should be noted that the seventh switch CP7, the ninth switch CP9 and the eleventh switch CP11 are controlled by the second clock signal, that is, when the second clock signal is at a high level, the seventh switch CP7, the ninth switch CP9 and the eleventh switch CP11 are closed, and when the second clock signal is at a low level, the seventh switch CP7, the ninth switch CP9 and the eleventh switch CP11 are opened; also, the eighth, tenth and twelfth switches CP8, CP10 and CP12 are controlled by the first clock signal, that is, the eighth, tenth and twelfth switches CP8, CP10 and CP12 are closed when the first clock signal is at a high level, and the eighth, tenth and twelfth switches CP8, CP10 and CP12 are opened when the first clock signal is at a low level. The third sub switch CK3 and the fourth sub switch CK4 are controlled by a fourth clock signal, the third sub switch CK3 and the fourth sub switch CK4 are closed when the fourth clock signal is at a high level, and the third sub switch CK3 and the fourth sub switch CK4 are closed when the fourth clock signal is at a low level. As shown in fig. 11, the second clock signal and the fourth clock signal are simultaneously at a high level, and when the second clock signal and the fourth clock signal are at a high level, the first clock signal is at a low level.
Further, according to an embodiment of the present invention, as shown in fig. 6, when the second subtraction channel line2 operates in the sampling mode, the seventh switch CP7, the ninth switch CP9, and the eleventh switch CP11 and the third sub-switch CK3 and the fourth sub-switch CK4 are controlled to be closed, and the eighth switch CP8, the tenth switch CP10, and the twelfth switch CP12 are controlled to be opened, so that the fourth signal is sampled through the fourth capacitor, and the third signal is sampled through the fifth capacitor C5 and the sixth capacitor C6.
It should be understood that, when the second subtraction channel line1 operates in the sampling mode, both the second clock signal and the fourth clock signal are at a high level and the first clock signal is at a low level, that is, the seventh switch CP7, the ninth switch CP9 and the eleventh switch CP11, and the third sub-switch CK3 and the fourth sub-switch CK4 are controlled to be closed, and the eighth switch CP8, the tenth switch CP10 and the twelfth switch CP12 are controlled to be opened, so that the fourth signal is sampled through the fourth capacitor C4, and the third signal is sampled through the fifth capacitor C5 and the sixth capacitor C6.
On the contrary, when the second subtraction channel line2 operates in the amplification mode, the seventh switch CP7, the ninth switch CP9, and the eleventh switch CP11 and the third sub-switch CK3 and the fourth sub-switch CK4 are controlled to be turned off, and the eighth switch CP8, the tenth switch CP10, and the twelfth switch CP12 are controlled to be turned on, so that the sampled third signal and fourth signal are subjected to subtraction processing by the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 to generate a second result.
That is, when the second subtraction channel line2 operates in the amplification mode, both the second clock signal and the fourth clock signal are at a low level and the first clock signal is at a high level, i.e., the seventh switch CP7, the ninth switch CP9, and the eleventh switch CP11, and the third sub-switch CK3 and the fourth sub-switch CK4 are controlled to be turned off, and the eighth switch CP8, the tenth switch CP10, and the twelfth switch CP12 are controlled to be turned on, so that the sampled third signal and the sampled fourth signal are subjected to subtraction processing by the fourth capacitor C4, the fifth capacitor C5, and the sixth capacitor C6 to generate a second result.
According to an embodiment of the present invention, as shown in fig. 11, taking a set of signal inputs as an example, when the first and third clock signals are at a high level and the second and fourth clock signals are at a low level, the first and second receiving terminals inp1 and inm1 receive signals and output a first result Vref + inp1-inm1 when the first and third clock signals are at a low level and the second and fourth clock signals are at a high level; at this time, the second and third receiving terminals inp1 and inm1 receive signals, and output a second result Vref + inp2-inm2 when the next first and third clock signals are high and the second and fourth clock signals are low. Wherein the setup time between the first result and the second result is determined by the speed of the first operational amplifier OPA1 and the second operational amplifier OPA 2.
Therefore, the second subtraction channel line2 amplifies the first subtraction channel line1 during sampling, and the second subtraction channel line2 samples the first subtraction channel line1 during amplification, which are alternately performed, so that the output terminal can output the first result and the second result in sequence, and the situation that the reference voltage exists in the output is avoided.
According to an embodiment of the present invention, the first operational amplifier OPA1 and the second operational amplifier OPA2 may employ operational amplifiers having a circuit configuration as shown in fig. 12. In summary, according to the switched capacitor subtraction apparatus provided in the embodiment of the present invention, the first receiving terminal and the second receiving terminal respectively receive the first signal and the second signal, and the subtraction processing unit includes a first operational amplifier, a second operational amplifier, and a first subtraction channel; when the first subtraction channel works in a sampling mode, simultaneously sampling the first signal and the second signal through the first subtraction channel, the first operational amplifier and the second operational amplifier; when the first subtraction channel operates in the amplification mode, the sampled first signal and second signal are subjected to subtraction processing by the first subtraction channel, the first operational amplifier and the second operational amplifier to generate a first result, and the first result is output through the output terminal. Therefore, the first signal and the second signal can be simultaneously sampled in the sampling mode, so that the noise in the signals is eliminated, the process of input signal transition establishment is eliminated, only calculation results are contained in output, and the operation precision of the subtraction device is improved.
The embodiment of the invention also provides an image sensor.
Fig. 13 is a block diagram of an image sensor according to an embodiment of the present invention. As shown in fig. 13, the image sensor 200 includes a pixel array 20, a column readout circuit 30, and a switched capacitor subtraction device 100.
The switched capacitor subtraction apparatus 100 is used to read out the sampling signal of the pixel array 20 through the column readout circuit 30.
According to an embodiment of the present invention, as shown in fig. 14, the odd column pixels 21 in the pixel array 20 are sampled by the column readout circuit 30 and then connected to the first receiving terminal inp1 and the second receiving terminal inm1, and the even column pixels 22 are sampled by the column readout circuit 30 and then connected to the third receiving terminal inp2 and the fourth receiving terminal inm 2.
According to one embodiment of the invention, the image sensor 200 is a one-dimensional image sensor. That is, the switched capacitor subtraction apparatus 100 of the foregoing embodiment can be applied to a one-dimensional image sensor, and more particularly, to an analog signal processing circuit of a barcode scanning chip of a one-dimensional image sensor.
In this way, the COLBUF column readout circuit 30 of the one-dimensional image sensor reads out the double-sampled signal of the Pixel Array 20, and the subtraction processing of the double-sampled signal is completed by the switched capacitor subtraction apparatus 100 according to the foregoing embodiment.
In summary, according to the image sensor provided by the embodiment of the invention, the sampling signal of the pixel array is read out by the column readout circuit according to the switched capacitor subtraction apparatus. Thus, the parallel signal subtraction can be processed without saving the transition time between the input signals, and the calculation accuracy of the subtraction device is improved.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (9)
1. A switched capacitor subtraction apparatus, comprising:
a first receiving terminal and a second receiving terminal for receiving a first signal and a second signal, respectively;
an output terminal;
a subtraction processing unit including a first operational amplifier, a second operational amplifier, a first subtraction channel connected to a first receiving terminal, a second receiving terminal, and the output terminal, respectively, wherein,
when the first subtraction channel is operated in a sampling mode, simultaneously sampling the first signal and the second signal through the first subtraction channel, the first operational amplifier and the second operational amplifier;
when the first subtraction channel works in an amplification mode, performing subtraction processing on the sampled first signal and second signal through the first subtraction channel, the first operational amplifier and the second operational amplifier to generate a first result, and outputting the first result through the output terminal;
a third receiving terminal and a fourth receiving terminal for receiving a third signal and a fourth signal, respectively;
the subtraction processing unit further comprises a second subtraction channel connected to a third receiving terminal, a fourth receiving terminal and the output terminal, respectively, wherein,
when the second subtraction channel operates in a sampling mode, simultaneously sampling the third signal and the fourth signal through the second subtraction channel, the first operational amplifier and the second operational amplifier;
when the second subtraction channel works in an amplification mode, performing subtraction processing on the sampled third signal and fourth signal through the second subtraction channel, the first operational amplifier and the second operational amplifier to generate a second result, and outputting the second result through the output terminal;
wherein the second subtraction channel operates in a sampling mode when the first subtraction channel operates in an amplification mode, and the second subtraction channel operates in an amplification mode when the first subtraction channel operates in the sampling mode.
2. The switched-capacitor subtraction device according to claim 1, wherein the first operational amplifier has a first non-inverting input, a first inverting input, and an output, the second operational amplifier has a first non-inverting input, a first inverting input, and an output, the first subtraction channel comprises:
a first switch, one end of which is connected to the second receiving terminal;
a first capacitor having one end connected to the other end of the first switch and a first node, and the other end connected to a first inverting input terminal of the first operational amplifier, wherein a first non-inverting input terminal of the first operational amplifier is connected to a reference voltage supply terminal for supplying a reference voltage;
one end of the second switch is connected with the first node, and the other end of the second switch is connected with the output end of the first operational amplifier;
one end of the first auxiliary switch is connected with the other end of the first capacitor, and the other end of the first auxiliary switch is connected with the reference voltage supply end;
a third switch, one end of which is connected to the first receiving terminal;
one end of the fourth switch is connected with the output end of the first operational amplifier;
a second capacitor, one end of which is connected to both the other end of the third switch and the other end of the fourth switch, and the other end of which is connected to the first inverting input terminal of the second operational amplifier and has a second node, wherein the first non-inverting input terminal of the second operational amplifier is connected to the reference voltage supply terminal;
one end of the second auxiliary switch is connected with the other end of the second capacitor, and the other end of the second auxiliary switch is connected with the reference voltage providing end;
a fifth switch and a sixth switch;
and one end of the third capacitor is connected with the second node, the other end of the third capacitor is connected with the reference voltage supply end through the fifth switch, the other end of the third capacitor is further connected with the output end of the second operational amplifier through the sixth switch, and the output end of the second operational amplifier is further connected with the output terminal.
3. The switched capacitor subtraction apparatus of claim 2,
when the first subtraction channel works in a sampling mode, the first switch, the third switch, the fifth switch, the first auxiliary switch and the second auxiliary switch are controlled to be closed, and the second switch, the fourth switch and the sixth switch are controlled to be turned off, so that the second signal is sampled through the first capacitor, and the first signal is sampled through the second capacitor and the third capacitor;
when the first subtraction channel works in an amplification mode, the first switch, the third switch, the fifth switch, the first secondary switch and the second secondary switch are controlled to be turned off, and the second switch, the fourth switch and the sixth switch are controlled to be turned on, so that the sampled first signal and second signal are subjected to subtraction processing through the first capacitor, the second capacitor and the third capacitor to generate the first result.
4. The switched-capacitor subtraction device according to claim 3, wherein the first result is a difference signal of the sampled first signal and the sampled second signal and the reference voltage is superimposed.
5. The switched capacitor subtraction device according to any of claims 2-4, wherein the first operational amplifier further has a second non-inverting input and a second inverting input, the second subtraction path comprises:
a seventh switch, one end of which is connected to the fourth receiving terminal;
a fourth capacitor, one end of which is connected to the other end of the seventh switch and has a third node, and the other end of which is connected to the second inverting input terminal of the first operational amplifier, wherein the second non-inverting input terminal of the first operational amplifier is connected to a reference voltage supply terminal that supplies a reference voltage;
one end of the eighth switch is connected with the third node, and the other end of the eighth switch is connected with the output end of the first operational amplifier;
one end of the third auxiliary switch is connected with the other end of the fourth capacitor, and the other end of the third auxiliary switch is connected with the reference voltage supply end;
a ninth switch, one end of which is connected to the third receiving terminal;
a tenth switch, one end of which is connected to the output end of the first operational amplifier;
a fifth capacitor, one end of which is connected to both the other end of the ninth switch and the other end of the tenth switch, and the other end of which is connected to the second inverting input terminal of the second operational amplifier and has a fourth node, wherein the second non-inverting input terminal of the second operational amplifier is connected to the reference voltage supply terminal;
one end of the fourth auxiliary switch is connected with the other end of the fifth capacitor, and the other end of the fourth auxiliary switch is connected with the reference voltage supply end;
an eleventh switch and a twelfth switch;
and one end of the sixth capacitor is connected with the fourth node, the other end of the sixth capacitor is connected with the reference voltage supply end through the eleventh switch, and the other end of the sixth capacitor is further connected with the output end of the second operational amplifier through the twelfth switch.
6. Switched capacitor subtraction device according to claim 5,
when the second subtraction channel works in a sampling mode, the seventh switch, the ninth switch, the eleventh switch, the third secondary switch and the fourth secondary switch are controlled to be closed, and the eighth switch, the tenth switch and the twelfth switch are controlled to be opened, so that the fourth signal is sampled through the fourth capacitor, and the third signal is sampled through the fifth capacitor and the sixth capacitor;
when the second subtraction channel operates in an amplification mode, the seventh switch, the ninth switch, the eleventh switch, the third secondary switch, and the fourth secondary switch are controlled to be turned off, and the eighth switch, the tenth switch, and the twelfth switch are controlled to be turned on, so that the sampled third signal and fourth signal are subtracted by the fourth capacitor, the fifth capacitor, and the sixth capacitor to generate the second result.
7. The switched-capacitor subtraction device according to claim 6, wherein the second result is a difference signal of the sampled third signal and the sampled fourth signal and the reference voltage is superimposed.
8. An image sensor, comprising:
an array of pixels;
a column readout circuit;
the switched capacitor subtraction device of any of claims 1-7, used to read out a sampled signal of the pixel array by the column readout circuit.
9. The image sensor of claim 8, wherein the image sensor is a one-dimensional image sensor.
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| CN1314202C (en) * | 2004-05-12 | 2007-05-02 | 凌阳科技股份有限公司 | Gain circuit and A/D conversion circuit of sharing operational amplifier and application |
| KR100719370B1 (en) * | 2005-08-03 | 2007-05-17 | 삼성전자주식회사 | Analog-to-digital converter and cmos image sensor with the same and method of operating cmos image sensor |
| JP4837673B2 (en) * | 2005-11-21 | 2011-12-14 | パナソニック株式会社 | Fully differential amplifier circuit |
| CN102904571A (en) * | 2011-07-29 | 2013-01-30 | 比亚迪股份有限公司 | Allowance gain circuit |
| CN103138762B (en) * | 2011-11-30 | 2016-04-27 | 禾瑞亚科技股份有限公司 | Multistage sample-and-hold circuit |
| US8471744B1 (en) * | 2011-12-01 | 2013-06-25 | Hong Kong Applied Science & Technology Research Institute Company, Ltd. | Reduced residual offset sigma delta analog-to-digital converter (ADC) with chopper timing at end of integrating phase before trailing edge |
| KR102074944B1 (en) * | 2013-06-18 | 2020-02-07 | 삼성전자 주식회사 | Programmable gain amplifier and devices having the same |
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