CN1313976C - JPEG 2000 image coding and transmitting method and system based on embedded platform - Google Patents
JPEG 2000 image coding and transmitting method and system based on embedded platform Download PDFInfo
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- CN1313976C CN1313976C CNB2005100235741A CN200510023574A CN1313976C CN 1313976 C CN1313976 C CN 1313976C CN B2005100235741 A CNB2005100235741 A CN B2005100235741A CN 200510023574 A CN200510023574 A CN 200510023574A CN 1313976 C CN1313976 C CN 1313976C
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Abstract
The present invention relates to a method and a system for coding and transmitting JPEG2000 images based on an embedded platform. The coding and the transmission of the images comprise the steps: receiving analog signals transmitted from a camera by using an image collecting part, and carrying out A/D conversion; receiving image data collected and converted by the image collecting part by an image coding part, and coding the images by using a hardware coding mode according to a JPEG2000 format. The coding mode and the coding process comprise: (1) memorizing the image data transmitted from the collecting part into a memorizer in a buffer way; (2) designing an image coding algorithm based on an FPGA platform, and directly generating coding data by using a hardware logic; (3) memorizing the coded data into the memorizer, obtaining image coding data which is in the JPEG2000 format and is generated by the image coding part by using a processing control part, packaging the data according to a TCP/IP protocol, and forwarding the data to an ethernet through a standard ethernet interface. The system is composed of the image collecting part, the image coding part, the processing control part and a power supply part. The whole system of the present invention is based on the embedded processor platform, and the system has the advantages of simple structure, high quality of image coding, high speed, high data processing capability, small volume and low cost.
Description
Technical field
The present invention relates to a kind of coding and transmission method and system of JPEG2000 image, the especially a kind of device that can realize on based on EP1C12Q240C8 and S3C4510B embedded platform carries out coding and the transmission method and the system of image.
Background technology
The JPEG2000 standard is high-quality still image coding standard, can provide from can't harm to the image coding and decoding algorithm of the different compression qualities that diminish.Along with multimedia and development of internet technology, the network image transmission is used widely.
Because JPEG2000 coding standard compressed image quality height, algorithm complexity, thereby at present traditional coded system all adopts based on the computer platform of PC or based on the high-end MCU of embedded OS and realizes, the equipment bulky complex, the cost height, travelling speed is low with execution efficient.Along with civil nature, the universalness that the video network transmission product is used, the picture coding and the network transmission system of research portable, cheap seem particularly important.Simultaneously, in the applied environment that needs the Real Time Compression image, need efficiently picture coding parts fast, use the method for traditional software compression not meet the demands, thereby need a kind of method of using hardware circuit directly to finish picture coding.
Summary of the invention
The object of the present invention is to provide a kind of based on the JPEG2000 picture coding of embedded platform and the method and system of transmission.This system can handle the image by camera collection in real time, with the hardware circuit logic institute's images acquired is carried out real-time coding according to the JPEG2000 standard, and the data behind the coding are transmitted by Ethernet according to ICP/IP protocol.Whole system is based on embedded processor platform, and is simple in structure, and the picture coding quality is good, speed is fast, and data-handling capacity is strong, and volume is little, cost is low.
For achieving the above object, the present invention adopts following technical proposals:
A kind of JPEG2000 picture coding and transmission method based on embedded platform is characterized in that the job step of this picture coding and transmission system is:
A. adopt image acquisition component to receive the simulating signal that camera transmits, carry out the A/D conversion;
B. adopt the picture coding parts to receive the view data of image acquisition component collection conversion, use the hardware encoding mode that image is carried out JPEG2000 form coding, coded system and flow process are: 1. the view data that acquisition component is transmitted is buffered in the storer, 2. design picture coding algorithm based on the FPGA platform, use hardware logic directly to produce coded data, the data storage after 3. will encoding is in storer; Above-mentioned picture coding parts extract view data from the video data buffer of acquisition component, according to JPEG2000 coding standard algorithm, use the hardware circuit logic to finish picture coding, this cataloged procedure realizes that on the FPGA platform data behind the coding are put into coded data buffer; Above-mentioned control treatment part extracts coded data from coded data buffer, cutting apart packing according to required data layout handles, generation meets the packet that ICP/IP protocol requires, according to request msg sender's network ip address, packet is mail to the PC of far-end by standard ethernet network interface again; The network port that above-mentioned control treatment part is appointed in advance to certain and LAN (Local Area Network) inner computer is intercepted.In case receive the request of transmitted image coded data, the IP address of promptly using the requestor according to ICP/IP protocol, sends to the requestor by Ethernet with encoded image data as destination address.
C. adopt control treatment part, obtain the image coded data of the JPEG2000 form that the picture coding parts produce, and with these data according to the ICP/IP protocol processing of packing, be forwarded to Ethernet by the standard ethernet interface again.
A kind of be used for above-mentioned based on the JPEG2000 picture coding of embedded platform and the system of transmission method, form by image acquisition component, picture coding parts, processor controls parts and power supply unit, it is characterized in that: image acquisition component is connected by corresponding interface circuits with the picture coding parts, the picture coding parts link to each other with control treatment part by corresponding interface circuits, control treatment part links to each other with the external ethernet network, and each parts power input mouth of power supply unit and other is connected;
Above-mentioned image acquisition component includes video acquisition head, image collection chip, and the output of video acquisition head links to each other with the input of image collection chip.The model of described image collection chip is the SAA7113H of Philips company.
Above-mentioned picture coding parts include fpga chip, SDRAM chip, PROM chip, the data bus of SDRAM chip, PROM chip, address bus link to each other with the universal port of fpga chip, wherein, the SDRAM chip is as the data-carrier store of fpga chip, and the PROM chip is as the config memory of fpga chip.The model of described fpga chip is the EP1C12Q240CB of altera corp, and the model of SDRAM chip is the K4S643232F of Samsung company, and the model of PROM chip is the EPCS1 of altera corp;
Above-mentioned control treatment part includes flush bonding processor, SDRAM chip, FLASH chip, ethernet physical layer chip, the data bus of SDRAM chip, FLASH chip, address bus link to each other with the corresponding bus of flush bonding processor, and the ethernet physical layer chip links to each other with the universal port of flush bonding processor.The model of described flush bonding processor is the S3C4510B of Samsung company, the model of SDRAM chip is the K4S643232F of Samsung company, the model of FLASH chip is the 39VF800A of SST company, and the model of ethernet physical layer chip is the AC101-TF of ALTIMA company.
Above-mentioned power supply unit includes the DC-DC conversion chip of 3.3V, 1.8V; 1.8V the DC-DC conversion chip link to each other with the power end of fpga chip, its model is the L10855 of NIKO company; 3.3V the DC-DC conversion chip link to each other with the power end of other chips such as flush bonding processor, its model is the AS2830-3.3 of ALPH company.
The present invention compared with prior art has following conspicuous outstanding substantive distinguishing features and remarkable advantage:
1. the present invention adopts fpga chip to realize the JPEG2000 standard code of image, finish encryption algorithm with the hardware circuit logic, the generation coded data has improved code rate and efficient greatly, compares with traditional software coding mode to have encoding characteristics rapidly and efficiently.
2. the present invention adopts Embedded hardware configuration, has guaranteed that this image delivering system has higher stability and reliability than the system based on PC, and travelling speed is fast, need not the personal management, is fit to very much long-range unattended environment.
3. the present invention is the network equipment of a standard, only needs to specify an effective I P address, just can with various types of ethernet device seamless links.Because Internet is the network environment of an opening, so as long as the present invention is inserted Internet, can carry out application such as remote monitoring, networking mode is flexible, has good extendability.Also have little, the easy to use characteristics of volume simultaneously.
4. the general network image delivering system all needs complicated system usually, relates to PC, Add-ons and hardware device.The present invention need not extra equipment, cheap,
Description of drawings
Fig. 1 is a system architecture diagram of the present invention.
Fig. 2 is the connection layout of image acquisition component of the present invention.
Fig. 3 is the connection layout of picture coding parts of the present invention.
Fig. 4 is the connection layout of control treatment part of the present invention.
Fig. 5 is the connection layout of power supply unit of the present invention.
Embodiment
The present invention is further described below in conjunction with drawings and Examples.A preferred embodiment of the present invention is referring to Fig. 1, and this example is based on the JPEG2000 picture coding and the transmission system of embedded platform, is connected and composed by image acquisition component 1, picture coding parts 2, control treatment part 3, power supply unit 4.Image acquisition component 1 links to each other with picture coding parts 2, and picture coding parts 2 link to each other with control treatment part 3, and power supply unit 4 links to each other with parts 1,2,3 respectively.Image acquisition component 1 links to each other with camera, and control treatment part 3 links to each other with external ethernet 6.
Above-mentioned image acquisition component 1 comprises coaxial video acquisition joint 7 and image collection chip 8, and the chip model is the SAA7113H of Philips company, and its connected mode as shown in Figure 2.Coaxial video acquisition joint 7 links to each other with the video inputs of SAA7113H, and the vision signal input SAA7113H with the outside carries out the image acquisition conversion; The data output of SAA7113H links to each other with the fpga chip 9 of picture coding parts 2 with synchronizing signal output, the view data that collects is sent into buffer memory in the fpga chip 9, the control signal of SAA7113H also links to each other with FPGA, produces steering logic by FPGA, control SAA7113H work.Outer video signal is changed into Digital Image Data to send into picture coding parts 2 by after the image acquisition component 1.
Above-mentioned picture coding parts 2 comprise fpga chip 9, and model is the EP1C12Q240CB of altera corp; SDRAM chip 10, model are the K4S643232F of Samsung company; PROM chip 11, model are the EPCS1 of altera corp.Each chip connects as shown in Figure 3.Wherein fpga chip 9 is main process chip of picture coding parts 2, is used to realize the picture coding of JPEG2000 standard.Its input/output end port links to each other with data-signal, synchronizing signal and the control signal of image acquisition component 1, be responsible for from image acquisition component 1, obtaining Digital Image Data, be buffered in the SDRAM storer, and, image encoded according to the encryption algorithm of JPEG2000 standard-required; Simultaneously it also links to each other with flush bonding processor chip in the control treatment part 3, sends the data after encoding to the control and treatment chip.PROM chip 11 is configuration store chips of FPGA system, links to each other with the configuration pin of fpga chip 9, fpga chip 9 is configured to meet the coding chip of JPEG2000 canonical algorithm.The address wire Addr of SDRAM, data line Data link to each other with the input/output interface of gating signal with fpga chip 9, as the data buffer of fpga chip, and the storage Digital Image Data.
Above-mentioned control treatment part 3 comprises 32 flush bonding processors 12, and model is the S3C4510B of Samsung company; SDRAM chip 13, model are the K4S643232F of Samsung company; FLASH chip 14, model are the 39VF800A of SST company; Ethernet physical layer chip 15, model can be the AC101-TF of ALTIMA company.Each chip connects as shown in Figure 4.Wherein flush bonding processor 12 is the key process unit of system, its I/O pin links to each other with the I/O pin of fpga chip 9 in the picture coding parts 2, directly obtain through fpga chip 9 encoded image data, and to these data according to the processing of packing of Ethernet transmission standard, send by Ethernet 6.The address wire of SDRAM, data line, gating control line link to each other the data storage area when working as processor with address bus, data bus and the storage select lines of processor chips respectively.The address wire of FLASH chip 14, data line and gating control line also link to each other with address bus, data bus and the storage select lines of processor chips respectively, as the program space of processor.The data input/output line of ethernet physical layer chip 15, control line link to each other with the input/output line of processor chips, come Control work by processor, as with the data-interface of Ethernet, the data after the packing send on the network by this chip.
Above-mentioned power supply unit 4 comprises the DC-DC conversion chip 16,17 of 3.3V and 1.8V, 3.3V the model of DC-DC conversion chip 16 are A82830-3.3 of ALPH company, 1.8V the model of DC-DC conversion chip 17 are L1085S of NIKO company, chip connects as shown in Figure 5.The power supply input of conversion chip is outside input power supply, and the output of 1.8V conversion chip 17 links to each other with the power supply input of fpga chip 9, for fpga chip 9 provides power supply; 3.3V the power supply of other chips such as the output of conversion chip and flush bonding processor links to each other, for their work provides power supply.
After system powered on, the start-up code that leaves in the FLASH chip in the control treatment part 3 was moved automatically, and peripheral chip such as initialisation image acquisition chip, Network Transmission chip is provided with its running parameter in application program; The configuration data that leaves in simultaneously among the PROM in the picture coding parts 2 is transferred in the fpga chip 9 automatically, fpga chip 9 is configured to meet the image encoding system of JPEG2000 canonical algorithm.
The workflow of system is: image acquisition component 1 receives the analog picture signal that video camera transmits by video-frequency connector, is converted into data image signal, and sends the fpga chip 9 in the picture coding parts 2 to, is stored in the buffer zone; 9 pairs of these digital signals of fpga chip in the picture coding parts 2 use circuit logic to carry out digital coding, and the bit stream data after will encoding leave coded data buffer in according to the JPEG2000 canonical algorithm; Flush bonding processor chip in the control treatment part 3 and the fpga chip 9 in the picture coding parts 2 carry out data transfer operation by input/output interface, from coded data buffer, extract the JPEG2000 coded data of image, carry out the dividing processing packing according to ICP/IP protocol; Control treatment part is intercepted particular network port in the LAN (Local Area Network) simultaneously, in case receive the request that transmits video data, the IP address of promptly using the requestor sends to far-end requestor by Ethernet with encoded image data as destination address.
Claims (2)
1. JPEG2000 picture coding and transmission method based on an embedded platform is characterized in that the step of this picture coding and transmission is:
A. adopt image acquisition component (1) to receive the simulating signal that camera (5) transmits, carry out the A/D conversion;
B. adopt picture coding parts (2) to receive the view data that image acquisition component (1) is gathered conversion, use the hardware encoding mode that image is carried out JPEG2000 form coding, coded system and flow process are: 1. the view data that acquisition component (1) is transmitted is buffered in the storer, 2. design picture coding algorithm based on the FPGA platform, use hardware logic directly to produce coded data, the data storage after 3. will encoding is in storer; Described picture coding parts (2) extract view data from the video data buffer of acquisition component (1), according to JPEG2000 coding standard algorithm, use the hardware circuit logic to finish picture coding, this cataloged procedure realizes that on the FPGA platform data behind the coding are put into coded data buffer; Described control treatment part (3) extracts coded data from coded data buffer, cutting apart packing according to required data layout handles, generation meets the packet that ICP/IP protocol requires, according to request msg sender's network ip address, packet is mail to the PC of far-end by standard ethernet network interface again; The network port that described control treatment part (3) is appointed in advance to certain and LAN (Local Area Network) inner computer is intercepted, in case receive the request of transmitted image coded data, the IP address of promptly using the requestor is as destination address, according to ICP/IP protocol, encoded image data is sent to the requestor by Ethernet (6).
C. adopt control treatment part (3), obtain the image coded data of the JPEG2000 form that picture coding parts (2) produce, and with these data according to the ICP/IP protocol processing of packing, be forwarded to Ethernet (6) by the standard ethernet interface again.
One kind to be used for claim 1 described based on the JPEG2000 picture coding of embedded platform and the system of transmission method, by image acquisition component (1), picture coding parts (2), processor controls parts (3) and power supply unit (4) are formed, it is characterized in that: image acquisition component (1) is connected by corresponding interface circuits with picture coding parts (2), picture coding parts (2) link to each other with control treatment part (3) by corresponding interface circuits, control treatment part (3) links to each other with external ethernet network (6), and each parts power input mouth of power supply unit (4) and other is connected; Described image acquisition component (2) includes video acquisition head (7) and image collection chip (8), the output of video acquisition head (7) links to each other with the input of image collection chip (8), and the model of described image collection chip (8) is the SAA7113H of Philips company; Described picture coding parts include fpga chip (9), SDRAM chip (10), PROM chip (11), the data bus of SDRAM chip (10) and PROM chip (11), address bus link to each other with the universal port of fpga chip (9), wherein, SDRAM chip (10) is as the data-carrier store of fpga chip (9), and PROM chip (11) is as the config memory of fpga chip (9); The model of described fpga chip (9) is the EP1C12Q240CB of altera corp, and the model of SDRAM chip (10) is the K4S643232F of Samsung company, and the model of PROM chip (11) is the EPCS1 of altera corp; Described control treatment part (3) includes flush bonding processor (12), SDRAM chip (13), FLASH chip (14) and ethernet physical layer chip (15), SDRAM chip (13), the data bus of FLASH chip (14), address bus links to each other with the corresponding bus of flush bonding processor (12), ethernet physical layer chip (15) links to each other with the universal port of flush bonding processor (12), the model of described flush bonding processor (12) is the S3C4510B of Samsung company, the model of SDRAM chip (13) is the K4S643232F of Samsung company, the model of FLASH chip (14) is the 39VF800A of SST company, and the model of ethernet physical layer chip (15) is the AC101-TF of ALTIMA company; Described power supply unit (4) includes the DC-DC conversion chip (16,17) of 3.3V, 1.8V; 1.8V DC-DC conversion chip (17) link to each other with the power end of fpga chip (9), its model is the L1085S of NIKO company; 3.3V DC-DC conversion chip (16) link to each other with the power end of flush bonding processor (12), its model is the AS2830-3.3 of ALPH company.
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| CN102547288B (en) * | 2012-01-11 | 2015-01-07 | 山东大学 | Runtime reconfigurable embedded security real-time image compression system and working method |
| CN102946537A (en) * | 2012-11-06 | 2013-02-27 | 中国科学院上海微系统与信息技术研究所 | System for realizing JPEG (joint photographic experts group) 2000 image coding by combining DSP (digital signal processor) and compression chip |
| CN106558083A (en) * | 2016-11-30 | 2017-04-05 | 郑州云海信息技术有限公司 | A kind of accelerated method in webp compression algorithms infra-frame prediction stage, apparatus and system |
| CN110855996B (en) * | 2019-09-30 | 2021-10-22 | 中国船舶重工集团公司第七0九研究所 | Image coding and decoding and network transmission method and device based on FPGA |
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| CN112437309A (en) * | 2020-11-12 | 2021-03-02 | 北京深维科技有限公司 | JPEG encoding method and device |
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