CN1558682A - Embedded image processor - Google Patents
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- CN1558682A CN1558682A CNA2004100126595A CN200410012659A CN1558682A CN 1558682 A CN1558682 A CN 1558682A CN A2004100126595 A CNA2004100126595 A CN A2004100126595A CN 200410012659 A CN200410012659 A CN 200410012659A CN 1558682 A CN1558682 A CN 1558682A
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Abstract
The invention relates to a multifunctional integration embedded static image compression system, wherein the image gathering module comprises a video decoder, a video gathering programmable logic device and the corresponding static storage, the image compression module comprises a digital signal processor for preliminary treatment, small wave conversion, entropy encoding, rate control and packing with the corresponding synchronous dynamic memory, and the data transmission module comprises a main controller and a general purpose serial controller. The invention realizes visualized control for rate flow with the transmission velocity of flow compression as high as 480Mbps.
Description
Technical field
The invention belongs to image-processing system, the embedded still image compressibility that particularly multiple function is integrated.
Background technology
Along with the extensive use of multimedia technology, still image compression standard JPEG 2000 of new generation is arisen at the historic moment, to satisfy the user to high compression efficiency more with to the requirement of the interactive and scalability of compressed image.
" more high compression ratio, more high image quality, lower code check " is the summary to the JPEG2000 fundamental characteristics, in addition JPEG2000 also provides a cover new feature, as progressive transmission, the special processing of area-of-interest etc., these features are extremely important for some new products (as digital camera) and application (as the Internet).In addition, be similar to the first international still image compression standard JPEG of cover and its motion jpeg (MJPEG, Motion JPEG), JPEG2000 also has the corresponding with it video encoding and decoding standard MJPEG2000 (Motion JPEG2000) that is used for image sequence, it has not only continued to use the various superior functions of JPEG2000, also it is successfully applied to moving image.Table 1 realizes that from application, range of code rates, editability, measurability, rest image pattern, lossless compress pattern, compression efficiency, software and hardware the several aspects of complexity contrast several video compression algorithms commonly used respectively.The unique advantage that can more clearly find out JPEG2000/MJPEG2000 thus and had.
Table 1 video compression algorithm performance commonly used relatively
| Compression algorithm | Application | The video code rate scope | Editability | Measurability | The rest image pattern | The lossless compress pattern | Compression efficiency | The software and hardware implementation complexity | |
| /Mbps | /fps | ||||||||
| ???MPEG-1 | VCD makes | 1.0～1.5 | @352×240×29.97 | Difference | Low | Do not have | Do not have | Good | High |
| ???MPEG-2 | The digital television broadcasting of DVD making/SD | 3.0～100 | @720×480×29.97 | Difference | Low | Do not have | Do not have | Good | High |
| ???MPEG-4 | Network Transmission | 0.75～0.25 0.3～1.0 1.2～4.0 | @176×120×29.97 @352×240×29.97 @720×480×29.97 | Difference | High | Do not have | Do not have | Fine | High |
| ???DVC | Professional video production/digital camera | 25.0 | @720×480×29.97 | Good | Low | Have | Do not have | Difference | Low |
| ???MJPEG | Video production | 10.0～80 | @720×480×29.97 | Good | Low | Have | Do not have | Generally | Low |
| ???MJPEG2000 | Professional video production/digital camera/video stream | 2.0～50 | @720×480×29.97 | Good | High | Have | Have | Good | Low |
Above-mentioned several Standard of image compression (removing JPEG2000) all do not provide lossless compress.JPEG also has the geometric algorithm of lossless compress, but its compression ratio is very little, does not have practical value, and the lossless compress ratio of JPEG2000 then can reach 3～5 times.For high-end applications such as medical image and satellite remote sensing images, lossless compress is best compress mode; Need the application of high definition such as the video editing of broadcast level for other, lossless compress also has very big attraction.
The technical advance of JPEG2000, demand specific aim and the application prospect that has guaranteed it in the performance of the excellent in performance of high-end applications, nowadays JPEG2000 has been considered to the desirable image coding solution that the Internet and wireless access are used, all obviously be better than traditional still image compression algorithm in all fields, but also do not obtain in practice to use widely, main cause is: the software of JPEG2000 is realized quite a lot, but it is considerably less that hardware is realized, particularly collect IMAQ, compression, coffret is that the JPEG2000 compression chip/module of one does not also occur, and this commerce that has restricted the JPEG2000 technology is greatly used.
The difficult point that the JPEG2000 hardware algorithm is realized mainly is: algorithm complexity, operand are big.As arithmetic coding is that at present institute is generally the most complicated a kind of in the entropy coding algorithm of employing; Wavelet transform (DWT) is at the entire image zone, it as resolution 720 * 576 image, the data space that the simple component storage needs is the 414.720K word, owing to carry out deinterleaving to entire image behind the first order DWT, so the maximum interim memory space that also needs the 414.720K word; Adopt the hardware language programming to have certain difficulty, relate to 32 floating number divisions as Rate Control " optimum rate distortion " algorithm partly, and hardware programming language (as ASM) does not provide divide instruction.
The hardware of JPEG2000 technology realizes mainly containing three kinds of main flow schemes at present.
Application-specific integrated circuit (ASIC) (ASIC)+peripheral circuit: the most representative at present is the ADVJP2000 that analogue device (AD) company produces, say that accurately it is a JPEG2000 accelerating engine, can only be used for realizing arithmetic section---wavelet transformation and arithmetic entropy coding in the JPEG2000 application system, that is to say with ADVJP2000 and realize the JPEG2000 system, also need the Video Decoder of design specialized that interface (I is set
2The C bus), video acquisition interface, video cache, nonvolatile storage (FLASH) interface and special-purpose a large amount of peripheral hardware supports such as system control processor, could constitute complete JPEG2000 image encoding kernel.
Field programmable gate array (FPGA) is realized: JPEG2000 itself is a kind of very complicated algorithm, and be that picture in its entirety is handled, need take the memory of enormous amount, this is unfavorable for realizing with FPGA very much, and programming complexity, the construction cycle of FPGA are long in addition, functional verification is complicated, power consumption is big etc. also is the factor of this scheme of restriction.
General dsp (digital signal processor) is realized: the development of dsp chip nowadays is very ripe, high instruction execution speed, low-power consumption, large storage capacity are the developing direction of DSP, and cost is cheap relatively, adopts general dsp to realize having several advantages: the DSP that can select friction speed, memory capacity according to different demands for use; Can finish most of function (as demonstration, network, storage etc.) of JPEG2000 application system; Can easily upgrade to software; Low power consumption can be used for portable equipment.Adopt general dsp to realize that the JPEG2000 technology is a kind of implementation of flexibility, can adapt to the application of various situations by the DSP that selects different class for use, the memory of different capabilities.
Summary of the invention
The present invention proposes a kind of embedded image processor, its objective is to design an expandability high-speed figure image processing platform cheaply on the general dsp platform of high performance-price ratio, adopts general dsp to realize the JPEG2000 technology.
Embedded image processor of the present invention is made up of image capture module, image compression module, data transmission module and four parts of supply module, it is characterized in that:
(1) image capture module comprises Video Decoder, video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM, and Video Decoder is converted to the digital video frequency flow that meets the CCIR656 form with the analog composite video signal of input; The CPLD images acquired, digital video frequency flow is carried out format analysis, corresponding brightness Y, colourity U, saturation V component are stored in the SRAM with 4: 1: 1 form, synchronization a slice SRAM is used to gather video image, and another sheet SRAM is used as the image buffer of DSP.
(2) image compression module is made up of digital signal processor DSP and corresponding synchronous dynamic memory SDRAM, and digital signal processor is responsible for image compression, and the deposit data after the compression is in synchronous dynamic random access memory,
Described digital signal processor comprises preliminary treatment, wavelet transformation, entropy coding, Rate Control and four modules of packing as the JPEG2000 encoder, respectively brightness Y, colourity U, three components of saturation V are carried out level shift, wavelet transformation, entropy coding, the encoding stream of all code blocks that will obtain requires to carry out laminated tissue according to Rate Control then, comprising the code stream break-in operation, the output of encoder promptly is the layering bit stream after the packing, i.e. compression position flow;
(3) data transmission module is made up of master controller Host Controller and general-purpose serial bus USB 2.0 controllers, passes through the HPI interface when powering on to DSP load module code; By the HPI interface compression control parameter is transferred to DSP during work, and reads the DSP compression result by the HPI interface with dma mode and send to main frame according to USB standard packing.
Described embedded image processor, it is further characterized in that in the described digital signal processor:
Described pretreatment module is carried out level shift, does not represent that with the p bit then the sampled value with these no sign component deducts 2 if promptly there is the glyph image component
P-1
Described wavelet transformation module adopts the LeGall5/3 filter to realize getting 1 bank of filters UMDFB Lifting Wavelet algorithm based on taking out 2, and 704 * 576 resolution sampled images carry out 5 grades of wavelet decomposition, and 352 * 288 images carry out 4 grades of wavelet decomposition;
Described entropy coding module adopts the optimum embedded block coding EBCOT+ adaptive bit plane arithmetic encoder that blocks, sub-band division behind the wavelet transformation is become little code block, and the wavelet coefficient in the code block is organized into some bit planes encodes, when carrying out the code block coding, EBCOT further is divided into three coding passes with each bit plane: validity passage, amplitude refinement and removing passage; When carrying out Bit-Plane Encoding, what JPEG2000 adopted is quick self-adapted binary arithmetic coding;
Described Rate Control and packetization module, the compression ratio that configures according to the user, the code block coding stream that behind entropy coding, obtains, according to the rate distortion requirement, intercept into the bit stream segment of different length, point of cut-off and distortion value are kept at together with the code block bit stream with the form of compressing, form the embedded compression position flow of code block.
Described embedded image processor, parallel work-flow by multi-disc DSP, the processing speed of elevator system greatly, adopt two DSP concurrent operations, can satisfy the demand of operand, described video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM can have two covers, two CPLD gather odd-numbered frame and even frame image respectively, every frame comprises odd field and even field, every CPLD carries out format analysis to digital video frequency flow, with corresponding brightness Y, colourity U, saturation V component is stored in the SRAM with 4: 1: 1 form, synchronization a slice SRAM is used to gather video image, and another sheet SRAM is used as the image buffer of DSP;
Image compression module can by two fully independently digital signal processor DSP and corresponding synchronous dynamic memory SDRAM form, be responsible for the compression of odd-numbered frame and even frame image respectively and deposit.
Described embedded image processor, higher if desired processing speed and bigger processing capacity, the quantity of DSP can be increased to 4 processing speeds that improve system, at this moment described video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM can have 4 covers, parallel running; Image compression module can fully independently digital signal processor DSP and corresponding synchronous dynamic memory SDRAM form parallel running by 4.
Described embedded image processor, described video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM can also have 8 covers, parallel running; Image compression module can also fully independently digital signal processor DSP and corresponding synchronous dynamic memory SDRAM form parallel running by 8.
Owing to take above-mentioned technology, JPEG2000 should provide more performance and more function in theory, is verified below by several groups of correction datas.With jpeg algorithm for referencial use is most popular compression algorithm on the current industry hardware platform; The test picture is 24 true color lenna figure.The compression performance tolerance that experiment is adopted is Y-PSNR (PSNR),
Test data (data unit: dB) under the table 2 different target code check
| ???????????4CIF | ???????????CIF | ?????????QCIF | |||||
| ?JPEG2000 | ?JPEG | ?JPE；2000 | ?JPEG | ?JPEG2000 | ?JPEG | ||
| ?1.0bpp | ?R | ?36.60 | ?34.90 | ?33.69 | ?32.67 | ?29.49 | ?28.00 |
| ?G | ?37.12 | ?36.97 | ?34.27 | ?33.84 | ?29.97 | ?28.55 | |
| ?B | ?34.58 | ?32.61 | ?33.12 | ?30.84 | ?29.89 | ?26.91 | |
| ?0.5bpp | ?R | ?34.57 | ?32.92 | ?30.62 | ?27.17 | ?25.88 | ?- |
| ?B | ?34.67 | ?34.05 | ?30.82 | ?27.72 | ?25.77 | ?- | |
| ?G | ?32.68 | ?30.67 | ?30.44 | ?27.48 | ?26.71 | ?- | |
| ?0.25bpp | ?G | ?32.40 | ?28.45 | ?27.88 | ?25.20 | ?- | ?- |
| ?B | ?32.15 | ?29.34 | ?27.36 | ?25.60 | ?- | ?- | |
| ?R | ?30.98 | ?26.54 | ?27.92 | ?25.31 | ?- | ?- | |
| ?0.125bpp | ?R | ?30.14 | ?22.28 | ?25.30 | ?21.43 | ?- | ?- |
| ?G | ?29.58 | ?23.41 | ?24.85 | ?21.95 | ?- | ?- | |
| ?B | ?29.06 | ?20.30 | ?25.66 | ?19.61 | ?- | ?- | |
Can be drawn to draw a conclusion by the data in the table 2: under higher compression ratio situation, the signal to noise ratio of JPEG2000 all exceeds JPEG6～9dB; Under high definition case, the snr value decline degree of JPEG2000 is lower than code check decline degree, this means that resolution is high more, can embody the high compression ratio performance of JPEG2000 more; When signal to noise ratio is lower than 26dB, the restructuring graph of JPEG since serious " mosaic " effect can't differentiate, though and this moment the JPEG2000 reconstructed image lost at detail section, image outline is still distincter."-" expression picture quality this moment is very low in the table, and the PSNR value of calculating no longer has practical significance.
PSNR reflection be the statistical average of signal noise ratio (snr) of image situation of change, though it is the method for the measurement image subjective quality of present extensive use, do not have general correlation with the subjective vision characteristic of human eye.Therefore, we have also carried out subjective vision relatively to several representational pictures (personage's picture, scenery picture, document picture).
System compresses speed under three kinds of resolution situations of table 3
| Resolution | ????QCIF(177 ????×144) | ????CIF(352 ????×288) | ????4CIF(704 ????×576) |
| Compression speed | 80 frame/seconds | 30 frame/seconds | 10 frame/seconds |
In sum, advance of the present invention be embodied in following some:
(1) image compression algorithm of the present invention's employing has been avoided the common disadvantage based on the image compression algorithm of dct transform based on wavelet transformation: compression ratio blocking artifact can occur when surpassing certain limit; Compression ratio is controlled by quantization parameter, and the user is difficult to visual control.
(2) image compression algorithm has adopted the brand-new scheme of EBCOT+ adaptive arithmetic code device.The code efficiency of this scheme has improved 10% than Huffman encoding efficient, has solved the requirement of " support of many distortion factors " simultaneously.
(3) the JPEG2000 compression algorithm adopts the scheme that collects fully, has brought into play the efficient of C6713 to greatest extent, and is limited and emphasize that under the situation of efficient, the advantage of assembler language is fully manifested at the native system memory headroom.
(4) interfacing is the present invention's another important technology except that Image Compression, is directly connected to the operating efficiency of this embedded system as input equipment.2.0 interfaces of the USB with 480Mbps transmission rate that adopt, the fluency of mass data exchange also has plug and play and hot swap characteristics easily when not only having guaranteed the high speed image compression, has powerful extensibility.
JPEG2000 has incomparable advantage in the video editing field, compares based on the video editing system of DV technology with existing, and the present invention has following characteristics:
(1) provide the lossless compress function, compression ratio reaches 3～5 times;
(2) provide and diminish compression function, for higher resolution image (as 4CIF), even the compression ratio that adopted 100: 1 also can obtain good reconstructed image quality, and exhausted nothing " blocking artifact ", these characteristics can require the memory space of system to reduce by 30～60%;
(3) provide the rest image pattern, but all arbitrary accesses of every frame just are easy to editor with a non-linear editor;
(4) code check is controlled, based on the band-limited Channel Transmission view data of wireless network or other time, utilizes this characteristics, the user can be as required and bandwidth, the quality of decision download images quality, thus limited bandwidth is saved, made full use of to the size of control data amount.
The present invention has realized high-quality image compression function with low cost, has application fields, for example: digital camera; High bit-error environment (as radio communication and internet); Be used for the high quality digital video record that specialty broadcasting and film are transcribed; High-resolution medical image or satellite remote sensing images; Handheld device (as mobile phone or PDA); Electronics movie theatre etc.
Description of drawings
Fig. 1 is a kind of execution mode of hardware configuration of the present invention;
Fig. 2 is a flow chart of data processing of the present invention;
Fig. 3 is that digital signal processor of the present invention is as the JPEG2000 encoder block diagram.
Embodiment
Fig. 1 is a kind of execution mode of hardware configuration of the present invention; Video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM have two covers, two CPLD gather odd-numbered frame respectively and even frame image, synchronization a slice SRAM are used to gather video image, and another sheet SRAM is used as the image buffer of DSP; Image compression module by two fully independently digital signal processor DSP and corresponding synchronous dynamic memory SDRAM form, be responsible for the compression of odd-numbered frame and even frame image respectively and deposit.Adopt two DSP concurrent operations, can satisfy the demand of operand.
Can select following chip for use according to design object:
● image processor is selected the high performance-price ratio Floating-point DSP-TMS320C6713 of TI company for use, selects the PQFP encapsulation simultaneously for use, effectively reduces system cost.The monolithic peak value processing speed of C6713 by the multi-disc parallel processing, satisfies the demand that high-speed data is handled up to 1600MIPS fully;
● select the interface of the conduct of CY7C68013 USB2.0 controller with the upper host data exchange of Cypress company for use, under low cost, realized exchanges data at a high speed;
● select for use the up-to-date MAX3000 series low-cost and high-performance CPLD (CPLD) of altera corp as the video image acquisition controller, directly the video flowing of CCIR656 standard is decomposed into the raw video image of depositing with 4: 1: 1 forms, reduces the task amount of image processing DSP;
● communication controler is selected the high cost performance DSP-TMS320VC5402 of TI for use, reading images processing DSP compression result, and be sent to main frame according to the usb protocol packing data.Also be responsible for the load module code simultaneously to each sheet C6713 inside.
● Video Decoder is selected the SAA7111AHZ high-performance decoders of Philiphs company for use, has the input of 4 road analog video composite signals, and can directly connect the input of YC component;
The SDRAM of every DSP expansion 16MB, SDRAM satisfy the requirement of mass data exchange in the image compression process with the frequency work of 100MHz.
Supply module:
Because the most of module of system is to exceed the high speed operation of 100MHz, power supply quality directly influences the stability of a system, except the generality to power filtering capacitor requires, and the labor of system's power demands, as table 4:
Table 4 system power demands
| Chip | 3.3V power supply (mA) | 1.2V/1.8V power supply (mA) | ||
| Mean value | Maximum | Mean value | Maximum | |
| ????TMS320C6713 | ????75 | ????565 | ||
| ????TMS320VC5402 | ????30 | ????45 | ||
| ????CY7C68013 | ????128 | ????260 | ||
| ????HY57V281620 | ????40 | ????220 | ||
| ????IS61LV5128AL | ????45 | ????90 | ||
| ????EPM3256 | ????90 | ????120 | ||
| ????SAA7111 | ????112 | ????122 | ||
According to above-mentioned analysis, the power supply of entire circuit plate is divided into 5 independently modules: 2 1.2V supply modules; 2 3.3V supply modules of 1 1.8V supply module.
The 1.2V power supply that C6713 uses obtains by linear transformation from the 5.0V power supply, and the about 2147mW of power supply power consumption needs finned, and two C6713 use two independently 1.2V power modules;
The 1.8V power supply that VC5402 uses obtains the about 144mW of power supply power consumption by linear transformation from the 5.0V power supply;
3.3V obtain by linear transformation from the 5.0V power supply, wherein two C6713, two SDRAM, CY7C68013 and the shared 3.3V power supply of VC5402, the about 660mW of power supply power consumption, two EPM7256,4 SRAM and the shared 3.3V power supply of SAA7111, the about 490mW of power supply power consumption.
The design object of native system is not a portable system, is design object with the system stability, can all adopt linear power supply, guarantees high-quality power supply.
Vision signal export from analog input to the JPEG2000 data flow experience flow process as shown in Figure 2.
The analog video signal of input forms the CCIR656 digital video frequency flow of standard through decoder, by the logical process of CPLD, this data flow is divided into odd-numbered frame image and even frame image, and two DSP are responsible for handling odd-numbered frame image and even frame image respectively; JPEG2000 deposit data after the compression is in the inner particular buffer of DSP, and Host reads by the mode of HPI interface with DMA.
In IMAQ and DSP processing procedure, used " table tennis " buffering area, as buffering area A (BufferA) when being used to gather video image, buffering area B (BufferB) is directly connected on the bus of DSP and carries out image compression, when in like manner BufferB is used to gather video image, BufferA is directly connected on the bus of DSP and carries out image compression, and whether this process does not need the intervention of DSP substantially, only need the collection of DSP query image to finish.
JPEG2000 data after the image compression are directly read after treatment by dma mode by Host and deliver to PC by USB, and this process does not need the intervention of DSP fully.
Adopt the data flow of last figure, can make the DSP that is responsible for Video processing bring into play its handling property to greatest extent, be responsible for the supply of data and read by peripheral circuit system, and avoided expensive FIFO (pushup storage) or DPSRAM (dual-ported memory), adopted low-cost design to realize high performance.
JPEG2000 encoder among the present invention as shown in Figure 3.
Pretreatment module comprises level shift, does not represent that with the p bit then the sampled value with these no sign component deducts 2 if promptly there is the glyph image component
P-1Its objective is in order when decoding, can from the numerical value that symbol is arranged, correctly to recover the no symbol sampler value of reconstruct.
The operand of traditional wavelet is quite big, and often 8 view data is transformed to floating type, in coding, introduce quantizing distortion, be unfavorable for the lossless compress of view data, so JPEG2000 mainly adopts the Lifting Wavelet algorithm based on UMDFB (take out 2 and get 1 bank of filters).Its advantage is that the memory space that speed is fast, computational complexity is low, required is few, and wavelet coefficient that obtains and coming to the same thing that the use traditional wavelet obtains.Through substantive test, JPEG2000 selects two kinds of filters for use: LeGall5/3 filter and Daubechies9/7 filter.The former can satisfy the integer type bank of filters that diminishes the lossless compress demand simultaneously, and the latter is the floating type bank of filters with higher lossy compression method performance.The relative 5/3 small echo computing complexity of 9/7 small echo, 4 times " lifting " and 2 " change yardstick " computings need have been carried out, and 5/3 small echo only need carry out 2 times " lifting " and can finish, and native system considers that real-time requires and the lossless compress demand, selects 5/3 small echo computing for use.The energy of decomposition coefficient is more concentrated when wavelet decomposition progression improves, but the raising of wavelet decomposition progression can make code efficiency descend to some extent, for native system, 4CIF (704 * 576) resolution sampled images carries out 5 grades of wavelet decomposition, and it is just enough that CIF (352 * 288) image carries out 4 grades of wavelet decomposition.
The multiresolution support can realize that the support of many distortion factors then can solve by entropy coding by wavelet transformation.The entropy coding module has adopted EBCOT (Embedded Block Coding withOptimized Truncation, the embedded block coding that optimum blocks)+scheme of MQ encoder (adaptive bit plane arithmetic encoder), and non-traditional JPEG Huffman encoding mode commonly used.Huffman encoding takes successively each coefficient to be carried out the mode of entropy coding; The JPEG2000 coded system then is that the sub-band division behind the wavelet transformation is become little code block, and the wavelet coefficient in the code block is organized into some bit planes encodes.With " bit plane " is coding unit, 2 benefits is arranged: can utilize the statistical property of image local better, provide support for obtaining the image compression bit stream at random; Help to improve the error-resilient performance of compressed bit stream.When carrying out the code block coding, JPEG2000 emphasizes the support of many point of cut-offs, and many more point of cut-offs show that image can provide more quality to select.If each code block is only carried out Bit-Plane Encoding, be the piece of N for data highest order number so, can obtain N point of cut-off at most.Many times this block be coarse and also the point of cut-off number very few.In order to obtain more point of cut-off, EBCOT introduces the notion of " coding pass ", and each bit plane further is divided into sub-bit plane (coding pass).In the JPEG2000 coded system, use three coding passes: validity passage, amplitude refinement and removing passage.Concerning certain code block Bi, possible point of cut-off can have 3N like this.When carrying out Bit-Plane Encoding, what JPEG2000 adopted is quick self-adapted binary arithmetic coding.Adaptive arithmetic code is that with the different of Huffman encoding maximum it is not that each signal is produced a code value, but a burst is produced a code value; It also will obtain the wherein prediction probability of each signal except needs picked up signal sequence.According to this probability, [0,1] interval constantly to be cut apart, the code value that obtains at last promptly is to cut apart the pairing binary representation in the minizone that obtains at last.The acquisition of adaptivity is to bring in constant renewal in the prediction probability of signal, makes it always to level off to reality.
Code check user controllable function of the present invention is mainly partly realized in Rate Control and packetization module.The compression ratio that configures according to the user, the code block coding stream that behind entropy coding, obtains,, intercept into the bit stream segment of different length according to certain rate distortion requirement, point of cut-off and distortion value are kept at together with the code block bit stream with the form of compressing, form the embedded compression position flow of code block.After multilevel wavelet decomposed, code stream had gradability on spatial resolution.In order to make compressed bit stream have qualitative gradability, the JPEG2000 standard is to the code block bit stream after encoding, adopt PCRD (Post-compression Rate-distortion Optimization, optimum rate distortion) algorithm thought, calculate the point of cut-off of code block bit stream on each layer.All code block bit streams according to point of cut-off laminated tissue, are formed the compressed bit stream with different quality level.The embedded compression position flow of code block is distributed on the different layers, and different code blocks has different contributions to different layers, even same code block, to different layers, contribution also may be different, the code block that has even to the basic just not contribution of certain one deck.With code stream laminated tissue, each layer contains certain quality information, on Ceng the basis, improves picture quality in front.Like this, when carrying out the image transmission, can transmit ground floor earlier, give thicker image of user, and then transmit the second layer, picture quality improves on the basis of ground floor, and transmission is gone down so layer by layer, can obtain the reconstructed image of different quality.If transmitted all layers, then can obtain complete image compression bit stream.
Claims (5)
1. an embedded image processor is made up of image capture module, image compression module, data transmission module and four parts of supply module, it is characterized in that:
(1) image capture module comprises Video Decoder, video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM, and Video Decoder is converted to the digital video frequency flow that meets the CCIR656 form with the analog composite video signal of input; The CPLD images acquired, digital video frequency flow is carried out format analysis, corresponding brightness Y, colourity U, saturation V component are stored in the SRAM with 4: 1: 1 form, synchronization a slice SRAM is used to gather video image, and another sheet SRAM is used as the image buffer of DSP.
(2) image compression module is made up of digital signal processor DSP and corresponding synchronous dynamic memory SDRAM, and digital signal processor is responsible for image compression, and the deposit data after the compression is in synchronous dynamic random access memory,
Described digital signal processor comprises preliminary treatment, wavelet transformation, entropy coding, Rate Control and four modules of packing as the JPEG2000 encoder, respectively brightness Y, colourity U, three components of saturation V are carried out level shift, wavelet transformation, entropy coding, the encoding stream of all code blocks that will obtain requires to carry out laminated tissue according to Rate Control then, comprising the code stream break-in operation, the output of encoder promptly is the layering bit stream after the packing, i.e. compression position flow;
(3) data transmission module is made up of master controller Host Controller and general-purpose serial bus USB 2.O controller, passes through the HPI interface when powering on to DSP load module code; By the HPI interface compression control parameter is transferred to DSP during work, and reads the DSP compression result by the HPI interface with dma mode and send to main frame according to USB standard packing.
2. embedded image processor as claimed in claim 1 is characterized in that in the described digital signal processor:
Described pretreatment module is carried out level shift, does not represent that with the p bit then the sampled value with these no sign component deducts 2 if promptly there is the glyph image component
P-1
Described wavelet transformation module adopts the LeGall5/3 filter to realize getting 1 bank of filters UMDFB Lifting Wavelet algorithm based on taking out 2, and 704 * 576 resolution sampled images carry out 5 grades of wavelet decomposition, and 352 * 288 images carry out 4 grades of wavelet decomposition;
Described entropy coding module adopts the optimum embedded block coding EBCOT+ adaptive bit plane arithmetic encoder that blocks, sub-band division behind the wavelet transformation is become little code block, and the wavelet coefficient in the code block is organized into some bit planes encodes, when carrying out the code block coding, EBCOT further is divided into three coding passes with each bit plane: validity passage, amplitude refinement and removing passage; When carrying out Bit-Plane Encoding, what JPEG2000 adopted is quick self-adapted binary arithmetic coding;
Described Rate Control and packetization module, the compression ratio that configures according to the user, the code block coding stream that behind entropy coding, obtains, according to the rate distortion requirement, intercept into the bit stream segment of different length, point of cut-off and distortion value are kept at together with the code block bit stream with the form of compressing, form the embedded compression position flow of code block.
3. embedded image processor as claimed in claim 1 or 2 is characterized in that:
Described video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM have two covers, two CPLD gather odd-numbered frame respectively and even frame image, every frame comprise odd field and even field, every CPLD carries out format analysis to digital video frequency flow, corresponding brightness Y, colourity U, saturation V component are stored in the SRAM with 4: 1: 1 form, synchronization a slice SRAM is used to gather video image, and another sheet SRAM is used as the image buffer of DSP;
Image compression module by two fully independently digital signal processor DSP and corresponding synchronous dynamic memory SDRAM form, be responsible for the compression of odd-numbered frame and even frame image respectively and deposit.
4. embedded image processor as claimed in claim 1 or 2 is characterized in that:
Described video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM have 4 covers, parallel running; Fully independently digital signal processor DSP and corresponding synchronous dynamic memory SDRAM form parallel running to image compression module by 4.
5. embedded image processor as claimed in claim 1 or 2 is characterized in that:
Described video acquisition programmable logic device (CPLD) and its corresponding two static memory SRAM have 8 covers, parallel running; Fully independently digital signal processor DSP and corresponding synchronous dynamic memory SDRAM form parallel running to image compression module by 8.
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