CN1308814C - Micro processing system for recording system program into main storage and recording method - Google Patents
Micro processing system for recording system program into main storage and recording method Download PDFInfo
- Publication number
- CN1308814C CN1308814C CNB031090494A CN03109049A CN1308814C CN 1308814 C CN1308814 C CN 1308814C CN B031090494 A CNB031090494 A CN B031090494A CN 03109049 A CN03109049 A CN 03109049A CN 1308814 C CN1308814 C CN 1308814C
- Authority
- CN
- China
- Prior art keywords
- primary memory
- control signal
- processor
- current potential
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Stored Programmes (AREA)
- Memory System (AREA)
Abstract
The present invention provides a microprocessing system and a recording method for recording a system program to a main memory by using a pluggable and extractable subsystem, wherein the system program is mainly recorded on the main memory by using a standby memory positioned on the pluggable and extractable subsystem by the microprocessing system. Whether information accessed by a processor is derived from the standby memory or the main memory is determined by a device which occupies two units of adjustment potential for information on a bus bar.
Description
Technical field
The present invention relates to a kind of microprocessing systems and carving method that system program is burnt to primary memory.
Background technology
Some microprocessor system is owing to use or development the program of necessary replacing system.Early stage program storage element because easily plug can take off it, after the service routine Writing device writes program then, is put back in the original system again and is got final product.But because the component package development of technology, some program storage element has been not suitable for often doing the action of plug.So this system just must provide the method for system program self.But it but has potential risks, is exactly the system program when write error, might cause system to start.Just must provide a kind of method this moment, can make system more again the update system program then when starting shooting next time, can allow system's normal operation at original program storage element.
The microprocessor running must have the program storage element that its operation procedure is provided.But the program of program storage element can't make system start-up, how to do the action of program updates again.Have only and use another program storage element just can make system start-up, if but original program storage element does not take off, though its data are incorrect, but under not special control, its procedure code still can be delivered to the data channel of system, conflicts and cause with procedure code that another program storage element is sent.Its result still can't make system start-up.
Summary of the invention
Technical matters to be solved by this invention is, the many shortcomings that produced at traditional microprocessor operation system, propose a kind of system program to be burnt to the microprocessing systems and the carving method of primary memory, under normal circumstances allow system use the running of main program storer.When system's main program storer is written into erroneous procedures when causing system can't normal operation to start, can use boostrap memory conversion, make system need not dismantle startup running under the main program storer, and with the correct program main program storer of writing system again, make its next time in no boostrap memory situation, but still normal operation.
The main program storer that another object of the present invention is to system can utilize the mode that can plug subcard that the program correction and the renewal of main program storer are returned in the self procedure failure.
A further object of the present invention is in the process of a large amount of production systems, if when detecting system mistake, can directly system do not revised when product is also gone public.Finished when product but,, also can utilize the mode that can plug subcard that problematic part of system or chip are found out if there is problem in the system that detects in the unlisted stage.
Another purpose of the present invention is in the process of manufacturing system not consider earlier whether the program of primary memory is correct, Yi Bian carry out the production of system, carries out primary memory procedure development and correction simultaneously.For present manufacturing industry, many production times can be saved significantly.
The invention provides and a kind of system program is burnt to the microprocessing systems of primary memory, comprise:
One processor, in order to send one first control signal and one second control signal, wherein said first control signal is a floating potential;
One primary memory electrically is connected to processor and receives one the 3rd control signal, whether transmits information with processor with decision;
One in order to be adjusted to the first current potential device, electrically is connected to processor, to receive first control signal and electrically to be connected to primary memory, makes that the 3rd control signal is first current potential, and this first current potential makes primary memory move; And
One has a plugged subsystem that is equipped with source memory, electrically is connected to processor, and receives second control signal;
When second control signal is first current potential, is equipped with the source memory action and is equipped with transmission information between source memory and the processor; And can plug subsystem and send one the 4th control signal, make that the 3rd control signal is one second current potential; Wherein, second current potential makes primary memory stop action, when second control signal is second current potential, be equipped with source memory and stop action, and stop to plug subsystem and send the 4th control signal, make that the 3rd control signal is first current potential, and transmission information between primary memory and the processor.
Described second current potential is higher than first current potential.
Described in order to be adjusted to first resistance that the first current potential device comprises a ground connection.
The method of transmitting signal between described primary memory and the processor comprises:
Between primary memory and processor, set up one first bus and one second bus, wherein, have address date above first bus, and have the storage data above second bus; And
Primary memory receive one read signal after, the storage data of corresponding address data are sent to processor by second bus.
The method of transmitting signal between described primary memory and the processor also comprises:
After primary memory receives a write signal, the storage data of corresponding address data are written to primary memory by second bus.
The described method that is equipped with the information that transmits between source memory and the processor is:
Setting up first bus and second bus between source memory and the processor fully, wherein, have address date above first bus, and have the storage data above second bus; And
After signal is read in source memory reception one fully, transmit the storage data that correspond to address date and arrive processor.
The described subsystem that plugs has:
A connector is in order to electrically to be connected to processor and primary memory;
One is equipped with source memory, electrically is connected to connector to receive second control signal; In order to be adjusted to the second current potential device, electrically be connected to connector, and send the 4th control signal, by connector to adjust the current potential of the 3rd control signal.
Describedly comprise second resistance that is connected to a power supply in order to be adjusted to the second current potential device.
Described connector is a slot apparatus.
Described primary memory is a non-volatility memorizer.
The present invention also provides a kind of method that system program is burnt to the primary memory of a microprocessing systems, wherein this microprocessing systems comprises: a processor, primary memory, in order to be adjusted to one first current potential device, and has a plugged subsystem that is equipped with source memory, first current potential can allow primary memory move, wherein
Processor transmits one first control signal adjusting a current potential of the 3rd control signal in order to the control primary memory, and transmits one second control signal to plugging subsystem, and wherein first control signal is a floating potential; Second control signal is first current potential, makes to plug the subsystem action; And the 3rd control signal be by being controlled to first current potential in order to be adjusted to the first current potential device;
Can plug subsystem and send one the 4th control signal, the 3rd control signal is adjusted to one second current potential, wherein second current potential is forbidden the primary memory action;
Be equipped with transmission information between source memory and the processor;
Processor transmits second control signal to plugging subsystem, and wherein second control signal is second current potential, makes that can plug subsystem stops action, and stops to send the 4th control signal; And
Transmission information between primary memory and processor.
Described second current potential is higher than first current potential.
Described in order to be adjusted to first resistance that the first current potential device comprises a ground connection.
The described method of transmitting signal between source memory and the processor that is equipped with is:
Setting up one first bus and one second bus between source memory and the processor fully, wherein have address date above first bus, and have the storage data above second bus; And
After signal is read in source memory reception one fully, the storage data that correspond to address date are sent to processor.
The method of transmitting signal between described primary memory and the processor comprises:
Between primary memory and processor, set up first bus and second bus, wherein have address date above first bus, and have the storage data above second bus; And
After signal is read in primary memory reception one, the storage data that correspond to address date are sent to processor by second bus.
The method of transmitting signal between described primary memory and the processor also comprises:
After primary memory receives a write signal, the storage data that correspond to address date are written to primary memory by second bus.
The described subsystem that plugs has:
A connector is used for electrically being connected to processor and primary memory;
One is equipped with source memory, electrically is connected to connector to receive second control signal;
In order to be adjusted to the second current potential device, electrically be connected to connector, and send the 4th control signal, by connector to adjust the current potential of the 3rd control signal.
Describedly comprise second resistance that is connected to a power supply in order to be adjusted to the second current potential device.
Described connector is a slot apparatus.
Described primary memory is a non-volatility memorizer.
The invention provides a kind of use one pluggable subsystem system program is burnt to the microprocessing systems of primary memory, comprise a processor, a primary memory, have a plugged subsystem that is equipped with source memory in order to be adjusted to the first current potential device and.Described processor, in order to send one first control signal and one second control signal, wherein first control signal is a floating potential.Described primary memory electrically is connected to processor, and receives one the 3rd control signal, whether transmits information with processor with decision.Described in order to be adjusted to the first current potential device, electrically be connected to processor receiving first control signal, and electrically be connected to primary memory, make that the 3rd control signal is first current potential, wherein first current potential can allow the primary memory action.Described have a plugged subsystem that is equipped with source memory, electrically is connected to processor and receives second control signal.
When second control signal is this first current potential, be equipped with the source memory action and be equipped with transmission information between source memory and the processor, and can plug subsystem and send one the 4th control signal, make that the 3rd control signal is one second current potential, wherein second current potential makes primary memory stop action.When second control signal is second current potential, be equipped with source memory and stop action, and stop to plug subsystem and send the 4th control signal, make that the 3rd control signal is first current potential, and transmission information between primary memory and the processor.
The present invention provides a kind of method that system program is burnt to the primary memory of a microprocessing systems simultaneously, wherein this microprocessing systems comprise a processor, primary memory, in order to be adjusted to one first current potential device and to have a plugged subsystem that is equipped with source memory, wherein first current potential can allow the primary memory action.Method of the present invention comprises from processor and transmits one first control signal, adjusting a current potential in order to the 3rd control signal of control primary memory, and transmits one second control signal to plugging subsystem; Wherein, first control signal is a floating potential, and second control signal is first current potential, makes to plug the subsystem action; And the 3rd control signal be by being controlled to first current potential in order to be adjusted to the first current potential device.Afterwards, can plug subsystem and send one the 4th control signal, the 3rd control signal is adjusted to one second current potential, wherein second current potential is forbidden the primary memory action.Then, be equipped with transmission information between source memory and the processor.Then, transmit second control signal to plugging subsystem from processor; Wherein second control signal is second current potential, makes pluggable subsystem stop action, and stops to send the 4th control signal.Afterwards, transmission information between primary memory and processor.
The invention has the advantages that:
The primary memory that is applied to system can utilize the mode that can plug subcard that the program correction and the renewal of primary memory are returned in the self procedure failure;
In addition, the present invention on can being applied to the primary memory that upgrades failure, for the factory that a large amount of manufacturings are produced, also be quite easily.Because in the process of a large amount of production systems, if when detecting mistake, can be when product not also be gone public just the utilization mode that can plug subcard the problematic part of system or chip found out directly revised.
Even, in the process of manufacturing system, can not consider earlier whether the program of primary memory is correct, on one side can carry out the production of system, carry out primary memory procedure development and correction simultaneously.For present manufacturing industry, many production times can be saved significantly.
Description of drawings
Fig. 1 shows the structural representation of microprocessing systems of the present invention;
Fig. 2 shows the structural representation that can plug subsystem;
Fig. 3 shows and reads and write in the flow process between each element data and signal flow to concerning synoptic diagram between primary memory and the processor;
Fig. 4 shows the data read between primary memory and the processor and writes process flow diagram;
Fig. 5 shows and can plug the data read between subsystem and the processor and to write in the flow process of primary memory between each element data and signal flow to concerning synoptic diagram; And
Fig. 6 shows data read that can plug between subsystem and the processor and the process flow diagram that writes primary memory.
Embodiment
The present invention mainly provides a kind of use one pluggable subsystem system program is burnt to the microprocessing systems of primary memory, comprises: a processor, a primary memory, have a plugged subsystem that is equipped with source memory in order to be adjusted to the first current potential device and.
Described processor, in order to send one first control signal and one second control signal, wherein first control signal is a floating potential.Primary memory is a non-volatility memorizer, is electrically to be connected to processor, and receives that one the 3rd control signal determines whether and processor transmits information.Describedly comprise first resistance of a ground connection, electrically be connected to processor in order to be adjusted to the first current potential device, receiving first control signal, and electrically be connected to primary memory, make that the 3rd control signal is first current potential, wherein first current potential is an electronegative potential, can allow primary memory move.Described have a plugged subsystem that is equipped with source memory, electrically is connected to processor and receives second control signal.
When second control signal is first current potential, be equipped with the source memory action, and be equipped with transmission information between source memory and the processor, and can plug subsystem and send one the 4th control signal, make that the 3rd control signal is one second current potential, wherein second current potential is noble potential and is higher than first current potential, can be so that primary memory stops action.
The method of transmitting signal between primary memory and the processor comprises: set up one first bus and one second bus between primary memory and processor, wherein has address date above first bus, and have the storage data above second bus, and primary memory receive one read signal after, the storage data that correspond to described address date are sent to processor by second bus.The method of transmitting signal between primary memory and the processor also comprises: after primary memory receives a write signal, the storage data of corresponding address data are written to primary memory by second bus.
The described method of transmitting signal between source memory and the processor that is equipped with is: setting up first bus and second bus between source memory and the processor fully, wherein has address date above first bus, and have the storage data above second bus, and be equipped with source memory receive one read signal after, the storage data of corresponding address data are sent to processor.
When second control signal is second current potential, be equipped with source memory and stop action and stop to plug subsystem sending described the 4th control signal, make that the 3rd control signal is to be able to transmission information between first current potential and primary memory and the processor.
The described subsystem that plugs has a connector, and one is equipped with source memory, and in order to be adjusted to the second current potential device.Described connector is in order to electrically to be connected to processor and primary memory; Be equipped with source memory, electrically be connected to connector to receive second control signal; In order to be adjusted to the second current potential device, electrically be connected to connector, and send the 4th control signal, to adjust the current potential of the 3rd control signal by connector.Describedly comprise second resistance that is connected to a power supply in order to be adjusted to the second current potential device.In addition, connector is a slot apparatus.
The present invention provides a kind of method that system program is burnt to the primary memory of a microprocessing systems simultaneously, wherein microprocessing systems comprise a processor, primary memory, in order to be adjusted to one first current potential device and to have a plugged subsystem that is equipped with source memory, wherein first current potential is an electronegative potential, can allow primary memory move.Primary memory is a non-volatility memorizer.In order to be adjusted to first resistance that the first current potential device comprises a ground connection.Method of the present invention comprises: transmit one first control signal from processor, to adjust a current potential of the 3rd control signal in order to the control primary memory; And transmit one second control signal to plugging subsystem; Wherein first control signal is a floating potential; Second control signal is first current potential, makes to plug the subsystem action; And the 3rd control signal is to be controlled to first current potential by described in order to be adjusted to the first current potential device.Afterwards, can plug subsystem and send one the 4th control signal, the 3rd control signal is adjusted to one second current potential, wherein second current potential is noble potential and is higher than first current potential, is to forbid the primary memory action.Then, be equipped with transmission information between source memory and the processor.Then, transmit second control signal to plugging subsystem from processor, wherein second control signal is second current potential, makes that can plug subsystem stops action and stop to send the 4th control signal.Afterwards, transmission information between primary memory and processor.
The described method of transmitting signal between source memory and the processor that is equipped with comprises: setting up one first bus and one second bus between source memory and the processor fully, wherein have address date above first bus, and have the storage data above second bus.Afterwards, be equipped with source memory receive one read signal after, the storage data of corresponding address data are sent to processor.
The method of transmitting signal between described primary memory and the processor comprises: set up first bus and second bus between primary memory and processor, wherein have address date above first bus, and have the storage data above second bus.Then, after signal was read in primary memory reception one, the storage data that will correspond to address date by second bus were sent to processor.The method of transmitting signal between primary memory and the processor also comprises: after primary memory receives a write signal, the storage data of corresponding address data are write primary memory by second bus.
The described subsystem that plugs has a connector, and one is equipped with source memory, and in order to be adjusted to the second current potential device.Described connector is in order to electrically to be connected to processor and primary memory; Be equipped with source memory and electrically be connected to connector, to receive second control signal; Describedly electrically be connected to connector, and send the 4th control signal, to adjust the current potential of the 3rd control signal by connector in order to be adjusted to the second current potential device.Comprise second resistance that is connected to a power supply in order to be adjusted to the second current potential device.In addition, connector is a slot apparatus.
Next, the embodiment that a use can plug the microprocessing systems of subsystem RW system program is described according to the present invention.As shown in Figure 1, a microprocessing systems 100 has comprised processor 101, and primary memory 102 is adjusted to electronegative potential device 103, and a pluggable subsystem 110.Processor 101 can sent two signals earlier at first, is respectively the plugged subsystem controls signal 126 of ternary output control signal 127 and take-off potential electronegative potential.Ternary output control signal 127 is used for controlling the current potential that primary memory is selected control signal 125, and primary memory selection control signal 125 is to be used for controlling reading and writing of primary memory 102.Can plug subsystem controls signal 126 and be and be used for control and can plug subsystem 110 and whether move.This processor 101 can be applied in the system that generally needs processor, for example digital video/use CD (digital video/versatile disc more; DVD) player.Processor 101 can be according to program implementation, and the order that the program of sending is carried out is to above the address bus 121, obtain the procedure code of sending from primary memory 102 sending to understand after reading signal 123 on data bus 122 then.Processor 101 can be to see off decoding and carry out desired action of procedure code.Also can carry out the action of program updates in some cases to primary memory 102.For example in DVD player, processor 101 can read the program that desire is upgraded from discs, and processor 101 will write the action of data to upgrade to primary memory 102 according to the program of refresh routine then.But the work that will carry out of guard system 100 is not why, and the condition an of necessity is exactly in system's 100 starts, and the program of primary memory 102 must be in the correct system that is loaded into 100.Just can't allow system's regular event if leave the program of primary memory 102 originally in, it may have no idea to allow the more new element of system's 100 executive routines.
The purpose that is adjusted to electronegative potential device 103 is to select the current potential of control signal 125 to pull to first current potential, just electronegative potential primary memory.A kind of simple practising way is to use the general resistance of a ground connection, or is called the resistance that pulls to ground.Because the three-state output control signal 127 of processor 101 outputs is a kind of input signals, its current potential is a floating potential.Its current potential is unknown state for primary memory 102.In order to allow processor 101 can allow primary memory 102 action, utilized the electronegative potential device 103 that is adjusted to that current potential is pulled to electronegative potential to make primary memory 102 actions.
As shown in Figure 2, can plug subsystem 110 and comprise that a connector 112, is equipped with source memory 114, and be adjusted to noble potential device 116.General plugged subsystem 110 can be made the form of subcard, utilizes an inserting slot construction electrically to be connected with system 100.Connector 112 is mainly used to be connected processor 101 and the transmission of the signal between the source memory 114 fully, and wherein signal comprises address bus 121, and data bus 122 reads signal 123, and can plug subsystem controls signal 126.In addition, connector 112 has also connected the signal that is adjusted to noble potential device 116 and is adjusted between the electronegative potential device 103 to be transmitted, and mainly is to select control signals 125 to close primary memory 102 from being adjusted to noble potential device 116 adjustment primary memorys noble potential control signal 128.General connector 112 can use inserting slot construction.
Being equipped with source memory 114, being called boostrap memory or auxiliary system program storing memory again, is general program storage unit.The general source memory 114 that is equipped with also is to use non-volatile memory element, and data can and then not disappear when power supply disappears.But it is not as the system program storer, can not carry out the action of self.Be equipped with source memory 114 receptions one control that can plug subsystem controls signal 126 and determine whether action.When plugging subsystem controls signal 126 is when being in electronegative potential, is equipped with source memory 114 and is activated, thereby wholely plug the state that subsystem 110 is in action.When the current potential that can plug subsystem controls signal 126 is noble potential, be equipped with that source memory 114 is closed and the whole subsystem 110 that plugs is failure to actuate.
The purpose that is adjusted to noble potential device 116 is to select the current potential of control signal 125 to pull to second current potential, just noble potential primary memory.A kind of simple practising way is to use an abundant resistance that connects power supply, or is called the drawing resistance that connects power supply.Because system 100 has and is adjusted to electronegative potential device 103 and primary memory can be selected the current potential of control signal 125 pull to electronegative potential, so primary memory selects the current potential of control signal 125 to be not equal to the noble potential control signal.Primary memory selects the current potential of control signal 125 can only make its partial pressure value near two drawing resistance.If pulling to the resistance value on ground is R1, the drawing resistance value of receiving power supply is R2, and then that the voltage of primary memory selection control signal 125 is the R1/ (R1+R2) of supply voltage.The ratio of R1 and R2 is done suitable adjustment, can make system 100 after connecting pluggable subsystem 110, make primary memory selection control signal 125 disengaging electronegative potentials and forbid primary memory 102 runnings.
System 100 does not need to add to plug subsystem 110, and its structural representation as shown in Figure 3.Total system 100 has only three elements in action, and only carries out the transmission of data between two buses between two elements.The program execution flow of system as shown in Figure 4 at this moment.In system's 100 starts, shown in the first step of Fig. 4, processor 101 transmits two control signals and comes out, and is respectively that output potential is float the three-state output control signal 127 of formula unit and the plugged subsystem selection control signal 126 that initial state is electronegative potential.Because pluggable subsystem 110 is not installed in the system 100, the primary memory of electronegative potential selects control signal 126 not have an effect.The three-state output control signal 127 of floating potential can be adjusted to electronegative potential device 103 and pull to electronegative potential, is that electronegative potential is to start primary memory 102 so primary memory is selected control signal 125.Then, shown in second step of Fig. 4, processor 101 can be in OPADD value on the address bus 121 to primary memory 102.Afterwards, shown in the third step of Fig. 4, the address value on the primary memory 102 decipher address buss 121.Then, processor 101 can determine it is need from 102 fetch programs of primary memory or writing data into primary memory 102 carries out self.Shown in the 4th step of Fig. 4, primary memory 102 receives from processor 101 and reads signal 123 or write signal 124.Then, when primary memory 102 receives when reading signal 123, the data that correspond to address value can be delivered to data bus 122 and give processor 101; Or when primary memory 102 is received write signal 124, the data on the data bus 122 are write the data area of the corresponding address value of primary memory 102.The data read of primary memory 102 or the action that writes have been finished in top action basically.
When the program of primary memory 102 goes wrong and can not start shooting, at this moment can plug subsystem 110 to be installed in the system 100, at this moment system's 100 structural representations as shown in Figure 5, and the program execution flow of system 100 is as shown in Figure 6.When system 100 started, shown in Fig. 6 first step, the first unlatching of meeting can plug subsystem 110 and stop the action of primary memory 102.The processing mode of this step is that processor 101 can be sent two signals earlier, is respectively that output potential is that the three-state output control signal 127 of floating potential is the plugged subsystem controls signal 126 of electronegative potential with initial state.Because pluggable subsystem 110 has been installed in the system 100, the plugged subsystem controls signal 126 of electronegative potential can start source memory 114 fully, can send current potential that a high potential signal 128 adjusts primary memory control signal 125 to noble potential and at this moment be adjusted to noble potential device 116, so primary memory 102 just can not move.Afterwards, shown in Fig. 6 second step, processor 101 is from pluggable 110 last fetch program of subsystem data.Detailed steps is processor 101 process connectors 112 and has set up address bus 121 between the source memory 114 fully, and processor 101 is delivered to address value on the address bus 121.Be equipped with source memory 114 after address bus 121 reads address value and decoding, processor 101 is sent and is read after the signal 123 by the time, and the data that correspond on the address value are delivered on the data bus 122.Processor 101 can be with data read on the data bus 122 and decoding.This is to have finished processor 101 and be equipped with data read between the source memory 114.Because being equipped with source memory 114 can not self-program updates, so the streams data direction on the data bus 122 has only from being equipped with source memory 114 to processor 101.
Afterwards, might need to write data on the primary memory 102, shown in Fig. 6 third step, can plug subsystem 110 and close and open primary memory 102.This step mainly is to send the plugged subsystem controls signal 126 of a noble potential from processor 101, is equipped with source memory 114 this moment and can stops action and be adjusted to noble potential device 116 and also stop to send high potential signal 128 simultaneously.At this moment only be adjusted to electronegative potential device 103 and control 125 one-tenth electronegative potentials of primary memory control signal fully.Therefore, can plug that subsystem 110 can be closed and be equipped with source memory 114 and and then begin action.Then, shown in Fig. 6 the 4th step, data are written to the primary memory 102 from processor 101.In this step, after primary memory 102 actions, set up address bus 121 and data bus 122 between meeting and the processor 101, wherein processor 101 can be sent address value earlier on address bus 121.Address value on primary memory 102 receptions and the decode address bus 121 waits for receiving after the write signal 124 that the data that processor 101 can be placed on the data bus 122 are put into the zone that corresponds on the address value, finish the action that writes.The primary memory 102 that therefore, can't act on has finished the self program now.Afterwards, can plug subsystem 110 and remove, starting shooting again, whether normal operation gets final product checking system 100.
In addition, when certain chip of microprocessing systems 100 or install problematic the time, also can utilize to plug subsystem 110 and look for problematic chip or device.For example, when system 100 can't start shooting and problem when going out program at hardware rather than primary memory 102, installation can plug subsystem 110.At this moment can go to read the information that can plug subsystem 110 in the time of system's 100 starts, and be equipped with the information that source memory 114 can be designed to issue start process.For example, a kind of mode is when start, and when running into certain chip problem being arranged, system utilizes luminous signal to send flash signal or utilizes buzzer call one long which chip of untill further notice user to belong to undesired.Whether design different notification signals and correspond to different chips, it is normal when start to detect a plurality of chips simultaneously.This debug mode is easily suitable in systemic debug.
Even the present invention describes by enumerating several preferred embodiments, but the present invention is not limited to the embodiment that enumerated.Though the specific embodiment of before enumerating and narrating, apparently, other does not break away under the disclosed spirit, and the equivalence of being finished changes or modifies, and all should be included in the claim scope of the present invention.In addition, all other do not break away under the disclosed spirit, and other that finished are similar and approximate to be changed or modification, also all is included in the claim scope of the present invention.Should explain scope of the present invention with the widest definition simultaneously, use and comprise all modifications and similar approach.
Claims (20)
1, a kind of system program is burnt to the microprocessing systems of primary memory, it is characterized in that comprising:
One processor, in order to send one first control signal and one second control signal, wherein said first control signal is a floating potential, and described first control signal is converted to the 3rd control signal through one in order to be adjusted to the first current potential device, in order to the control primary memory;
One primary memory electrically is connected to processor and receives the 3rd control signal, whether transmits information with processor with decision;
One in order to be adjusted to the first current potential device, electrically is connected to processor, to receive described first control signal; And electrically be connected to described primary memory, and making that described the 3rd control signal is first current potential, this first current potential makes described primary memory move; And
One has a plugged subsystem that is equipped with source memory, electrically is connected to processor and receives described second control signal;
When described second control signal is first current potential, described be equipped with the source memory action and and processor between transmission information, and the described subsystem that plugs is sent one the 4th control signal, make that described the 3rd control signal is second current potential, wherein this second current potential makes primary memory stop action; When described second control signal was second current potential, the described source memory that is equipped with stopped action and stops the described subsystem that plugs sending the 4th control signal, makes that the 3rd control signal is first current potential, and transmission information between described primary memory and the processor.
2, according to claim 1 system program is burnt to the microprocessing systems of primary memory, it is characterized in that: described second current potential is higher than first current potential.
3, according to claim 1 system program is burnt to the microprocessing systems of primary memory, it is characterized in that: described in order to be adjusted to first resistance that the first current potential device comprises a ground connection.
4, according to claim 1 system program is burnt to the microprocessing systems of primary memory, it is characterized in that: the method for transmitting signal between described primary memory and the processor comprises:
Between described primary memory and processor, set up one first bus and one second bus, have address date above wherein said first bus, and have the storage data above second bus; And
Described primary memory receive one read signal after, the storage data of the described address date of correspondence are sent to processor by second bus.
5, the microprocessing systems that system program is burnt to primary memory according to claim 4, it is characterized in that: the method for transmitting signal between described primary memory and the processor also comprises: after described primary memory receives a write signal, the storage data of the described address date of correspondence are written to primary memory by second bus.
6, according to claim 1 system program is burnt to the microprocessing systems of primary memory, it is characterized in that: the described method that is equipped with the information that transmits between source memory and the processor is:
Set up first bus and second bus in described being equipped with between source memory and the processor, have address date above wherein said first bus, and have the storage data above second bus; And
Described be equipped with source memory receive one read signal after, the storage data of the described address date of correspondence are sent to processor.
7, according to claim 1 system program is burnt to the microprocessing systems of primary memory, it is characterized in that: the described subsystem that plugs has:
A connector is in order to electrically to be connected to described processor and primary memory;
One is equipped with source memory, electrically is connected to described connector to receive second control signal; And
In order to be adjusted to the second current potential device, electrically be connected to described connector, and send described the 4th control signal, by described connector to adjust the current potential of the 3rd control signal.
8, according to claim 7 system program is burnt to the microprocessing systems of primary memory, it is characterized in that: describedly comprise second resistance that is connected to a power supply in order to be adjusted to the second current potential device.
9, according to claim 7 system program is burnt to the microprocessing systems of primary memory, it is characterized in that: described connector is a slot apparatus.
10, according to claim 1 system program is burnt to the microprocessing systems of primary memory, it is characterized in that: described primary memory is a non-volatility memorizer.
11, a kind of method that system program is burnt to the primary memory of a microprocessing systems, wherein this microprocessing systems comprises: a processor, a primary memory, in order to be adjusted to one first current potential device and to have a plugged subsystem that is equipped with source memory, described first current potential can make the primary memory action, it is characterized in that comprising:
Described processor transmits one first control signal, is converted to the 3rd control signal through the described first current potential device that is adjusted to, with the control primary memory; And transmit one second control signal to pluggable subsystem; Wherein, described first control signal is a floating potential; When second control signal is first current potential, make pluggable subsystem action; And the 3rd control signal be by being controlled to first current potential in order to be adjusted to the first current potential device;
The described subsystem that plugs is sent one the 4th control signal, and the 3rd control signal is adjusted to one second current potential, and wherein second current potential is forbidden the primary memory action;
Transmission information between described source memory fully and processor;
Described processor transmits second control signal to plugging subsystem, and wherein second control signal is second current potential, makes that can plug subsystem stops action, and stops to send the 4th control signal; And
Transmission information between described primary memory and processor.
12, according to claim 11 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: described second current potential is higher than this first current potential.
13, according to claim 11 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: described in order to be adjusted to first resistance that the first current potential device comprises a ground connection.
14, according to claim 11 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: the described method of transmitting signal between source memory and the processor that is equipped with is:
Setting up one first bus and one second bus between source memory and the processor fully, wherein have address date above first bus, and have the storage data above second bus; And
Described be equipped with source memory receive one read signal after, the storage data of the described address date of correspondence are sent to processor.
15, according to claim 11 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: the method for transmitting signal between described primary memory and the processor comprises:
Between primary memory and processor, set up first bus and second bus, wherein have address date above first bus, and have the storage data above second bus; And
After signal is read in described primary memory reception one, the storage data that correspond to described address date are sent to processor by second bus.
16, according to claim 15 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: the method for transmitting signal between described primary memory and the processor also comprises:
After described primary memory receives a write signal, the storage data that correspond to described address date are written to primary memory by second bus.
17, according to claim 11 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: the described subsystem that plugs has:
A connector is in order to electrically to be connected to processor and primary memory;
One is equipped with source memory, electrically is connected to connector to receive second control signal;
In order to be adjusted to the second current potential device, electrically be connected to connector, and send the 4th control signal, by connector to adjust the current potential of the 3rd control signal.
18, according to claim 17 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: describedly comprise second resistance that is connected to a power supply in order to be adjusted to the second current potential device.
19, according to claim 17 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: described connector is a slot apparatus.
20, according to claim 11 system program is burnt to the method for the primary memory of a microprocessing systems, it is characterized in that: described primary memory is a non-volatility memorizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031090494A CN1308814C (en) | 2003-04-02 | 2003-04-02 | Micro processing system for recording system program into main storage and recording method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031090494A CN1308814C (en) | 2003-04-02 | 2003-04-02 | Micro processing system for recording system program into main storage and recording method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1534459A CN1534459A (en) | 2004-10-06 |
| CN1308814C true CN1308814C (en) | 2007-04-04 |
Family
ID=34283250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031090494A Expired - Fee Related CN1308814C (en) | 2003-04-02 | 2003-04-02 | Micro processing system for recording system program into main storage and recording method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1308814C (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1403923A (en) * | 2002-10-21 | 2003-03-19 | 威盛电子股份有限公司 | DRAM data maintaining method and relative device |
| CN2625965Y (en) * | 2003-04-23 | 2004-07-14 | 其乐达科技股份有限公司 | Microprocessing unit with system program recorded to main memory by use of hot swap sub system |
-
2003
- 2003-04-02 CN CNB031090494A patent/CN1308814C/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1403923A (en) * | 2002-10-21 | 2003-03-19 | 威盛电子股份有限公司 | DRAM data maintaining method and relative device |
| CN2625965Y (en) * | 2003-04-23 | 2004-07-14 | 其乐达科技股份有限公司 | Microprocessing unit with system program recorded to main memory by use of hot swap sub system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1534459A (en) | 2004-10-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| USRE40325E1 (en) | Device and method for repeatedly updating the function of a monitor | |
| JP5559778B2 (en) | High-speed and low-power data reading in flash memory | |
| US20090248965A1 (en) | Hybrid flash memory device and method of controlling the same | |
| US20130293559A1 (en) | Method for setting panel parameter and associated controller | |
| CN101437110B (en) | Method, apparatus for controlling start-up picture display mode and video player | |
| CN114860279B (en) | Rapid empty-chip upgrading method | |
| US10387361B2 (en) | Serial device with configuration mode for changing device behavior | |
| US20130067142A1 (en) | Flash memory storage device and method of judging problem storage regions thereof | |
| CN101075213A (en) | ROM data patch circuit, embedded system including the same and method of patching rom data | |
| US7404026B2 (en) | Multi media card with high storage capacity | |
| CN1308814C (en) | Micro processing system for recording system program into main storage and recording method | |
| CN1340770A (en) | Multi-media module card, equipment for its operation and integrated multi-media system | |
| CN2625965Y (en) | Microprocessing unit with system program recorded to main memory by use of hot swap sub system | |
| CN101060014A (en) | A method and device for detecting the physical parameters of flash memory | |
| CN201869296U (en) | Television | |
| CN103716688A (en) | Information reporting method and device in television shutdown abnormality | |
| CN101047029A (en) | Semiconductor memory and data sending/receiving system | |
| CN101354653A (en) | Method and system for automatically mounting driver of hardware apparatus | |
| US20120166717A1 (en) | Data Storage Device and Operation Method Thereof | |
| CN112988465A (en) | Method for automatically recovering operation of single chip microcomputer in upgrading failure | |
| CN1886771A (en) | Display apparatus and a method of controlling the same | |
| US20040255178A1 (en) | Micro-system for burn-in system program from a plug-able subsystem into main memory and method thereof | |
| KR100748509B1 (en) | Display identification data managing method and update apparatus thereof | |
| US20060176741A1 (en) | Method and apparatus for driving flash memory | |
| CN1873621A (en) | Method and relevant apparatus for providing secondary basic input/output system code through synchronizing monitor and control |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: NOVATEK TECHNOLOGY CO. Free format text: FORMER OWNER: JILEDA SCI-TECH CO., LTD. Effective date: 20081024 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20081024 Address after: Hsinchu Science Industrial Park, Taiwan Patentee after: Lianyong Science and Tech. Co., Ltd. Address before: Hsinchu Science Industrial Park, Taiwan Patentee before: Qileda Science and Technology Co., Ltd. |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070404 Termination date: 20140402 |