CN2625965Y - Microprocessing unit with system program recorded to main memory by use of hot swap sub system - Google Patents
Microprocessing unit with system program recorded to main memory by use of hot swap sub system Download PDFInfo
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- CN2625965Y CN2625965Y CN 03241594 CN03241594U CN2625965Y CN 2625965 Y CN2625965 Y CN 2625965Y CN 03241594 CN03241594 CN 03241594 CN 03241594 U CN03241594 U CN 03241594U CN 2625965 Y CN2625965 Y CN 2625965Y
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Abstract
The utility model provides a micro processing unit with a system program recorded to a main memory by use of a hot swap sub system; wherein, the micro processing unit is mainly used for recording the system program of a backup memory on the hot swap sub system to the main memory; wherein, the data on a collecting bar determines that the data that the processor accesses comes from the backup memory or the main memory by depending upon two devices adjusting the level.
Description
Technical field
The utility model relates to a kind of usefulness can plug the micro treatmenting device that subsystem is burnt to system program primary memory.
Background technology
Some microprocessor system is owing to use or development the program of necessary replacing system.Early stage program storage element because easily plug can take off it, after the service routine burning device writes program then, is put back in the original system again and is got final product.But because the component package development of technology, some program storage element has been not suitable for often doing the action of plug.So this system just must provide the method for system program self.But it but has potential risks, is exactly the system program when write error, might cause system to start.Just must provide a kind of method this moment, can make system more again the update system program then when starting shooting next time, can allow system's normal operation at original program storage element.
The microprocessor running must have the program storage element that its operation procedure is provided.But the program of program storage element can't make system start-up, how to do the action of program updates again.Have only and use another program storage element just can make system start-up, if but original program storage element does not take off, though its data is incorrect, but under not special control, its procedure code still can be delivered to the data channel of system, conflicts and cause with procedure code that another program storage element is sent.Its result still can't make system start-up.
Summary of the invention
Technical problem to be solved in the utility model is, the many shortcomings that produced at traditional microprocessor operation system, can plug subsystem system program is burnt to the micro treatmenting device of primary memory and propose a kind of usefulness, under normal circumstances allow system use the running of main program storer.When system's main program storer, be written into erroneous procedures when causing system can't normal operation to start, can use boostrap memory conversion, make system need not dismantle startup running under the main program storer, and with the correct program main program storer of writing system again, make its next time in no boostrap memory situation, but still normal operation.
Another purpose of the present utility model is that the main program storer of system can utilize the mode that can plug subcard that the program correction and the renewal of main program storer are returned in the self procedure failure.
A purpose more of the present utility model is in the process of a large amount of production systems, if can directly system not revised when product is also gone public when detecting system mistake.But finished also in the unlisted stage when product,, and can utilize the mode that can plug subcard that problematic part of system or chip are found out if there is problem in the system of detecting.
Another purpose of the present utility model is in the process of manufacturing system not consider earlier whether the program of primary memory is correct, Yi Bian carry out the production of system, carries out primary memory procedure development and correction simultaneously.For present manufacturing industry, many production times can be saved significantly.
Above-mentioned purpose of the present utility model is realized by following technical scheme.
A kind of usefulness can plug subsystem system program is burnt to the micro treatmenting device of primary memory, it is characterized in that comprising:
One processor is in order to sending one first controlling signal and one second controlling signal, and wherein this first controlling signal is the suspension joint type current potential;
One primary memory is electrically to be connected to this processor and to receive one the 3rd controlling signal to determine whether transmitting information with this processor;
One in order to be adjusted to the first current potential device, is electrically to be connected to this processor to make the 3rd controlling signal be this first current potential to accept this first controlling signal and electrically to be connected to this primary memory, and this first current potential makes this primary memory move; And
One has a plugged subsystem that is equipped with source memory, be electrically to be connected to this processor and to receive this second controlling signal, when this second controlling signal is this first current potential, should be equipped with the source memory action and should be equipped with between source memory and this processor and transmit information.And this can plug subsystem and send one the 4th controlling signal and make that the 3rd controlling signal is one second current potential, wherein this second current potential makes this primary memory stop action, when this second controlling signal is this second current potential, should be equipped with source memory stops action and stops this can plugging subsystem and sending the 4th controlling signal, make the 3rd controlling signal be this first current potential, and transmit information between this primary memory and this processor.
This micro treatmenting device, except that above-mentioned essential features, in specific implementation process, also can replenish following technology contents:
Above-mentioned this second current potential is higher than this first current potential.
Above-mentioned in order to be adjusted to first resistance that this first current potential device comprises a ground connection.
Set up one first bus-bar and one second bus-bar between this primary memory and this processor, wherein this has the address data above first bus-bar, and this has data on file above second bus-bar; And
After this primary memory receives a reading signal, will be sent to this processor via this second bus-bar to this data on file that should the address data.
This primary memory receive one write signal after, will be written to this primary memory via this second bus-bar to this data on file that should the address data.
Be equipped with at this and set up this first bus-bar and this second bus-bar between source memory and this processor, wherein this has the address data above first bus-bar, and this has data on file above second bus-bar; And
Transmission corresponded to this data on file of this address data to this processor after source memory received a reading signal fully.
Above-mentioned plugged subsystem has:
A connector is in order to electrically to be connected to this processor and this primary memory;
One to be equipped with source memory be electrically to be connected to this connector to receive this second controlling signal; And
In order to be adjusted to this second current potential device is electrically to be connected to this connector, and send the 4th controlling signal via this connector to adjust the current potential of the 3rd controlling signal.
Above-mentioned comprise second resistance that is connected to a power supply in order to be adjusted to this second current potential device.
Above-mentioned connector is a slot apparatus.
Above-mentioned primary memory is a non-volatility memorizer.
The utility model provides a kind of use one pluggable subsystem that system program is burnt to the micro treatmenting device of primary memory, comprises a processor, a primary memory, has a plugged subsystem that is equipped with source memory in order to the first current potential device of regulating and.Above-mentioned processor is in order to sending one first controlling signal and one second controlling signal, and wherein this first controlling signal is the suspension joint type current potential.Above-mentioned primary memory is electrically to be connected to this processor and to receive one the 3rd controlling signal to determine whether transmitting information with this processor.Above-mentioned in order to be adjusted to the first current potential device, to be electrically to be connected to this processor to make the 3rd controlling signal be this first current potential to accept this first controlling signal and electrically to be connected to this primary memory, wherein this first current potential can allow this primary memory action.Above-mentioned have a plugged subsystem that is equipped with source memory, is electrically to be connected to this processor and to receive this second controlling signal.
When this second controlling signal is this first current potential, should be equipped with the source memory action and should be equipped with between source memory and this processor and transmit information, and this can plug subsystem and send one the 4th controlling signal and make that the 3rd controlling signal is one second current potential, and wherein this second current potential makes this primary memory stop action.When this second controlling signal is this second current potential, should be equipped with source memory and stop action, and stop this and can plug subsystem and send the 4th controlling signal, make the 3rd controlling signal be this first current potential, and transmit information between this primary memory and this processor.
The micro treatmenting device that system program on the pluggable subsystem is burnt to a primary memory provided by the utility model, wherein this micro treatmenting device comprise a processor, above-mentioned primary memory, in order to be adjusted to one first current potential device and above-mentioned pluggable subsystem, wherein this first current potential can allow this primary memory action.Transmit one first controlling signal from this processor, to adjust a current potential in order to the 3rd controlling signal of controlling this primary memory, and transmit one second controlling signal to this pluggable subsystem, wherein this first controlling signal is a suspension joint type current potential, this second controlling signal is this first current potential, make this pluggable subsystem move, and the 3rd controlling signal is to be controlled to this first current potential by this in order to be adjusted to this first current potential device.Afterwards, above-mentioned pluggable subsystem is sent one the 4th controlling signal the 3rd controlling signal is adjusted to one second current potential, and wherein this second current potential is forbidden this primary memory action.Then, be equipped with between source memory and this processor at this and transmit information.Then, transmit this second controlling signal to this pluggable subsystem from above-mentioned processor, wherein this second controlling signal makes this pluggable subsystem stop action for this second current potential, and stops to send the 4th controlling signal.Afterwards, between this primary memory and this processor, transmit information.
Advantage of the present utility model is:
The utility model mainly is that the primary memory of the system of being applied to can utilize the mode that can plug subcard that the program correction and the renewal of primary memory are returned in the self procedure failure.In addition, the utility model on can being applied to the primary memory that upgrades failure, for the factory that a large amount of manufacturings are produced, also be quite easily.Because in the process of a large amount of production systems, if when detecting mistake, can when also not going public, product utilize the mode that can plug subcard that problematic part of system or chip are found out, directly revise.Even, in the process of manufacturing system, can not consider earlier whether the program of primary memory is correct, on one side can carry out the production of system, carry out primary memory procedure development and correction simultaneously.For present manufacturing industry, many production times can be saved significantly.
For system of the present utility model, method and effect thereof are had further understanding, enumerate specific embodiment now and also be described in detail as follows in conjunction with the accompanying drawings.Yet except describing in detail, the utility model can also be widely implemented with other embodiment, and scope of the present utility model do not limited, and is as the criterion with claims.
Description of drawings
Fig. 1 shows the structural representation of micro treatmenting device of the present utility model.
Fig. 2 shows the structural representation that can plug subsystem.
Fig. 3 shows in the read/write flow process between primary memory and the processor that data and signal flow between each element and concerns synoptic diagram.
Fig. 4 shows each data read/write process flow diagram of primary memory and processor.
The data can plug between subsystem and the processor that shows Fig. 5 reads and writes in the flow process of primary memory that data concerns synoptic diagram with the signal flow direction between each element.And
Fig. 6 shows that the data can plug between subsystem and the processor please get and write the process flow diagram of primary memory.
Fig. 7, Fig. 8 are physical circuit figure of the present utility model.
Embodiment
The utility model mainly provides a kind of use one pluggable subsystem system program is burnt to the micro treatmenting device of primary memory, comprises: a processor, a primary memory, have a plugged subsystem that is equipped with source memory in order to the first current potential device of regulating and.Above-mentioned processor is in order to sending one first controlling signal and one second controlling signal, and wherein first controlling signal is the suspension joint type current potential.Above-mentioned primary memory is a non-volatility memorizer, is electrically to be connected to processor, and receives that one the 3rd controlling signal determines whether and this processor transmits information.The above-mentioned first current potential device in order to regulate, first resistance that comprises a ground connection, be electrically to be connected to this processor, to accept this first controlling signal, and electrically be connected to aforesaid primary memory and make that the 3rd controlling signal is first current potential, wherein first current potential is an electronegative potential, can allow primary memory move.Above-mentioned have a plugged subsystem that is equipped with source memory, is electrically to be connected to processor and to receive second controlling signal.
When second controlling signal is first current potential, should be equipped with the source memory action, and should be equipped with between source memory and the processor and transmit information, and the aforesaid subsystem that plugs is sent one the 4th controlling signal and is made that the 3rd controlling signal is one second current potential, wherein second current potential is noble potential and is higher than first current potential, can be so that primary memory stops action.
The method of transmitting signals is included in and sets up one first bus-bar and one second bus-bar between primary memory and the processor between above-mentioned primary memory and the processor, wherein has the address data above first bus-bar, and have data on file above second bus-bar, and primary memory receives the data on file that will correspond to this address data behind the reading signal and is sent to processor via this second bus-bar.The method of transmitting signals more is included in primary memory and receives a data on file that writes behind the signal corresponding address data and be written to this primary memory via second bus-bar between above-mentioned primary memory and this processor.
The above-mentioned method that is equipped with transmitting signals between source memory and the processor is for setting up aforesaid first bus-bar and aforesaid second bus-bar between source memory and the processor fully, wherein has the address data above first bus-bar, and have data on file above second bus-bar, and source memory transmits the data on file of corresponding address data to processor after receiving a reading signal fully.
When second controlling signal is second current potential, be equipped with source memory and stop action and stop to plug subsystem sending aforesaid the 4th controlling signal, make the 3rd controlling signal be transmitted information between first current potential and primary memory and the processor.
Above-mentioned plugged subsystem has a connector, and one is equipped with source memory, and in order to be adjusted to the aforesaid second current potential device.Above-mentioned connector is in order to electrically to be connected to processor and primary memory.Above-mentioned source memory fully is electrically to be connected to connector to receive second controlling signal.The above-mentioned second current potential device in order to regulate is electrically to be connected to connector, and sends aforesaid the 4th controlling signal to adjust the current potential of the 3rd controlling signal via connector.Above-mentioned comprise second resistance that is connected to a power supply in order to the second current potential device of regulating.In addition, above-mentioned connector is a slot apparatus.
A kind of micro treatmenting device that system program on the pluggable subsystem is burnt to primary memory provided by the utility model, transmit one first controlling signal to adjust a current potential of the 3rd controlling signal in order to the control primary memory from processor, and one second controlling signal to aforesaid pluggable subsystem, wherein first controlling signal is a suspension joint type current potential, second controlling signal is that first current potential makes pluggable subsystem move, and the 3rd controlling signal is to be controlled to first current potential by aforesaid in order to be adjusted to the first current potential device.Afterwards, above-mentioned pluggable subsystem is sent one the 4th controlling signal the 3rd controlling signal is adjusted to one second current potential, and wherein second current potential is noble potential and is higher than first current potential, is to forbid the primary memory action.Then, transmitting information between source memory and this processor fully.Then, transmit second controlling signal to pluggable subsystem from above-mentioned processor, wherein second controlling signal is that second current potential makes pluggable subsystem stop action and stops to send the 4th controlling signal.Afterwards, between primary memory and this processor, transmit information.
The above-mentioned transmission that is equipped with signal between source memory and this processor, be to be equipped with at this to set up one first bus-bar and one second bus-bar between source memory and this processor, wherein have the address data above first bus-bar, and have data on file above second bus-bar.Be equipped with afterwards and transmit the data on file of corresponding address data to processor after source memory receives a reading signal.
The transmission of signal between above-mentioned primary memory and this processor is to set up first bus-bar and second bus-bar between primary memory and processor, wherein has the address data above first bus-bar, and has data on file above second bus-bar.Then, primary memory receives a reading signal after the data on file that will correspond to the address data by second bus-bar is sent to processor.The method of transmitting signals more is included in primary memory and receives a data on file that writes behind the signal corresponding address data and write primary memory via second bus-bar between above-mentioned primary memory and this processor.
Above-mentioned plugged subsystem has a connector, and one is equipped with source memory, and in order to be adjusted to this second current potential device.Above-mentioned connector is in order to electrically to be connected to processor and primary memory.Above-mentioned source memory fully is electrically to be connected to connector to receive second controlling signal.Above-mentioned is electrically to be connected to connector in order to regulate the second current potential device, and sends the 4th controlling signal to adjust the current potential of the 3rd controlling signal via connector.Above-mentioned comprise second resistance that is connected to a power supply in order to regulate the second current potential device.In addition, above-mentioned connector is a plug-in and pull-off device.
Next, be to describe the embodiment that a use can plug the micro treatmenting device of subsystem programming system program according to the utility model.As shown in Figure 1, a micro treatmenting device 100 has comprised processor 101, and primary memory 102 is adjusted to electronegative potential device 103, and a pluggable subsystem 110.Processor 101 can sent two signals earlier at first, be respectively ternary output controlling signal 127 and take-off potential electronegative potential plugged subsystem controls signal 126.Ternary output controlling signal 127 is used for controlling the current potential that primary memory is selected controlling signal 125, and primary memory selection controlling signal 125 is to be used for controlling reading and writing of primary memory 102.Can plug subsystem controls signal 126 and be and be used for control and can plug subsystem 110 and whether move.This processor 101 can be applied in the system that generally needs processor, for example digital video/use CD (digital video/versatile disc more; DVD) player.Processor 101 can be according to program implementation, and the order that the program of sending is carried out can obtain the procedure code of sending from primary memory 102 then to above the address bus-bar 121 on data bus 122 after sending reading signal 123.Processor 101 can be to see off decoding and carry out desired action of procedure code.Also can carry out the action of program updates in some cases to primary memory 102.For example in DVD player, processor 101 can read the program that desire is upgraded from discs, and processor 101 will write the action of data to upgrade to primary memory 102 according to the program of refresh routine then.But the work that will carry out of guard system 100 is not why, and the condition an of necessity is exactly in system's 100 starts, and the program of primary memory 102 must be in the correct system that is loaded into 100.Just can't allow system's regular event if leave the program of primary memory 102 originally in, it may have no idea to allow the more new element of system's 100 executive routines.
The purpose that is adjusted to electronegative potential device 103 is to select the current potential of controlling signal 125 to pull to first current potential, just electronegative potential primary memory.A kind of simple practising way is to use the general resistance of a ground connection, or is called the resistance that pulls to ground.Because the three-state output controlling signal 127 of processor 101 outputs is a kind of input signals, its current potential is the suspension joint type current potential.Its current potential is unknown state for primary memory 102.In order to allow processor 101 can allow primary memory 102 action, utilized the electronegative potential device 103 that is adjusted to that current potential is pulled to electronegative potential to make primary memory 102 actions.
As shown in Figure 2, can plug subsystem 110 and comprise that a connector 112, is equipped with source memory 114, and be adjusted to noble potential device 116.General plugged subsystem 110 can be made the form of subcard, utilizes an inserting slot construction electrically to be connected with system 100.Connector 112 is mainly used to be connected processor 101 and the transmission of the signal between the source memory 114 fully, and wherein signal has comprised address bus 121, data bus 122, and reading signal 123, and can plug subsystem controls signal 126.In addition, connector 112 has also connected the signal that is adjusted to noble potential device 116 and is adjusted between the electronegative potential device 103 to be transmitted, and mainly is to select controlling signal 125 to close primary memory 102 from being adjusted to noble potential device 116 adjustment primary memorys noble potential controlling signal 128.General connector 112 can use inserting slot construction.
Being equipped with source memory 114, being called boostrap memory or auxiliary system program storing memory again, is general program storage unit.The general source memory 114 that is equipped with also is to use non-volatile memory element, and data can and then not disappear when power supply disappears.But it is not as the system program storer, can not carry out the action of self.Be equipped with source memory 114 acceptance one control that can plug subsystem controls signal 126 and determine whether action.When plugging subsystem controls signal 126 is when being in electronegative potential, is equipped with source memory 114 and is activated, thereby wholely plug the state that subsystem 110 is in action.When the current potential that can plug subsystem controls signal 126 is noble potential, be equipped with that source memory 114 is closed and the whole subsystem 110 that plugs is failure to actuate.
The purpose that is adjusted to noble potential device 116 is to select the current potential of controlling signal 125 to pull to second current potential, just noble potential primary memory.A kind of simple practising way is to use an abundant resistance that connects power supply, or is called the drawing resistance that connects power supply.Because system 100 has and is adjusted to electronegative potential device 103 and primary memory can be selected the current potential of controlling signal 125 pull to electronegative potential, so primary memory selects the current potential of controlling signal 125 to be not equal to the noble potential controlling signal.Primary memory selects the current potential of controlling signal 125 can only make its partial pressure value near two drawing resistance.If pulling to the resistance value on ground is R1, the drawing resistance value of receiving power supply is R2, and then that the voltage of primary memory selection controlling signal 125 is the R1/ (R1+R2) of supply voltage.The ratio of R1 and R2 is done suitable adjustment, can make system 100 after connecting pluggable subsystem 110, make primary memory selection control signal 125 disengaging electronegative potentials and forbid primary memory 102 runnings.
When the program of primary memory 102 goes wrong and can not start shooting, at this moment can plug subsystem 110 to be installed in the system 100, system's 100 structural representations at this moment as shown in Figure 5, and the program execution flow of system 100 is as shown in Figure 6.When system 100 started, shown in Fig. 6 first step, the first unlatching of meeting can plug subsystem 110 and stop the action of primary memory 102.The processing mode of this step is that processor 101 can be sent two signals earlier, is respectively that output potential is the three-state output controlling signal 127 of suspension joint type current potential and the primary memory selection controlling signal 126 that initial state is electronegative potential.Because pluggable subsystem 110 has been installed in the system 100, the primary memory of electronegative potential selects controlling signal 126 can start source memory 114 fully, can send current potential that a noble potential signal 128 adjusts primary memory controlling signal 125 to noble potential and at this moment be adjusted to noble potential device 116, so primary memory 102 just can not move.Afterwards, shown in Fig. 6 second step, processor 101 is from pluggable 110 last fetch program of subsystem data.Detailed steps is processor 101 process connectors 112 and has set up address bus 121 between the source memory 114 fully, and processor 101 is delivered to the address value on the address bus 121.Be equipped with source memory 114 after address bus 121 reads address value and decoding, processor 101 is sent the data that will correspond on the address value after the reading signal 123 and is delivered on the data bus 122 by the time.Processor 101 can read the data on the data bus 122 and decode.This is to have finished processor 101 and the data that is equipped with between the source memory 114 reads.Because being equipped with source memory 114 can not self-program updates, so the data flow direction on the data bus 122 has only from being equipped with source memory 114 to processor 101.
Might need afterwards data is written on the primary memory 102, shown in Fig. 6 third step, can plug subsystem 110 and close and open primary memory 102.This step mainly is to send the plugged subsystem controls signal 126 of a noble potential from processor 101, is equipped with source memory 114 this moment and can stops action and be adjusted to noble potential device 116 and also stop to send noble potential signal 128 simultaneously.At this moment only be adjusted to electronegative potential device 103 and control 125 one-tenth electronegative potentials of primary memory controlling signal fully.Therefore, can plug that subsystem 110 can be closed and be equipped with source memory 114 and and then begin action.Then, shown in Fig. 6 the 4th step, data is written to the primary memory 102 from processor 101.In this step, after primary memory 102 actions, set up address bus 121 and data bus 122 between meeting and the processor 101, wherein processor 101 can be sent the address value earlier on address bus 121.Address value on primary memory 102 receptions and the decoding address bus 121 waits for receiving writing after the signal 124 that the data that processor 101 can be placed on the data bus 122 is put into the zone that corresponds on the address value, finishes the action that writes.The primary memory 102 that therefore, can't act on has finished the self program now.Afterwards, can plug subsystem 110 and remove, starting shooting again, whether normal operation gets final product checking system 100.
In addition, when certain chip of micro treatmenting device 100 or install problematic the time, also can utilize to plug subsystem 110 and look for problematic chip or device.For example, when system 100 can't start shooting and problem when going out program at hardware rather than primary memory 102, installation can plug subsystem 110.At this moment can go to read the information that can plug subsystem 110 in the time of system's 100 starts, and be equipped with the information that source memory 114 can be designed to issue start process.For example, a kind of mode is when start, and when running into certain chip problem being arranged, system utilizes luminous signal to send the flicker signal or utilizes buzzer call one long which chip of untill further notice user to belong to undesired.Whether design different notice signals and correspond to different chips, it is normal when start to detect a plurality of chips simultaneously.This debug mode is easily suitable in systemic debug.
Fig. 7 and Fig. 8 are the annexation of circuit diagram of the present utility model and related elements, and wherein can to adopt model be that can to adopt model be that can to adopt model be W27E040 storer (EEPROM) for the source memory 114 that is equipped with in the flash memory (Flash memory), pluggable subsystem 110 of W28J800B for CT9928AF microprocessor, primary memory 102 to processor 101.
The take-off potential that processor 101 is exported controlling signal 127 and EROM-CS by FLASH-CS with three-state is that the plugged subsystem controls signal 126 of low level is sent, wherein ternary output controlling signal 127 is used for controlling the current potential that primary memory is selected controlling signal 125, and primary memory to select controlling signal 125 be to be used for controlling reading and writing of primary memory 102, can plug subsystem controls signal 126 in addition and be to be used for control and can to plug subsystem 110 and whether move.Processor 101 can be according to program implementation, the order that the program of sending is carried out above address bus-bar 121 (SA[8..19]), then send reading signal 123 (/PSEN) can on data bus 122 (AD[0..7]), obtain the procedure code of sending from primary memory 102 afterwards.As shown in Figure 8, can plug subsystem 110 and comprise that a connector 112, is equipped with source memory 114, and be adjusted to noble potential device 116.Can plug subsystem 110 and can make the form of subcard, utilize an inserting slot construction electrically to be connected with system 100.
Connector 112 is mainly used to connection processing device 101 and the transmission of the signal between the source memory 114 fully, wherein signal has comprised address bus 121 (SA[8..19]), data bus 122 (AD[0..7]), reading signal 123 (/PSEN), and can plug subsystem controls signal 126 (EROM CSM).In addition, connector 112 has also connected the signal that is adjusted to noble potential device 116 and is adjusted between the electronegative potential device 103 to be transmitted, and mainly is to select controlling signal 125 to close primary memory 102 from being adjusted to noble potential device 116 adjustment primary memorys noble potential controlling signal 128.General connector 112 can use inserting slot construction.Even the utility model is to describe by enumerating several preferred embodiments, but the utility model is not limited to the embodiment that enumerated.Though the specific embodiment of before having enumerated and having narrated, but apparently, other does not break away under the spirit that the utility model discloses, and the equivalence of being finished changes or modifies, and all should be included in the claim scope of the present utility model.In addition, all other do not break away under the spirit that the utility model discloses, and other that finished are similar and approximate to be changed or modify, and also all is included in the claim scope of the present utility model.Should explain scope of the present utility model with the widest definition simultaneously, use and comprise all modifications and similar approach.
Claims (9)
1, a kind of usefulness can plug subsystem system program is burnt to the micro treatmenting device of primary memory, it is characterized in that comprising:
One processor is in order to sending one first controlling signal and one second controlling signal, and wherein this first controlling signal is the suspension joint type current potential;
One primary memory is electrically to be connected to this processor and to receive one the 3rd controlling signal to determine whether transmitting information with this processor;
One in order to be adjusted to the first current potential device, is electrically to be connected to this processor to make the 3rd controlling signal be this first current potential to accept this first controlling signal and electrically to be connected to this primary memory, and this first current potential makes this primary memory move; And
One has a plugged subsystem that is equipped with source memory, is electrically to be connected to this processor and to receive this second controlling signal;
When this second controlling signal is this first current potential, should be equipped with the source memory action and should be equipped with between source memory and this processor and transmit information, and this can plug subsystem and send one the 4th controlling signal and make that the 3rd controlling signal is second current potential, wherein this second current potential makes this primary memory stop action, when this second controlling signal is this second current potential, should be equipped with source memory stops action and stops this can plugging subsystem and sending the 4th controlling signal, make the 3rd controlling signal be this first current potential, and transmit information between this primary memory and this processor.
2, usefulness according to claim 1 can plug subsystem system program is burnt to the micro treatmenting device of primary memory, and it is characterized in that: above-mentioned this second current potential is higher than this first current potential.
3, usefulness according to claim 1 can plug subsystem system program is burnt to the micro treatmenting device of primary memory, it is characterized in that: above-mentioned in order to be adjusted to first resistance that this first current potential device comprises a ground connection.
4, usefulness according to claim 1 can plug the micro treatmenting device that subsystem is burnt to system program primary memory, it is characterized in that: between this primary memory and this processor, set up one first bus-bar and one second bus-bar, wherein this has the address data above first bus-bar, and this has data on file above second bus-bar; And
After this primary memory receives a reading signal, will be sent to this processor via this second bus-bar to this data on file that should the address data; Or
This primary memory receive one write signal after, will be written to this primary memory via this second bus-bar to this data on file that should the address data.
5, usefulness according to claim 1 can plug the micro treatmenting device that subsystem is burnt to system program primary memory, it is characterized in that: be equipped with at this and set up this first bus-bar and this second bus-bar between source memory and this processor, wherein this has the address data above first bus-bar, and this has data on file above second bus-bar; And
Transmission corresponded to this data on file of this address data to this processor after source memory received a reading signal fully.
6, usefulness according to claim 1 can plug subsystem system program is burnt to the micro treatmenting device of primary memory, and it is characterized in that: above-mentioned plugged subsystem has:
A connector is in order to electrically to be connected to this processor and this primary memory;
One to be equipped with source memory be electrically to be connected to this connector to receive this second controlling signal; And
In order to be adjusted to this second current potential device is electrically to be connected to this connector, and send the 4th controlling signal via this connector to adjust the current potential of the 3rd controlling signal.
7, usefulness according to claim 1 can plug subsystem system program is burnt to the micro treatmenting device of primary memory, it is characterized in that: above-mentioned comprise second resistance that is connected to a power supply in order to be adjusted to this second current potential device.
8, usefulness according to claim 1 can plug subsystem system program is burnt to the micro treatmenting device of primary memory, and it is characterized in that: above-mentioned connector is a slot apparatus.
9, usefulness according to claim 1 can plug subsystem system program is burnt to the micro treatmenting device of primary memory, and it is characterized in that: above-mentioned primary memory is a non-volatility memorizer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03241594 CN2625965Y (en) | 2003-04-23 | 2003-04-23 | Microprocessing unit with system program recorded to main memory by use of hot swap sub system |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 03241594 CN2625965Y (en) | 2003-04-23 | 2003-04-23 | Microprocessing unit with system program recorded to main memory by use of hot swap sub system |
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| CN2625965Y true CN2625965Y (en) | 2004-07-14 |
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| CN 03241594 Expired - Fee Related CN2625965Y (en) | 2003-04-23 | 2003-04-23 | Microprocessing unit with system program recorded to main memory by use of hot swap sub system |
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| Country | Link |
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| CN (1) | CN2625965Y (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1308814C (en) * | 2003-04-02 | 2007-04-04 | 其乐达科技股份有限公司 | Micro processing system for recording system program into main storage and recording method |
-
2003
- 2003-04-23 CN CN 03241594 patent/CN2625965Y/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1308814C (en) * | 2003-04-02 | 2007-04-04 | 其乐达科技股份有限公司 | Micro processing system for recording system program into main storage and recording method |
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