CN1307825C - Environmental simulator for high-speed communicating network - Google Patents

Abstract

The present invention relates to a high-speed network environmental simulator which comprises a microprocessor MCU, a programmable logic device FPGA and a peripheral assembly keyboard, a liquid crystal display screen, a memory, a PC interface and eight communication node interfaces, wherein MCU controls systems, and key assignments is converted to a matrix function to generate matrix control signals, error code selecting signals and speed rate selecting signals. FPGA which realizes the main functions of the simulator is synchronously or asynchronously connected in series with the eight communication node interfaces to process input signals and output signals of FPGA. The matrix control signals from MCU are used for controlling the flow direction of data, and a commuting matrix is formed. Variable channel characteristics are normalized into a plurality of error rates; the error code selecting signals are used for controlling the selection of error codes, loading and compounding, and outputting characteristics of error code flow simulation channels. The communication speed rate selecting signals are used for controlling and generating communication speed rate clock signals and sequence control signals. The present invention provides laboratory simulation environment for communication networks and a testing platform with small size, low cost, and convenient and flexible use for the verification of network communication protocols.

Description

Environmental simulator for high-speed communicating network

Technical field

The invention belongs to network communications technology field, specifically is a kind of environmental simulator for high-speed communicating network, can be the communication network test and verifies that procotol provides the lab simulation environment.

Background technology

Along with the enhancing that people require network service, the research to network service (fixed network, mobile network, Ad-hoc network) in recent years constantly heats up, research talk various network protocols and algorithm.Different with point-to-point communication, network service is that one group of user can interconnect simultaneously.Provide that the facility of interconnection and interflow is abstract to be network environment, as wired switching center or wireless channel.

To the research of large scale network communication is routing algorithm, the network management of the process of a complexity, particularly network, the debugging checking of procotol system, and research work is difficult more when number of users increases.For this reason, must seek effective adjustment method and measure.The basic skills of at present network being studied has three kinds: model analysis, system simulation and actual tests.Wherein, model analysis depends on the support of mathematical tool and modeling method, is used in the theory analysis stage at research initial stage, and result and the reality analyzed often also are that gap is huge.And system simulation is subject to the operation resource, can only simulate the small number of nodes network, because the mutability of annexation between the network communication node is simulated various topological structures, can't accomplish real-time control, so can not see the network data control procedure that flows intuitively.It is directly perceived in good time to rely on the physical channel direct test to accomplish, but its drawback is tangible:

[1] physical channel experimentation cost is very high.Make a mobile radio network operation, need terminal equipment, wireless transmitting-receiving equipments, mobile device, the manpower of maintenance operation.In the actual tests process, the on-the-spot difficulty of revising of pinpointing the problems can only be got back to and indoorly be taken all factors into consideration, and causes frequent upper signal channel test, and this is that the manpower financial capacity can't support.

[2] channel is single.Present homemade twoway radio is single, frequency band limited coverage area (as shortwave, ultrashort wave, microwave etc.), and a cover system can't be verified variety of protocol.

[3] network topology structure is difficult to control.Because radio wave is subjected to the influence in environment and geographical position big, can't accurately control the network topology structure of hope, result of the test has and limitation, and is insufficient to the checking of procotol and control, is difficult to get a desired effect.

In sum,, need a kind of not only economy but also equipment easily, analog wireless communication and the function of network exchange is provided under the baseband transmission environment in the development stage of network service.But also there is not this series products to occur at present as yet, and channel simulator is only arranged.As, " the digitlization real-time radio channel simulator " of the big proposition of the high roc Li Hongniuli of Wang Jun is referring to " Circuits and Systems journal " 2004,9 (2) .-135-137,129; " design of channel simulator and FPGA realize " that Wu state Hangzhoupro Liu Jing great waves propose, referring to " electronics today " 2003, (11) .-20-21,19, generally the channel simulator of being realized by FPGA and DSP mainly is the analog wireless channel characteristic.Its purpose is that the transmission of electric wave causes error condition, so that make the researcher take the EDC error detection and correction measure after simulating be interfered at wireless channel (how the decline of radio wave is through transmission, co-channel interference etc.).It can only provide point-to-point communication, does not have network and function of exchange.

The strong luxuriant proposition of Xu Yubin " the switching network design of radio communication ", referring to " mobile communication " 1997,21 (1) .-19-21, be to utilize MCS-51 series single chip microcomputer technology, realization constitutes the switching matrix network to the control of analog switch array integrated circuit, finish the automatic connection between many telephones and a plurality of wireless channel, finish the automatic connection between a plurality of wireless channels and a plurality of wireless channel.Based on small scale integrated circuit, at have, wireless conversion designs, its function is simple, do not have topological dynamic mapping function; Do not add error code, can't the analog channel characteristic.

Zhao Zhi peak Tian Chang etc. propose " design and the realization of Ad hoc procotol debugging enironment ", see " telecommunications science ", 2001,17 (10) .-12-15, debugging based on the mobility protocol of the multi-hop characteristic of Adhoc network and node proposes, join by a master computer that multi-serial-port card realizes, realize function of exchange, have certain debugging network communication function based on soft algorithm.Operation principle is that the data of a communication node are read in computer from serial ports by byte, is sent to other serial ports again according to network topology structure, realizes the Flow Control of data.Loading error code is to be unit with the byte, adds up with the wrongly written character joint number.There are the following problems and deficiency for this simulator:

[1] the transfer of data time-delay is big, and its real-time is poor.

Communication does not form real time data stream between the node, is not instant transparent.But transmit by main frame, serial ports reads in certain node data, sends to the serial ports that links to each other with another node according to topological structure again, and transfer of data need take the main frame time.If need multi-hop to transmit, time-delay can further enlarge, can't requirement of real time.Serial ports is operated in interrupt mode, and a plurality of serial ports interruption of work, load on host computers is very heavy, must improve main frame to require to strengthen cost.Current computer serial ports speed is up to 115.2kbps, so traffic rate can be very not high, is difficult to satisfy the requirement of Communication Development.

[2] channel error code is to be add rather than the whole bit stream of unit with the data byte, is difficult to true reflection with ginseng channel characteristics, the channel that can't simulate different characteristic.

[3] volume is big, cost is high, do not have the network environment memory function.

Summary of the invention

The technical problem to be solved in the present invention is the deficiency that overcomes prior art, a kind of environmental simulator for high-speed communicating network is provided, various communication channels of simulation and the network exchange function is provided under the baseband transmission environment are for communication network test and checking procotol provide an indoor analog platform.

The high-speed communicating network simulator that technical problem provided that the present invention solves comprises microprocessor MCU, programmable logic device FPGA and peripheral assembly keyboard, LCDs, memory and PC interface, eight communication node interfaces.Described microprocessor MCU gets in touch into complete system by software with above-mentioned device.MCU is a main control singlechip, finishes the control of system, produces the switch matrix control signal, error code selects signal and traffic rate to select signal, and the signal that is produced is transferred to programmable logic device FPGA handles.Described programmable logic device FPGA is used to realize the major function of simulator, receives the matrix control signal of MCU by data/address bus, and is latched in the memory cell; The rate selection and the error rate that receive MCU by control bus are selected control signal; Adopt synchronous serial connection mouth or asynchronous interface to be connected, its input, dateout are handled with eight road communication nodes; Programmable logic device FPGA to the processing of communication node input, dateout comprise to its input synchronously, asynchronous data is handled and output synchronously, asynchronous data handles:

[1] after input data processing FPGA selects synchronous, the asynchronous data that receive, removes asynchronous data start bit and stop bits, become plain streams, produce corresponding bit clock signal simultaneously, together import the error code load-on module with the asynchronous process module; With the synchrodata processing module synchrodata is carried out the bit clock sampling, produce corresponding bit clock signal, realize that input signal and simulator clock signal are synchronous;

[2] dateout is handled under the switch matrix signal controlling, node data converges the signal gathering that module will flow to certain node and becomes one road signal, the asynchronous plain streams of this signal is added start bit and stop bits by data restoring module, is reduced into asynchronous transmission signal format; Synchrodata is directly output then.

According to the present invention, described memory can be stored default 20 cover network environments, and every cover contains the 20 network topo graphs of throwing the net, and the renewal of every topo graph has manual renewal and upgrades dual mode at interval automatically according to setting.

According to the present invention, with key network environment is set and carries out three kinds of selections: promptly read network environment, New-deployed Network environment, recover network environment, network environment parameter and the topo graph selected are shown on liquid crystal display screen, and send programmable logic device FPGA to simulate.

Compared with prior art, the present invention has following advantage:

1. the invention provides the communication network environment of the functions such as forwarding networking, self adaptation route between bit error performance, data collision and the multi-hop terminal of a research channel.Be used under the baseband transmission environment, the analog network topological structure changes and the mobile telecommunication channel feature.Can be in the correctness of indoor checking network communication protocol, and needn't rely on the actual physical channel, do a large amount of field tests, can reduce experimentation cost, shorten the lead time, be the good platform of checking network parameter and performance and procotol.Have simplicity of design, working stability, volume is little, the advantage that cost is low.

2. normalized error rate scheme is supported various channel models, because data show the height of the error rate through the final result with the ginseng Channel Transmission.With containing various channel characteristics on this parameter theory of the error rate, this equipment provides 8 kinds of selections, covers channel characteristics such as wired, wireless, mobile, fixing.The error rate not only reflects channel transmission quality, the near-far interference of also indirect embodiment mobile channel.Therefore, it is very useful loading the default error rate on the transmission path of hope.Be that the test of software emulation and physical channel is beyond one's reach.

3. transfer of data is in real time transparent and support multiple traffic rate, the invention provides the data directly physical channel and the 8 circuit node communication interfaces of exchange, any two inter-node communications be by link connection and do not need main frame to participate in, thereby be real-time.16 kinds of (synchronous 8 kinds, asynchronous 8 kinds) traffic rates can be supported,, just different network environments can be simulated as long as change the traffic rate setting.As the ultra-short wave radio network of the short-wave radio network of low speed, middling speed, at a high speed microwave network and cable network etc., this flexibility makes purposes greatly expand, and is that the actual physics channel is incomparable.

Intelligentized design make topological structure setting, the change convenient, flexible, the LCDs of panel band 320*240 of the present invention and the keyboard of 34 keys, also is furnished with host interface, can break away from/connect main frame network environment and operational factor are set, the connected relation of network can manually change, and also can change automatically; The man-machine interface simple and direct-viewing operation, all network environments and operational factor can directly be keyed in, this just make communication node in the network link connection, change, forwarding relation be provided with very convenient, quick, particularly for comparatively complicated topological structure with 8 nodes, adopting software emulation still is the actual channel test, all be difficult, but come the topological structure of Simulation of Complex just to realize easily with the present invention.The present invention can provide network model accurately, can observe the overall process of TOCOM total communication control in real time intuitively, realizes the function of exchange of aerial data.Have the network environment memory function, can store 20 default cover network environments, can select the default network environment of any cover by button.

5. has expandability, if the multiple devices coupling can enlarge network size.

Description of drawings

Fig. 1 is existing communication network simulator and communication node connection diagram

Fig. 2 is that existing communications network simulator is formed and the interface block diagram

Fig. 3 is a FPGA functional block diagram of the present invention

Fig. 4 is that FPGA is to signal input processing schematic diagram

Fig. 5 is that schematic diagram is handled in the output of FPGA signal

Fig. 6 is that FPGA switch matrix control data flows to schematic diagram

Fig. 7 is that schematic diagram is selected, loaded to the FPGA error code

Fig. 8 is a FPGA clock generating schematic diagram

Fig. 9 is the main control MCU main program flow chart

Figure 10 is a mobile ad-hoc network structural representation of the present invention

Embodiment

The present invention is described in detail with reference to the accompanying drawings.

Referring to Fig. 1, Fig. 2, the present invention adopts microprocessor to add the implementation of programmable logic device on the basis of existing network environment simulator, constitute a network link, make the contact data of respectively communicating by letter according to default topological structure automatic circulation, and do not need main frame to participate in, reach the data in real time transmission.Under the baseband transmission environment, simulate all communication channels at a high speed and the network exchange function is provided.The composition of high-speed communicating network simulator comprises microprocessor MCU, programmable logic device FPGA, peripheral assembly keyboard and LCDs, memory and PC interface and eight communication node interfaces.Microprocessor MCU forms a whole above-mentioned device by software.MCU is a main control singlechip, adopts the W78LE516-44 single-chip microcomputer of Hua Bang company, finishes the control of system.Main control MCU produces the switch matrix control signal, error code is selected control signal and rate selection control signal, gives programmable logic device FPGA with these three kinds of control signals and controls.Main control MCU is described the topology relationship of communication network with matrix function, and by changing the matrix function element value, mapping changes in the connected relation of communication node in the communication network and the network that the connected sum of link disconnects between the node.Suppose that communication environment simulator connecting terminal number is n, the switch matrix function of n * n:

$\begin{array}{ccc}{K}_{\mathrm{ij}}=\[D_{\mathrm{ij}}{\]}_{n\×n}& D_{\mathrm{ij}}\∈\left\{\mathrm{0,1}\right\}& i,j\≤n\left(\text{n=1,2,3.....}\right)\end{array}$

D wherein _IjFor the terminal number of node, work as D _Ij=1 o'clock, node i was communicated with the link of node j, works as D _Ij=0 o'clock, D _iWith D _jLink disconnect.When i=j, D _Ij=0, D _iWith D _jBe same node, promptly any node can not internal loopback.For simplified design, the link that native system is described is two-way, i.e. D _Ij=D _Ji

Matrix function is that MCU produces, and obtains the matrix function element value by the matrix press-key of keyboard, is translated into the matrix switch control signal, and the matrix switch register (topological register) of delivering to FPGA latchs.Switch matrix has 7 * 8=56 switching signal, but under the identical condition of diconnected and the error rate, its receipts, and sending out two switches can a shared control signal, so can realize the network configuration of an appointment with 28 switching signals.The state of each switch is mapped as 28 bit informations by one 1 or 0 expression, sends into the topological register of FPGA.

Programmable logic device FPGA is a core devices of the present invention, is controlled by main control MCU, finishes the major function of network simulator.The EP1C3T144C8 chip that programmable logic device FPGA adopts altera corp to release.Exploitation has used the schematic diagram mode of this chip to import, Verilog HDL imports, the Mixed Design method, make FPGA have latching and controlling of switch matrix signal, the generation of bit synchronous clock signal and control, input, output signal are handled bit error signal generation, selection, value-added tax function.

Referring to Fig. 3, programmable logic device FPGA is connected with MCU with control bus by data/address bus, and is connected in series or asynchronous serial connection synchronously with eight road communication node interfaces employing of simulator.Receive matrix control signal via data/address bus, and be latched in the memory cell of FPGA from main control MCU.Select control signal via the control bus reception from the rate selection and the error rate of main control MCU.Switch controlling signal with the MCU input forms a switching network, and the data-signal of control communication node flows to, thereby realizes the default topological structure and the routing relation of formation; Input, output signal to communication node are handled, and realize the real-time transparent transmission of signal; Select under the signal controlling at error code, select, load error code, export corresponding error code stream; Under the rate selection signal controlling, produce various traffic rate clock signals and required timing control signal.Thus,, constructed the switching network of a transparent real-time Transmission of data, and do not needed main frame to participate in by the FPGA chip piece.

Programmable logic device FPGA is normalized to the error rate with noise, decline, multipath, the interference signal of wireless mobile channel, and common property is given birth to eight kinds of error rates.Loading the different error rates in the communicating pair link arbitrarily, simulate wired, wireless, fixing, mobile various with the ginseng characteristic of channel, so that under the baseband transmission environment, coding, decoding and the error-detection mechanism of transfer of data are verified, observe the control channel transmission quality.The error rate not only reflects channel transmission quality, also embodies the near-far interference of mobile communication indirectly, and it is very useful therefore loading the default error rate on the transmission path of hope.The generting machanism of its error code to a Bit Error Ratio Measurement in the cycle randomness and unexpected error decompose and draw.Concrete reckoning is as follows:

[1] error code models: the error code with the ginseng channel generally includes at random and two types of bursts.Therefore, except an error pattern error code that includes randomness (single error), also should contain continuous a plurality of type error codes (error code continuously) in the error code models greater than 1 mistake.

[2] the Bit Error Ratio Measurement cycle: the period T of the statistics error rate must be much larger than the minimum code element number 1/p that produces this error rate p, i.e. Terror_period=K/p.The K value is selected more than 10 times at least, and certainly K is big more, and confidence level is high more, but when p value hour, timing statistics can be very long.From the confidence level of Bit Error Ratio Measurement with occupy resource comprehensive and consider, set K=50, Terror_period=50/p, promptly the channel error code form is the cycle repetition with T (or 50/p code element).

[3] error code generating algorithm:

Simulate above two class error code forms, K mistake of the sum of the error code in the Bit Error Code Statistics period T is decomposed into repeatedly random and burst error, its decomposition principle is described below:

1. the regulation single error accounts for m, for example gets m=K/2 (integer), other types number of errors sum=K-m.

2. be maximum with (K-m)/2 (rounding), in 2～(K-m)/2 natural numerical value, select numerical value n at random, when

$\underset{i=1}{\overset{\text{l}}{\text{\Σ}}}{n}_i\≤\frac{K-m}{2}$ The time, this n value is the code element number that a time burst error comprised, and continues to select n;

3. work as $K-m>\underset{i=1}{\overset{l}{\mathrm{\Σ}}}{n}_i>\frac{K-m}{2}$ The time, change into $2~(K-\underset{i=1}{\overset{l}{\mathrm{\Σ}}}{n}_i)$ Choose n value next time in the natural number, up to $\underset{i=1}{\overset{l}{\mathrm{\Σ}}}{n}_i=K-m$ Till.

Can obtain like this will producing m single type error code and L secondary burst type error code in the cycle at a T.The error code frequency is m+L, and error code adds up to K.

Algorithm according to error code generates draws eight kinds of error rate distribution patterns 1 * 10 ^-2, 5 * 10 ^-3, 1 * 10 ^-3, 5 * 10 ^-4, 1 * 10 ^-4, 5 * 10 ^-5, 1 * 10 ^-5, no error code, these error rates can contain most of characteristics of channel, comprise wire message way.Various error rate distribution patterns data are solidificated among the RAM of FPGA.If original error-code pattern is all stored, data volume is very big, takies a lot of resources, original error code information must be compressed.According to the algorithm that error code produces, bit-error sequence is made up of Binary Zero, 1 yard, and " 1 " in the sequence represents on this position error code is arranged, and " 0 " represents not have error code on this position.Most of sign indicating number is " 0 " sequence of no error code in the sequence so, and therefore the space of compression is provided.Its compression algorithm is: to continuous in the whole sequence " 1 " and " 0 " counting, the count value sequence is exactly the error code information after the compression.Decompress(ion) is taked following method: in elected during the error code information of a certain error rate correspondence, the error code compressed information of this error rate correspondence is decompressed, recover original error code stream.Decompression process is the inverse operation of compression process.

Referring to Fig. 4, environmental simulator for high-speed communicating network receives the data of each terminal input, sends into programmable logic device FPGA and carries out signal processing.At first FPGA enters input processing module to the synchrodata SRXD1 of input with after asynchronous data ARXD1 carries out alternative, handles respectively.Asynchronous data is removed start bit and stop bits through the asynchronous data extraction module, becomes plain streams, is convenient to load error code.Produce corresponding bit clock signal Aabck1 simultaneously, together be input to the error code load-on module.READY1 signal among the figure is the indication of data ready, is used for the reduction of asynchronous signal.Tributary signal enters the synchrodata processing module synchronously, and the sampling of completion bit clock obtains SRXD11, realizes input signal and simulator synchronization of clock signals.The corresponding bit clock signal Sbck1 that produces.After two paths of signals produces, by the circuit generated data signal RXD11 and the clock signal bck1 of back.This signal is input to matrix control circuit.Have eight tunnel input data processing modules, the input data are handled.

Referring to Fig. 5, the present invention and data input processing module be corresponding the data output processing module, and its effect is that the data that will flow to a certain node merge into one road signal, asynchronous data is added go up start bit and stop bits, is reduced into asynchronous transmission signal format.In the data output processing module, node data converge signal TXD21, TXD31, TXD41, TXD51, TXD61, TXD71 and TXD81 that module will flow to certain node totally seven node datas after matrix switch control convergence flow to the data of node TXD11.The asynchronous data recovery module is added start bit and is closed stop bits on the TXD11 plain streams, add that clock signal of system clk is reduced into asynchronous transmission signal format ATXD1.Synchronizing signal is directly output then.Needing 8 identical dateout processing modules handles dateout.

Referring to Fig. 6, the matrix control module that the signal RXD11 that the present invention handles through input number pick processing module enters FPGA, under matrix signal control, carry out data distribution, divide to RXD12, RXD13, RXD14, RXD15, RXD16, RXD17, seven nodes of RXD18.c _IjBe matrix control signal, the whereabouts of matrix control signal control data signal forms switching network, realizes the function of exchange of aerial data.Have 8 identical matrix control modules, control the data flow of eight communication nodes respectively.

Referring to Fig. 7, error code is selected signal R-SEL[2..0] and error code enable control signal R-EN from MCU, the bit synchronization clock BCLKI (I=1 that provides by input processing module, 2 ... 8) bit error signal is sampled, the right to use must with flow out data sync from switch matrix, common anamorphic zone has the signal TXD1 of error code.Bit error signal has 8 kinds of selections.

Referring to Fig. 8, the clock module of FPGA be used for to input signal synchronously.Though it is at random that each node data sends, enter after the network simulator, synchronous by the clock signal location of simulator with bit error signal, be convenient to exchange and control.Because synchronous transmission is different with asynchronous transmission speed, the input dominant frequency has two kinds, that is: asynchronous clock 11.0592Mhz and synchronised clock 16.384Mhz have selected corresponding dominant frequency simultaneously when selecting synchronous or asynchronous working mode.Asynchronous enable signal A-EN and synchronous enabled signal S-EN are produced by main control MCU, are used for controlling the work of clock module.Main control MCU traffic rate control signal control clock selecting traffic rate, clock selection signal 3bit is used for selecting traffic rate, and every kind of working method is supported eight kinds of speed.

Asynchronous system: support 4.8kbps, 9.6kbps, 19.2kbps, 38.4kbps, 57.6kbps, 115.2kbps, 230.4kbps, 460.8kbps

The method of synchronization: support 16kbps, 32kbps, 64kbps, 128kbps, 256kbps, 512kbps, 1024kbps, 2048kbps

It is selective to the invention provides so many speed, can simulate the channel characteristic of different rates, can artificial antenna, wired, mobile, fixing multiple communication network feature.

In environmental simulator for high-speed communicating network, the MCU single-chip microcomputer is a central controller, and it links together a series of parts in periphery by the software that is solidificated in internal storage region, realizes the various functions of simulator jointly.Software systems comprise main program and a series of subprogram, and main program flow as shown in Figure 9.The at first internal register of initialization MCU single-chip microcomputer and external interface and serial communication interface after the start, remove the LCD buffer area, three options that show main menu: New-deployed Network environment map, read network environment (selecting the network environment figure of storage in advance), recover network environment figure last time, enter the keyboard handling procedure this moment, wait for that the user selects to be provided with network environment with keyboard:

1. the setting of reading this function of network environment is for fear of repetitive operation.The present invention has designed the network environment store function, stores among the rom after newly-built network environment input can being finished.Can store 20 cover network environments altogether, distinguish, show numbering in the bottom of liquid crystal display screen with the numbering of 1-20.Select to select corresponding numbers again after this function, can read corresponding network environment by definite key.Read after the parameter of its setting, program is carried out following process:

---topological diagram and environmental parameter are delivered to liquid crystal display screen refresh demonstration, comprise connected relation, the error rate and traffic rate between the node;

---the connected relation of node is converted to parameters such as switch matrix signal, the error rate, traffic rate gives FPGA and control.

2. behind the New-deployed Network environmental selection New-deployed Network environment map, enter the parameter setting program, comprise the topological relation of mode of operation (synchronous/asynchronous), channel speed, network, key parameters such as each channel bit error rate.Operating procedure is as follows:

---at first select to want the storage numbering of the topological diagram edited, by determining key, enter the topological diagram edit pattern then with right and left key.With the key switching is every up and down.

---input basic parameter: select mode of operation: synchronous/asynchronous; Selective channel speed; Select the error rate.

---topological environmental is set: use the channel setting key: " 1-2 ", " 1-3 ", " 1-4 " etc. are provided with the connected relation between the node.For example, when pressing " 2-3 " key, just be provided with node 2 and be communicated with link between the node 3, when once more by " 2-3 " key, the link disconnection between node 2 and the node 3.The user is provided with own required topological structure between 8 nodes.Can be after current topological diagram configures by " " key withdraws from esc, selects the current topological diagram of storage numbering storage, can continue to select numbering editor then if any second topological diagram, can edit 20 topological diagrams altogether.If all required topological diagrams are all finished, then in this pattern, press execute key, screen meeting refresh all shows first topological diagram to be simulated then, has at this moment just begun the analog network environment.

3. recovering network environment, to recover environment automatically be that the network environment of input is lost (storage before causing for fear of abnormal shutdown.Also availablely read network environment and recover as storing).One scratchpad area (SPA) is set in the rom of main control MCU, and when setting network environment, and after the operation, system at first stores this network environment into this scratchpad area (SPA), begins simulation afterwards again.If shutdown unusually in simulation process, thereby the network environment before can selecting to recover has avoided repeating input.Requirement will be provided with a cover route variation scheme and store, and refresh by the time interval dynamic change that is provided with.

After finishing the network environment selection, corresponding network environment parameter and topological diagram are presented on the liquid crystal display screen, display is opened up connected relation with the graphical display network, with the literal display working condition.MCU is converted to the switch controlling signal of matrix function with the switch key assignments, gives FPGA as matrix control signal, realizes the network exchange function.

The replacing of network topological diagram has manually and automatic two kinds, manually is as required, by user's Reparametrization; And automated manner is to change according to Routing Protocol.

In the process of simulation, press the esc key, just can stop and returning to main menu and carry out next step operation.

The present invention is provided with network environment by keyboard, make topological structure setting, the change convenient, flexible.Network environment can also for the present invention has increased a kind of network setting method, make the operation of system more flexible by the host PC setting not only by the keyboard setting.

The embodiment of analogue test of the present invention

Figure 10 is that the present invention carries out mobile self-organizing network communication test simulation schematic diagram.Adopt distributed layer management two-tier network structure.This network router is formed backbone network via the high speed network environment simulator, and next straton net also is to form via the high speed network environment simulator.The subnet of three kinds of different agreements shown in the figure, each subnet can be supported the communication of 8 mobile nodes, is the mobile communication demonstration net that can effectively support various types of traffic and different agreement.

When at subnet inside or internetwork communication, at first need between source node and purpose, seek and set up an accessible shortest path by.Alternative wired, the wireless various communication medias of simulator of the present invention are set up straight-through or required route is jumped in commentaries on classics.The topological structure of supposing the network simulator of subnet A inside is set to A ₁-A ₂-A ₃-A ₁The full-mesh state then is a hop node between each node; If the network simulator topological structure is set to A ₁-A ₃-A ₂, A then ₁With A ₂Between communication need node A ₃Switching, A ₁With A ₂Two hop nodes each other; If A ₁And A ₂Simultaneously to A ₃Send data, the node collision phenomenon has just taken place.Suppose that subnet A communicates by letter with subnet C, will seek a route that can reach through backbone network so.Procotol judges that destination node not at Home Network, through gateway node, enters backbone network, seeks the path, and the topological structure in the backbone network is set by network simulator, and assignment procedure is identical with subnet.When searching out the router three that is connected with subnet C, enter subnet C again, further seek, until finding destination node C ₃Till.Article one, the path that can reach has been set up, and can realize communicating by letter between A and the C.Network simulator has been arranged, and the setting of this route is just very convenient, thereby can verify multiple Routing Protocols such as full-mesh, multi-hop connection, data collision easily.The checking of this multilayer IP(Internet Protocol) all can't realize by software emulation and the test of actual physical channel.Network simulator of the present invention has been arranged, just can realize simply and flexibly indoor.The high speed network environment simulator is studied based on mobile radio network, but it also can be applicable to the research of fixed network and wired network protocol.Therefore, for procotol research, utilizing the network communications environment simulator is effective method.

Claims (3)

1. environmental simulator for high-speed communicating network, comprise microprocessor MCU, programmable logic device FPGA and peripheral assembly keyboard thereof, LCDs, memory, PC interface and eight communication node interfaces, described microprocessor MCU, carry out system's control, be used to produce switch matrix control signal, error code selection signal and rate selection signal, and the control signal that produces is transferred to programmable logic device FPGA processing; Described programmable logic device FPGA is used to realize the major function of simulator, receives the matrix control signal of MCU by data/address bus, and is latched in the memory cell; The rate selection and the error rate that receive MCU by control bus are selected control signal; Adopt synchronous serial connection mouth or asynchronous interface to be connected, its input, dateout are handled with eight road communication nodes; It is characterized in that: programmable logic device FPGA to the processing of communication node input, dateout comprise to its input synchronously, asynchronous data is handled and output synchronously, asynchronous data handles:

[1] after input data processing FPGA selects synchronous, the asynchronous data that receive, removes asynchronous data start bit and stop bits, become plain streams, produce corresponding bit clock signal simultaneously, together import the error code load-on module with the asynchronous process module; With the synchrodata processing module synchrodata is carried out the bit clock sampling, produce corresponding bit clock signal, realize that input signal and simulator clock signal are synchronous;

[2] dateout is handled under the switch matrix signal controlling, node data converges the signal gathering that module will flow to certain node and becomes one road signal, the asynchronous plain streams of this signal is added start bit and stop bits by data restoring module, is reduced into asynchronous transmission signal format; Synchrodata is directly output then.

2. environmental simulator for high-speed communicating network according to claim 1, it is characterized in that: described memory can be stored 20 default cover network environments, every cover contains the 20 network topo graphs of throwing the net, and the renewal of every topo graph has manual renewal and upgrades dual mode at interval automatically according to setting.

3. environmental simulator for high-speed communicating network according to claim 1, it is characterized in that: with key network environment is set and carries out three kinds of selections: promptly read network environment, New-deployed Network environment, recover network environment, network environment parameter and the topo graph selected are shown on liquid crystal display screen, and send programmable logic device FPGA to simulate.

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