CN1304087A - Microprocessor structure capable of implementing control of critical section - Google Patents
Microprocessor structure capable of implementing control of critical section Download PDFInfo
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- CN1304087A CN1304087A CN 99126042 CN99126042A CN1304087A CN 1304087 A CN1304087 A CN 1304087A CN 99126042 CN99126042 CN 99126042 CN 99126042 A CN99126042 A CN 99126042A CN 1304087 A CN1304087 A CN 1304087A
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Abstract
The present invention relates to a microprocessor structure capable of implementing critical section control, and is characterized by that it uses a instruction temporay memorry to hold the instruction to be executed by microprocessor, and provides a judgement logic unit to control the interrupt request signal line of microprocessor, the judgement logic unit is used to compare the content of the instruction temporary memory with a stored instruction, when the compared result is identical, the interrupt request signal line is closed, it can utilize the interrup service request closure after the holding instruction is executed or before the storage in struction is excecuted to implement control of cirtical section, so that when the holding and storage address are identical, it can implement control of ctritical section, and can implement complete document copying.
Description
The present invention is the technical field of relevant microprocessor, refers to a kind of microprocessor structure capable of implementing control of critical section especially.
In known microprocessor, can provide a kind of method to satisfy the control that the user uses for system resource usually when the environment of multiple stroke (Multi-Process) to critical section (Critical Section) control; with the generation of avoiding conflicting between each stroke; and the general method that adopts promptly is to use test and the mode of setting (Test and Set) to reach control to the critical section, and its algorithm is as follows:
bool test-and-set(bool*s){//atomic function, //can not be ∥interruptedbool original=s；s=true；return original；}
And the use-case that makes of corresponding program end is:
while(test-and-set(&sign));//if sign is true, //someone else is //in critical //section,wait.…Critical section here…sing=false;//leave critical section,make it //available to others.…Non-critical section…
Is that whole function performance is packaged in the exclusive instruction with it in general micro controller for the realization of Test and Set, and reach indivisible characteristic, can be to guarantee whole process once to be finished not interrupted by other program of carrying out midway.Microprocessors such as 80386 and 80486 in the x86 family that is produced with the most common INTE1 company are to provide the exclusive instruction of BTS (Test Bit Set) to realize the method for Test and Set.Yet this kind is in the mode of the control that provides extra exclusive instruction to realize to use for the critical section, more instruction set number must be arranged for microprocessor, even cause to use long instruction length, and also can increase the complexity and size of microprogram, the exclusive instruction of more necessary use just can be accomplished the control of critical section and the management of system resource for the developer of application program, therefore, aforementioned known microprocessor gives improved necessity in fact for the mode of the control of critical section use.
The creator whence originally in the spirit of positive innovation, is urgently thought a kind of " microprocessor structure capable of implementing control of critical section " that can address the above problem because of in this, and several times research experiment is eventually to finishing this novel progressive creation.
A purpose of the present invention is that a kind of microprocessor structure capable of implementing control of critical section is being provided, and it does not need exclusive instruction can support the control of critical section with simple circuit.
Another object of the present invention is that a kind of microprocessor structure capable of implementing control of critical section is being provided, and it can realize safe data recasting.
For reaching aforesaid purpose, microprocessor structure capable of implementing control of critical section of the present invention is the instruction that keeps microprocessor to carry out with an instruction registor, and provide a decision logic unit to come the interrupt request signal line of control microprocessor according to the content of this instruction registor, to judge that when this decision logic unit content that this instruction registor was kept is one when being written into instruction or save command, this interrupt request signal line is closed, before being written into instruction execution back or save command execution, closed the control that the critical section is reached in the break in service requirement and utilize, so when being written into when identical with the address that stores, can realize the control of critical section, and the address is not simultaneously, and can realize safe data recasting.
Because modern design of the present invention can provide on the industry and utilize, and truly have the enhancement effect, so apply for a patent in accordance with the law.
For making your juror can further understand structure of the present invention, feature and purpose thereof, the attached now detailed description with stationary and preferred embodiment as after, wherein:
Fig. 1 is the functional block diagram of microprocessor structure capable of implementing control of critical section of the present invention.
Fig. 2 is the structural drawing of a preferred embodiment of microprocessor structure capable of implementing control of critical section of the present invention.
Fig. 3 is the structural drawing of another preferred embodiment of microprocessor structure capable of implementing control of critical section of the present invention.
Fig. 4 is the structural drawing of the another preferred embodiment of microprocessor structure capable of implementing control of critical section of the present invention.
Fig. 5 is the structural drawing of a preferred embodiment again of microprocessor structure capable of implementing control of critical section of the present invention.
For improving the implementation of microprocessor to critical section control, at first via to the analysis of the critical section steering order of general test and setting (Test and Set) as can be known, it has following properties:
(1) Test and Set instruction is made up of an instruction that is written into (Load) and storage (Store).
(2) implementation that is written into and stores two instructions among the Test and Set is cannot be divided.
(3) whether the break in service requirement is just can be examined to be triggered before an instruction is finished back or execution.
According to above-mentioned characteristic, microprocessor structure capable of implementing control of critical section of the present invention is the inspection of then closing the break in service requirement before back or save command execution are carried out in instruction being written into, so that be written into and store between two instructions is to carry out continuously and can be not divided, and can realize control, so only need select one and can implement to being written into or storing to the critical section.
Fig. 1 promptly shows the functional block diagram of microprocessor structure capable of implementing control of critical section of the present invention, it mainly is with interrupt request signal line 11, instruction registor 12, decision logic unit 13 and demoder 15 provide the function of instruction decoding and down trigger, and realization is to the control of critical section, wherein, this instruction registor 12 is the instructions in order to keep microprocessor to carry out, and decode to carry out it by 15 pairs of these instructions of this demoder, and this decision logic unit 13 is to control this interrupt request signal line according to the content of this instruction registor 13, to judge that when this decision logic unit 13 content that this instruction registor was kept is one when being written into instruction or save command, this decision logic unit 13 is the output states that produce a logical one in its output, otherwise be the state of output logic 0, and this interrupt request signal line 11 and just be connected to a colligator 14 with the output of this decision logic unit 13, anti-input end, according to this inverse value of the output of interrupt request and this decision logic unit 13 is carried out the computing of logical and (AND), the output of this colligator 14 then is fed to this demoder 15.
Structure by above-mentioned microprocessor, the instruction that will carry out when this instruction registor 12 is to be written into or during save command for one, this decision logic unit 13 is output as logical one, computing via this colligator 14, this logical one carries out the computing that logic reaches through anti-phase for logical zero and with interrupt request, this interrupt request signal line 11 is closed, can reach and make that to be written into and to store between two instructions be to carry out continuously and can divided effect, otherwise, the instruction that will carry out when this instruction registor 12 is non-to be one to be written into or during save command, this interrupt request signal line 11 is to be fed to this demoder 15 through this colligator 14, to allow the generation of interruption acknowledge.
Therefore, when being written into when identical with the address that stores, can realize the control of critical section, and the address is not simultaneously, and can realize safe data recasting (data duplicate), that is to be written into and save command is remake in the process of data, the not influence that can be interrupted and destroy the security of data.Aforesaid again be written into or save command is not limited to access to storer (Memory) also can be used the access for I/O mouth (IO Port).
And to other general non-being written into or the execution of save command of critical section control of being engaged in, can close the action of break in service with eliminating by limiting its addressing mode, that is, this decision logic unit 13 only when judging that the instruction that this instruction registor 12 is kept is the addressing mode of microprocessor in order to the instruction of access critical section, is just closed this interrupt request signal line 11.In addition, and can whether be that storage and other approximate mode are got rid of most situation further by limiting the order (for example will be written into and store alternate order and change continuous being written into or storing into) that instructs or prejudging next bar instruction, for the situation of failing to get rid of, because this kind function is just closed the inspection of break in service requirement, delay an instruction time generation (be written into and carry out the required time) so only can cause interrupt service routine, and consuming time very short, so even under the situation of erroneous judgement, also there is not influence for function face and result owing to being written into the instruction execution.
With reference to a preferred embodiment shown in Figure 2, it is to come content and to instruction registor 12 to be written into instruction with a comparer 21 to compare, reach the function of the decision logic unit 13 of aforementioned microprocessor structure capable of implementing control of critical section according to this, and as this comparer 21 result relatively when being identical, it is closed this interrupt request signal line 11, therefore can after being written into the instruction execution, close the break in service requirement, and realize control the critical section.
Fig. 3 then shows another preferred embodiment of the present invention, it is to come the content of instruction registor 12 is compared with a save command with a comparer 31, reach the function of the decision logic unit 13 of aforementioned microprocessor structure capable of implementing control of critical section according to this, and as this comparer 31 result relatively when being identical, it is closed this interrupt request signal line 11, therefore can before save command is carried out, close the break in service requirement, and realize control the critical section.
Fig. 4 then shows another preferred embodiment of the present invention, it is with a comparer 41, one storage unit 42 and a colligator 43 are realized the decision logic unit 13 of aforementioned microprocessor structure capable of implementing control of critical section, wherein, this comparer 41 is that the content and to instruction registor 12 is written into instruction or a save command is compared, when being identical when comparative result, it relatively is output as 1, and work as comparative result for not simultaneously, it relatively is output as 0, this storage unit 42 is preferably to be a bolt lock device, for in order to keep this comparer 41 in the relatively output that the last instruction cycle produced, and what the relatively output that this comparer 41 is produced and this storage unit 42 were kept is just relatively exporting and is being connected to this colligator 43, anti-input end, according to this present relatively output and the relatively inverse value of output in last cycle are carried out the computing of logical and (AND), the output of this colligator 43 promptly is in order to control interrupt request signal line 11, the output that also is about to interrupt request signal line 11 and this colligator 43 just is being connected to another colligator 14, anti-input end, so that inverse value and this interrupt request signal line 11 of the output of aforementioned colligator 43 are carried out the computing of logical and, and can be at this comparer 41 relatively be output as 1, and what this storage unit 42 was kept relatively is output as at 0 o'clock, this interrupt request signal line 11 is closed, so removing can be by carrying out and closes the break in service requirement before back or save command are carried out and realize the control to the critical section being written into instruction, and can further get rid of continuous be written into or the save command execution the erroneous judgement that may cause.
Fig. 5 shows a preferred embodiment more of the present invention, it is with one first comparer 51, one second comparer 52 and a logical AND gate 53 are realized the decision logic unit 13 of aforementioned microprocessor structure capable of implementing control of critical section, wherein, this first comparer 51 is that the content and to instruction registor 12 is written into instruction and compares, when being identical when comparative result, it relatively is output as 1, and work as comparative result for not simultaneously, it relatively is output as 0, this second comparer 52 is to compare in advance in order to the instruction that will carry out the next instruction cycle, and the instruction that the next instruction cycle will carry out is kept by the working storage 54 of looking ahead, therefore, this second comparer 52 promptly is that the content of this working storage 54 of looking ahead is compared with a save command, when being identical when comparative result, it relatively is output as 1, and work as comparative result for not simultaneously, it relatively is output as 0, and the input end of relatively exporting and be connected to this logical AND gate 53 that the relatively output that this first comparer 51 is produced and this second comparer 52 are produced, according to this with two comparers 51, the computing that logic reaches is carried out in 52 output, the output of this logical AND gate 53 promptly is in order to control interrupt request signal line 11, the output that also is about to this interrupt request signal line 11 and this logical AND gate 53 just is being connected to colligator 14, anti-input end, with the inverse value of the output of this logical AND gate 53 and this interrupt request signal line 11 are carried out logic and computing, and can be at this first and second comparer 51,52 relatively output is at 1 o'clock, this interrupt request signal line 11 is closed, close the effect of break in service requirement to reach before being written into instruction execution back and save command execution, and can further reduce the possibility of erroneous judgement.
Via aforesaid explanation as can be known, with respect to known mode to provide extra exclusive instruction to support critical section control, microprocessor structure capable of implementing control of critical section of the present invention has following benefit:
(1) need not provide extra exclusive instruction can support the control of critical section, the instruction set number is less.
(2) only need simple circuit can reach control, can simplify the exploitation of microprogram, do not need to realize especially exclusive steering order.
(3) parallel simultaneously term of execution that the control of critical section can and instruction, therefore can't increase on the sequential of carrying out for each instruction.
(4) the general instruction of use that can very suitable feel for procedure development person and reach the control of critical section need not the exclusive instruction of special call.
(5) the present invention also provides a kind of safe data recasting mode.
To sum up institute is old, and no matter the present invention is all showing it totally different in the feature of known techniques with regard to purpose, means and effect, for the quantum jump of microprocessor in the design that realizes critical section control, earnestly ask your juror and perceive, grant quasi patent early, with Jiahui society, the true feeling moral just.Only it should be noted that above-mentioned many embodiment give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (10)
1. a microprocessor structure capable of implementing control of critical section is characterized in that, mainly comprises:
One interrupt request signal line;
One instruction registor is the instruction that keeps microprocessor to carry out: and.
One decision logic unit, its content according to this instruction registor is controlled this interrupt request signal line, to judge that when this decision logic unit content that this instruction registor was kept is one when being written into instruction or save command, is closed this interrupt request signal line.
2. microprocessor structure capable of implementing control of critical section according to claim 1, it is characterized in that, wherein this interrupt request signal line is closed in this decision logic unit and when judgement content that this instruction registor kept is the instruction of specific addressing mode.
3. microprocessor structure capable of implementing control of critical section according to claim 2 is characterized in that, wherein this specific addressing mode is to be the addressing mode of microprocessor in order to the instruction of access critical section.
4. microprocessor structure capable of implementing control of critical section according to claim 1, it is characterized in that, wherein this decision logic unit is a comparer, with the content and to this instruction registor be written into the instruction or a save command compare, and, this interrupt request signal line is closed as relatively result when being identical.
5. microprocessor structure capable of implementing control of critical section according to claim 1, it is characterized in that, also comprise a colligator with the inverse value of the output of this interrupt request signal line and this comparer is carried out logic and computing, use comparative result at this comparer and be identical and it is output as at 1 o'clock, this interrupt request signal line is closed.
6. a microprocessor structure capable of implementing control of critical section is characterized in that, mainly comprises:
One interrupt request signal line;
One instruction registor is the instruction that keeps microprocessor to carry out:
One comparer, it is that content and to this instruction registor is written into instruction or a save command is compared, to produce a relatively output; And
One storage unit is in order to keep this comparer in the relatively output that the last instruction cycle produced;
Wherein, it is identical representing comparative result when the relatively output of this comparer, and the relatively output that this storage unit kept represents comparative result for not simultaneously, and this interrupt request signal line is to be closed.
7. microprocessor structure capable of implementing control of critical section according to claim 6, it is characterized in that, wherein also comprise one first colligator and one second colligator, this first colligator is that relatively output that this comparer is produced and the inverse value of relatively exporting that this storage unit is kept are carried out the computing that logic reaches, this second colligator is that the inverse value of the output of this first colligator and this interrupt request signal line are carried out the computing that logic reaches, use comparative result at this comparer and be identical and it relatively is output as 1, and what this storage unit kept relatively is output as at 0 o'clock, and this interrupt request signal line is closed.
8. microprocessor structure capable of implementing control of critical section according to claim 7 is characterized in that, wherein this storage unit is to be a bolt lock device.
9. a microprocessor structure capable of implementing control of critical section is characterized in that, mainly comprises:
One interrupt request signal line;
One instruction registor is the instruction that keeps microprocessor to carry out:
One working storage of looking ahead is to read the next instruction that microprocessor will be carried out in advance;
One first comparer, it is that content and to this instruction registor is written into instruction and compares, to produce one first relatively output: and
One second comparer, it is that the content of this working storage of looking ahead is compared with a save command, to produce one second relatively output;
Wherein, when this first relatively output and this second relatively output is when all to represent comparative result be identical, this interrupt request signal line is to be closed.
10. microprocessor structure capable of implementing control of critical section according to claim 7, it is characterized in that, also comprise a logical AND gate and a colligator, this logical AND gate be to this first relatively output and this second relatively output carry out the computing of logical and, this colligator is that the inverse value of the output of this logical AND gate and this interrupt request signal line are carried out the computing of logical and, use comparative result at this first and second comparer be identical and this first and second relatively export and be at 1 o'clock, this interrupt request signal line is closed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 99126042 CN1224896C (en) | 1999-12-13 | 1999-12-13 | Microprocessor structure capable of implementing control of critical section |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 99126042 CN1224896C (en) | 1999-12-13 | 1999-12-13 | Microprocessor structure capable of implementing control of critical section |
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| CN1304087A true CN1304087A (en) | 2001-07-18 |
| CN1224896C CN1224896C (en) | 2005-10-26 |
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| CN 99126042 Expired - Fee Related CN1224896C (en) | 1999-12-13 | 1999-12-13 | Microprocessor structure capable of implementing control of critical section |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102801419B (en) * | 2004-02-23 | 2016-12-21 | 索尼株式会社 | Analog-digital conversion method and device, semiconductor device and electronic installation |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102801419B (en) * | 2004-02-23 | 2016-12-21 | 索尼株式会社 | Analog-digital conversion method and device, semiconductor device and electronic installation |
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| CN1224896C (en) | 2005-10-26 |
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Granted publication date: 20051026 Termination date: 20131213 |