CN1298117C - Cross-processing method for float pointer - Google Patents
Cross-processing method for float pointer Download PDFInfo
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- CN1298117C CN1298117C CNB021453896A CN02145389A CN1298117C CN 1298117 C CN1298117 C CN 1298117C CN B021453896 A CNB021453896 A CN B021453896A CN 02145389 A CN02145389 A CN 02145389A CN 1298117 C CN1298117 C CN 1298117C
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Abstract
The present invention discloses a cross processing method of floating pointers. The CJ signal and the PL signal of a floating or locking pointer are delayed and born again after being crosswise processed by a time-division cross matrix; the method at least comprises the steps of processing the CJ signal and processing the PL signal. The technical scheme provides a pointer processing method of different mapping mode signals after the signals pass through the time-division cross matrix. The required function can be finished only by minor logic; signals of any mapping mode can finish cross via the time-division cross matrix. The method has generally adaptable significance in SDH systems.
Description
Technical field:
The present invention relates to the method for the Optical synchronization digital transmission in a kind of communication field, relate in particular to the cross processing method of the floating pointer in the light synchronizing digital transmission equipment.
Background technology:
In synchronous digital hierarchy (Synchronous Digital Hierarchy is called for short SDH) equipment, generally adopt cross-interaction matrix of time division to finish the flexible intersection allotment of tributary unit (Tributary Unit is called for short TU) level signal.In the handling process of SDH device signal, for with tributary unit group (Tributary Unit Group, abbreviation TUG) signal of structure composition, before entering cross-interaction matrix of time division, at first carry out finishing administrative unit (AdministrativeUnit via the adjustment of TU pointer, being called for short AU) pointer following unload the relocation process with multi-frame, make and enter the signal that cross-interaction matrix of time division signal before becomes the locking of AU pointer, the signal of each TU is all adjusted on the fixedly columns of SDH frame, and what make that cross-interaction matrix of time division can be by standard intersects the intersection finish the TU signal by row.
At this moment, the data that go out cross-interaction matrix of time division are than entering cross-interaction matrix of time division data N 19M clock cycle of time-delay before, the pointer of signal also is the standard locking pointer and corresponding to intersecting afterwards, wherein C1 signal (output header signal) is than input FP (input header signal) N clock cycle of time-delay of cross-interaction matrix of time division, (AU provides the message structure of adaption function for higher order path layer and multiplex section layer for AU-4, two kinds of forms of AU-3 and AU-4 are arranged) signal, J1 (pointer index signal) signal is in the position in the 3rd 19M cycle behind the C1 signal, for the AU-3 signal, the J1 signal is in the position in continuous 3 19M cycles in the 3rd 19M cycle behind the C1 signal.The PL signal is that 9 clock cycle of standard are low, and 261 clock cycle are high signal, and adjusting the position at positive and negative pointer does not have pointer adjustment indication.
But signal for non-TUG structure, such as: from VC (virtual container, Virtual Container)-4 (ITU-T is the standard interface container of finishing adaption function in the agreement G.707 to map directly to the signal C4 of AU-4, be a kind of message structure) → VC-4 → AU-4, with (ITU-T is the standard interface virtual container the agreement G.707 from VC3, be a kind of message structure) map directly to signal C3 → VC3 → AU-3 of AU-3, can not be by the following module of unloading with the relocation process of multi-frame of finishing the AU pointer via the adjustment of TU pointer.Its reason is: it does not comprise the TU pointer part.On processing mode, data adopt direct mode operation in this functional module, according to the position of output frame head, with several 19M week after date outputs of signal lag.The signal of this mapped mode is exactly the signal that pointer floats when entering cross-interaction matrix of time division.
According to the definition of the frame structure of SDH: what VC-4 and VC-3 occupied in the frame structure of SDH is the columns of fixing, so the time-division of the data of the signal that floats for this pointer intersects and can followingly carry out:
For the VC-4 signal, 261 row that can be directly that whole VC-4 signal is shared are all straight-through; Corresponding to the VC-3 signal, exactly with each VC-3 signal with its 86 fixing as a whole intersections of row that occupy.
Summary of the invention:
Main purpose of the present invention is to provide the signal of a kind of AU-4 of comprising and all mapped modes of AU-3 intersecting the back pointer treatment method corresponding with dateout through the time-division, comprise float or locking pointer CJ (signal-arm) signal and PL (payload index signal) signal in the method for living again through the time-delay after the cross-interaction matrix of time division cross processing, make the SDH equipment that calls this module correct finish the function of the signal of various mapped modes being carried out the low order signal cross.
The object of the present invention is achieved like this:
A kind of method of cross processing of floating pointer, will float or locking pointer CJ signal and PL signal living again through the laggard line delay of cross-interaction matrix of time division cross processing, specifically comprise to the CJ Signal Processing with to the PL Signal Processing.Wherein, comprise for the CJ Signal Processing:
Step 10: extract respectively according to the J1 signal of the frame structure of frame head and SDH definition with 3 AU-3 correspondences;
Step 11: with the clock cycle of each J1 signal lag one predetermined number;
Step 12: the J1 signal of 3 AU-3 correspondences is adjusted on the position of identical AU-3;
Step 13: the input of the J1 signal of each the AU-3 correspondence that need intersect being introduced cross matrix, and the J1 signal of the latched position that will produce according to frame head also introduces the input of cross matrix, then according to the intersection of data with its corresponding J1 signal cross to the position corresponding with the cross matrix dateout;
Step 14: the J1 signal of 3 AU-3 of every group of data correspondence and frame head synthesize complete CJ signal.
Comprise for the PL Signal Processing:
Step 20: the PL signal extraction that each AU-3 adjusts the position corresponding to pointer is come out, and the output of the clock cycle of the predetermined number of delaying time;
Step 21: the PL signal that the pointer of 3 AU-3 is adjusted the position is all adjusted to the pointer of the AU-3 of same position and is adjusted on the corresponding position, position;
Step 22: the input of the pointer of each the AU-3 correspondence that need intersect being adjusted the PL signal introducing cross matrix of position, and the pointer of first AU-3 that will produce according to the frame head locking PL signal of adjusting the position also introduces the input of cross matrix, according to the intersection of data the pointer of its corresponding each AU-3 correspondence adjusted the PL signal cross of position to the position corresponding with data then;
Step 23: the PL signal of the pointer of 3 AU-3 of every group of data correspondence being adjusted the position is synthetic;
Step 24: the PL signal according to frame head and pointer adjustment position lives again out with complete PL signal.
Above-mentioned technical scheme provides the pointer treatment method of a kind of different mappings mode signal behind the process cross-interaction matrix of time division, only use less logic just can finish required function, make the signal of any mapped mode can finish the intersection of signal, in the SDH system, have general significance of application via cross-interaction matrix of time division.
Description of drawings:
Fig. 1 is multiplexing mapping structure schematic diagram G.707.
Fig. 2 is the transaction module of cross-interaction matrix of time division.
Fig. 3 is the particular flow sheet of CJ signal lag of the present invention cross processing.
Fig. 4 is the particular flow sheet of PL signal lag of the present invention cross processing.
Embodiment:
The present invention is described in further detail below in conjunction with accompanying drawing and specific embodiment:
Referring to Fig. 1, it is the multiplexing mapping structure schematic diagram of (be the standard of international uniform, that is: the standard agreement of SDH (Synchronous Digital Hierarchy) (SDH) Network-Node Interface, ITU-T G.707) defined SDH G.707.
As can be seen from the figure: outside the signal of forming divided by C4 → VC4 → AU-4 and C3 → VC3 → AU-3 mapped mode, the signal of other mapping path is all finished mapping to AU via TU.For the signal of forming with the TUG pattern, before entering cross matrix, can be by the following module of unloading with the relocation process of multi-frame of finishing the AU pointer via the adjustment of TU pointer, and become the signal of AU pointer locking; So after intersecting through cross matrix, the pointer corresponding with output signal is locking pointer.And for the signal of C4 → VC4 → AU-4 and C3 → VC3 → AU-3 mapping path, the following relocation process of unloading with multi-frame that can not finish the AU pointer via the adjustment of TU pointer then is so be the signal that the AU pointer floats when entering cross matrix; Therefore, cooperate the intersection of data, its signal-arm also will be done corresponding intersection.Among the present invention the intersection of the pointer of the floating mode of indication be exactly especially at the signal of these two kinds of mapped modes in the processing of carrying out time slot pointer of correspondence when intersecting.
Referring to Fig. 2, Fig. 3 and Fig. 4, one embodiment of the invention specific embodiment is as follows:
To the CJ Signal Processing:
1,, the J1 signal of 3 AU-3 correspondences is extracted respectively according to the definition of the frame structure of frame head and SDH.The method of extracting is: set up a cycle counter, count value is 0,1,2, is 2 o'clock in the position of frame head sum counter value, with the Counter Value zero clearing.Count value according to counter is separated the J1 signal of importing; In count value is 0 o'clock, is output as the J1 signal of first AU-3; In count value is 1 o'clock, is output as the J1 signal of second AU-3; In count value is 2 o'clock, is output as the J1 signal of the 3rd AU-3.Header signal was exported after clock cycle of time-delay, and the output frame head is corresponding with output J1 signal.In this step, the J1 signal of each AU-3 and frame head are all delayed time 1 clock cycle.
2, with 269 clock cycle of each J1 signal lag.Be to save resource, the method for time-delay is: adopting one 9 counter, is zero clearing and enabling counting signal with the J1 signal, when the counter meter to 269 the time, export a high impulse as the J1 signal after delaying time, count value stops to count greater than 271 hour counters.The time-delay method of frame head is identical with the J1 signal; Adopting one 9 counter, is zero clearing and enabling counting signal with the header signal, when the counter meter to 269 the time, export the frame head of a high impulse after as time-delay, count value stops counting greater than 271 hour counters.In this step, the J1 signal of each AU-3 and frame head are all delayed time 269 clock cycle.
3, the J1 signal of 3 AU-3 correspondences is adjusted on the position of first AU-3.Concrete method is: with 3 clock cycle of J1 signal lag of first AU-3, and with 2 clock cycle of J1 signal lag of second AU-3, with 1 clock cycle of J1 signal lag of the 3rd AU-3, and with 3 clock cycle outputs of the frame head of correspondence time-delay.In this step, the J1 signal of first AU-3 and frame head are all delayed time 3 clock cycle.
4, the J1 signal of the AU-3 correspondence that each need be intersected is introduced the input of cross matrix, and the J1 signal of the latched position that will produce according to frame head is also introduced the input of cross matrix, the position of its position the 3rd clock cycle behind frame head corresponds to the J1 signal of locking data; Intersection according to data arrives the position corresponding with the cross matrix dateout with its corresponding J1 signal cross then.In this step, the J1 signal of each AU-3 and frame head are all delayed time 1 clock cycle.
5, J1 signal and the frame head with 3 AU-3 of every group of data correspondence synthesizes complete CJ signal.Concrete synthetic method is: earlier with second 1 clock cycle of J1 signal lag of exporting the AU-3 correspondence, with 2 clock cycle of J1 signal lag of the 3rd output AU-3 correspondence, then with the J1 signal of 3 AU-3 correspondences and frame head together mutually or, obtain the CJ signal corresponding with one group of data-signal of AU-3 standard.If these data are the signal of the AU-4 standard of locking, then can in this step, produce the CJ signal of the locking corresponding with data according to frame head.If the AU-4 standard signal that floats then adopts identical method to handle with the AU-3 standard signal, still, 3 pointers of correspondence to be done same cross processing during intersection.In this step, CJ signal and frame head are all delayed time 1 clock cycle.
Processing through above 5 steps promptly obtains the time-delay corresponding with the data that the go out cross matrix CJ signal in 275 cycles.
To the PL Signal Processing:
1, the PL signal extraction that each AU-3 is adjusted the position corresponding to pointer is come out, and 269 the clock cycle outputs of delaying time.Wherein, the PL signal of adjusting the position corresponding to the pointer of first AU-3 is PL1, and the PL signal of adjusting the position corresponding to the pointer of second AU-3 is PL2, and the PL signal of adjusting the position corresponding to the pointer of the 3rd AU-3 is PL3.
Concrete implementation method is: the counter of setting up one 9 is as the counting that is listed as in the SDH frame structure, and count range is 0-269; The counter of setting up one 4 is as the counting of going in the SDH frame structure, and count range is 0-8, and the counting of being expert at was less than 8 o'clock, and column count is that 269 o'clock row count values add 1, the column count zero clearing.Be expert at the counting be 8 and column count be the zero clearing of 269 o'clock row count values, the column count zero clearing.In the frame head position, the row count value is 0, and the column count value is 6.
According to SDH frame structure definition, line number wherein is 3, and columns is 6 o'clock, the position of adjusting for the negative pointer of first AU-3; Line number is 3, and columns is 7 o'clock, is the position of the negative pointer adjustment of second AU-3; Line number is 3, and columns is 8 o'clock, is the position of the negative pointer adjustment of the 3rd AU-3; Line number is 3, and columns is 9 o'clock, the position of adjusting for the positive pointer of first AU-3; Line number is 3, and columns is 10 o'clock, is the position of the positive pointer adjustment of second AU-3; Line number is 3, and columns is 11 o'clock, is the position of the positive pointer adjustment of the 3rd AU-3.
Because need and will extract in the PL value that pointer is adjusted the position, so be 3 in line number, columns is 6,7,8,9,, the value of PL signal is latched in six registers (not shown) among T1, T2, T3, T4, T5, the T6 respectively at 10,11 o'clock.
One 9 counter is adopted in concrete time-delay, is 3 in line number, columns is to start this counter at 6 o'clock, count value to 268 and 271 o'clock, respectively the value of register T1 and register T4 is got among the signal PL1, all the other constantly signal PL1 be low; Count value to 269 and 272 o'clock, respectively the value of register T2 and register T5 is got among the signal PL2, all the other constantly signal PL2 be low; Count value to 270 and 273 o'clock, respectively the value of register T3 and register T6 is got among the signal PL3, all the other constantly signal PL3 be low.Count value reaches 280 hour counters and stops counting.
2, the PL signal of the pointer of 3 AU-3 being adjusted the position is all adjusted to the pointer of first AU-3 and is adjusted on the corresponding position, position.Method is the pointer of first AU-3 to be adjusted 3 clock cycle of PL signal lag of position, the pointer of second AU-3 is adjusted 2 clock cycle of PL signal lag of position, the pointer of the 3rd AU-3 is adjusted 1 clock cycle of PL signal lag of position, and with 3 clock cycle outputs of frame head time-delay of correspondence.In this step, the pointer of output is adjusted the PL signal and the frame head of position and is delayed time on phase place 3 clock cycle than input signal.
3, the pointer of the AU-3 correspondence that each need be intersected is adjusted the input of the PL signal introducing cross matrix of position, and the pointer of first AU-3 that will produce according to the frame head locking PL signal of adjusting the position is also introduced the input of cross matrix, its signal form is that the position of the negative pointer adjustment of first AU-3 is low, and the position signalling of adjusting at the positive pointer of first AU-3 is high.According to the intersection of data the pointer of its corresponding each AU-3 correspondence is adjusted the PL signal cross of position to the position corresponding with data then.In this step, adjust the PL signal and the frame head of position from the pointer of cross matrix output and delay time 1 clock cycle in phase place than input signal.
4, it is synthetic the pointer of 3 AU-3 of every group of data correspondence to be adjusted the PL signal of position.Synthetic method is: 1 clock cycle of PL signal lag of earlier pointer of second AU-3 correspondence being adjusted the position, the pointer of the 3rd AU-3 correspondence is adjusted 2 clock cycle of PL signal lag of position, the PL signal of the pointer of 3 AU-3 correspondences being adjusted the position is done exclusive disjunction with frame head then, obtains the PL signal that the pointer corresponding with one group of data-signal of AU-3 standard adjusted the position.If these data are the signal of the AU-4 standard of locking, then can in this step, produce the PL signal that the locking pointer corresponding with data adjusted the position according to frame head.If the AU-4 standard signal that floats then adopts with the AU-3 standard signal and handles with quadrat method; But, 3 pointers of correspondence to be done same cross processing during intersection.In this step, the pointer of output is adjusted the PL signal and the frame head of position and is delayed time on phase place 1 clock cycle than input signal.
5, according to the PL signal of frame head and pointer adjustment position complete PL signal is lived again out.Concrete method is: the counter of setting up one 9 is as the counting that is listed as in the SDH frame structure, and count range is 0-269; The counter of setting up one 4 is as the counting of going in the SDH frame structure, and count range is 0-8, is that 269 o'clock row count values add 1, the column count zero clearing in column count.If the row counting is greater than 8, then row is counted zero clearing.In the frame head position, the row counting is zero, and column count is 6.These two counters are according to this rule cycle count.
The counting of being expert at is 3, and when column count was 6-11, the output of PL selected pointer to adjust the PL signal of position, and in other position, the output of PL is low when counting less than 9 the time, when column count more than or equal to 9 the time, PL is output as height.In this step, the PL signal of output and frame head are delayed time on phase place 1 clock cycle than input signal.
Processing through above 5 steps obtains the time-delay corresponding with the data that the go out cross matrix PL signal in 275 cycles.
It should be noted last that: above embodiment is the unrestricted technical scheme involved in the present invention in order to explanation only, although the present invention is had been described in detail with reference to above preferred embodiment, those of ordinary skill in the art should be appreciated that technical scheme of the present invention can make amendment, is out of shape or is equal to replacement; And do not break away from the spirit and scope of technical solution of the present invention, all should be encompassed among the claim scope of the present invention.
Claims (1)
1, a kind of method of cross processing of floating pointer, it is characterized in that: will float or locking pointer signal and payload index signal are being lived again through the laggard line delay of cross-interaction matrix of time division cross processing, at least comprise to the processing of signal-arm with to the processing of payload index signal
Wherein, the processing to signal-arm comprises:
Step 10:, the J1 signal of 3 AU-3 correspondences is extracted respectively according to the definition of the frame structure of frame head and SDH;
Step 11: with the clock cycle of each J1 signal lag one predetermined number;
Step 12: the J1 signal of 3 AU-3 correspondences is adjusted on the position of identical AU-3;
Step 13: the input of the J1 signal of each the AU-3 correspondence that need intersect being introduced cross matrix, and the J1 signal of the latched position that will produce according to frame head also introduces the input of cross matrix, then according to the intersection of data with its corresponding J1 signal cross to the position corresponding with the cross matrix dateout;
Step 14: J1 signal and the frame head of 3 AU-3 of every group of data correspondence are synthesized complete signal-arm,
Processing to the payload index signal comprises:
Step 20: the payload index signal that each AU-3 is adjusted the position corresponding to pointer extracts, and the output of the clock cycle of the predetermined number of delaying time;
Step 21: the payload index signal that the pointer of 3 AU-3 is adjusted the position is all adjusted to the pointer of the AU-3 of same position and is adjusted on the corresponding position, position;
Step 22: the input of the pointer of each the AU-3 correspondence that need intersect being adjusted the payload index signal introducing cross matrix of position, and the pointer of first AU-3 that will produce according to the frame head locking payload index signal of adjusting the position also introduces the input of cross matrix, and the payload index signal of the pointer of its corresponding each AU-3 correspondence being adjusted the position according to the intersection of data is crossed to the position corresponding with data then;
Step 23: the payload index signal of the pointer of 3 AU-3 of every group of data correspondence being adjusted the position is synthetic;
Step 24: the payload index signal according to frame head and pointer adjustment position lives again out with complete payload index signal.
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| CNB021453896A CN1298117C (en) | 2002-11-21 | 2002-11-21 | Cross-processing method for float pointer |
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| CNB021453896A CN1298117C (en) | 2002-11-21 | 2002-11-21 | Cross-processing method for float pointer |
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| CN1298117C true CN1298117C (en) | 2007-01-31 |
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| JP4453915B2 (en) * | 2005-03-18 | 2010-04-21 | 富士通株式会社 | Crossbar device, control method and program |
| CN101814966B (en) * | 2009-11-25 | 2013-01-30 | 华为技术有限公司 | Method and device for configuring new pointer value in multi-frame cascade of cross chips |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1051646A (en) * | 1989-08-31 | 1991-05-22 | 西门子公司 | The cross-join method of synchronous digital multiplexing series STM-1 signal |
| US5335223A (en) * | 1991-12-18 | 1994-08-02 | Fujitsu Limited | Pointer processing circuit in sonet system |
| JPH07135673A (en) * | 1993-11-10 | 1995-05-23 | Nec Corp | Cross connector |
| US5914952A (en) * | 1995-12-23 | 1999-06-22 | Electronics And Telecommunications Research Institute | Tributary unit signal cross-connection apparatus |
| CN1230834A (en) * | 1998-02-25 | 1999-10-06 | 朗迅科技公司 | Nonblocking synchronous digital hierarchy column cross-point switch |
-
2002
- 2002-11-21 CN CNB021453896A patent/CN1298117C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1051646A (en) * | 1989-08-31 | 1991-05-22 | 西门子公司 | The cross-join method of synchronous digital multiplexing series STM-1 signal |
| US5335223A (en) * | 1991-12-18 | 1994-08-02 | Fujitsu Limited | Pointer processing circuit in sonet system |
| JPH07135673A (en) * | 1993-11-10 | 1995-05-23 | Nec Corp | Cross connector |
| US5914952A (en) * | 1995-12-23 | 1999-06-22 | Electronics And Telecommunications Research Institute | Tributary unit signal cross-connection apparatus |
| CN1230834A (en) * | 1998-02-25 | 1999-10-06 | 朗迅科技公司 | Nonblocking synchronous digital hierarchy column cross-point switch |
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