CN1289143A - Semiconductor device and production technology thereof - Google Patents

Semiconductor device and production technology thereof Download PDF

Info

Publication number
CN1289143A
CN1289143A CN00126862A CN00126862A CN1289143A CN 1289143 A CN1289143 A CN 1289143A CN 00126862 A CN00126862 A CN 00126862A CN 00126862 A CN00126862 A CN 00126862A CN 1289143 A CN1289143 A CN 1289143A
Authority
CN
China
Prior art keywords
semiconductor chip
tape substrates
wire
type surface
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN00126862A
Other languages
Chinese (zh)
Inventor
秋山雪治
柴本正训
下石智明
有田顺一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Solutions Technology Ltd
Original Assignee
Hitachi Ltd
Hitachi ULSI Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi ULSI Systems Co Ltd filed Critical Hitachi Ltd
Publication of CN1289143A publication Critical patent/CN1289143A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0134—Quaternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present invention realizes the semiconductor device for improving the reflow durability, which comprises: a porous elastomer 3, which is configured on the main surface 1a of the semiconductor chip 1, and formed as exposing the opening 3c of the electrode pad 1b; and, the conductive wires 4c, extending from the main surface 1a to outside of the chip, and electrically connected with the electrode pad 1b at one end and electrically connected with the bump electrode 2 at the other end; and, a frame-type reinforcing member 6, supported by a tape-like substrate 4 formed exposing the opening 4e of the electrode pad 1b and reinforcing the bump electrode 2; and, the sealing portion for sealing the electrode pad 1b and the wiring 4c; in which, the reinforcing effect by the reinforcing member 6 is supported by the tape-like substrate 4 of the bump electrode 2.

Description

Semiconductor device and production technology thereof
The present invention relates to semiconductor fabrication techniques, relate to more precisely and can improve fan-in and fan-out CSP (chip size package or chip scale package part) technology of dependability.
The inventor finishes research of the present invention by it, has checked technology described below.The overview of this technology is as follows.
Known dimensions equals or the semiconductor device CSP that is slightly greater than chip is an example of the semiconductor device for the treatment of will to do thinner and forr a short time.CSP usually is installed on the printed wiring board for the treatment of to be assemblied in mobile electronic device and so on.
The general structure of CSP will be described below.CSP comprises: be equipped with as the salient pole of outside terminal on it and be equipped with the tape substrates of the lead-in wire of the splicing ear (electrode pads) that is electrically connected to semiconductor chip; The elastomer (elastomeric material) of the stress that occurs when being placed in the reduction projection installation between semiconductor chip and the tape substrates; And come the splicing ear of sealing semiconductor chips and be electrically connected to the hermetic unit of lead-in wire of the tape substrates of splicing ear with sealing resin.
Recently, to reduce cost the pin number purpose required and increase and the dwindling of chip (reducing of die size) in order to dispose, proposed a kind of CSP, its structure makes the outside that is positioned in semiconductor chip as the salient pole of outside terminal.The CSP of this structure is called as fan-in and fan-out CSP.
In for example Japanese uncensored patent application (JP-A) No.9-223759,10-79402,10-340968,6-504408 (U.S.P 5148265 and 5148266), 9-260535 (U.S. sequence number No.08/822933) and 11-87414 (U.S. sequence number No.09/113500), various fan-ins and fan-out CSP are disclosed.
At first, the disclosed CSP of JP-A-9-223759 has such structure, promptly makes polyimide film on the supporting frame of semiconductor chip and chip outside, and make a plurality of solder projections on polyimide film.
The disclosed CSP of JP-A-10-79402 has such structure, and the contour loop that is made of copper promptly is provided around chip, and contour loop and chip are connected to each other via the lead-in wire figure, and make a plurality of external connection terminals on lead-in wire figure and chip.
The disclosed CSP of JP-A-10-340968 has such structure, promptly supports to provide the resilient coating with three dimensional network structure on the substrate at chip with around the chip that chip extends, and make a plurality of solder projections on resilient coating.
The disclosed CSP of JP-A-6-504408 has the structure of using elastomer layer.
The disclosed CSP of JP-A-9-260535 has such structure, promptly via the elastomer on the semiconductor chip with around the supporting ring of chip, makes a plurality of solder projections.
The disclosed CSP of JP-A-11-87414 has such structure, promptly provides to extend on the semiconductor chip and tape substrates on every side, and semiconductor chip is fixed to tape substrates via porous elastomers, and the projection as outside terminal is provided on tape substrates.
In each CSP that is fan-in and fan-out CSP of above-mentioned various technology, projection (outside terminal) holder that is placed in the semiconductor chip outside structurally is fragile, causes the inadequate of projection to support into problem.In 6 files among disclosed each fan-in and the fan-out CSP, as described, be inadequate to the support of the projection that is placed in the semiconductor chip outside, or its manufacture method is complicated.
And, using porous elastomers to improve under the situation of anti-reflux characteristic, because the intensity of porous elastomers is low, also there is the problem that is difficult to assemble CSP with structure that projection is placed in the chip outside.
The purpose of this invention is to provide a kind of fan-in and fan-out semiconductor device and a kind of method of making this device, this device has high anti-reflux characteristic, and the salient pole that wherein is placed in outside the chip is supported reliably.
Another object of the present invention provides a kind of fan-in that can easily produce and fan-out semiconductor device and a kind of method of making this device.
From the following description of specification and accompanying drawing, above-mentioned purpose and features of novelty with other will become obvious.
In the disclosed the present invention of the application, with the overview of general introduction representative art.
Semiconductor device of the present invention comprises: be placed on the first type surface of semiconductor chip and a plurality of salient poles as outside terminal of chip first type surface outside; Be placed on the first type surface of semiconductor chip, and wherein make the poroelasticity element of the window of the splicing ear that therefrom exposes semiconductor chip; Be equipped with the lead-in wire that extends to chip outside from the first type surface of semiconductor chip, the one end is electrically connected to splicing ear and the other end is electrically connected to salient pole, and wherein is constructed for exposing the tape substrates of the window of splicing ear; Be used for strengthening fastening element to the support of the salient pole that is placed in the semiconductor chip outside; And be used for the hermetic unit of lead-in wire of the splicing ear of sealing semiconductor chips and tape substrates.
By means of the fastening element that is placed in semiconductor chip outside is provided, the support of the salient pole of chip outside is reinforced element has strengthened.Therefore, a plurality of salient poles of supporting chip outside reliably.And, because the poroelasticity component positioning is on the first type surface of semiconductor chip, so in the reflux course that semiconductor device is installed, do not form the cavity in flexible member.So can realize having the semiconductor device of excellent anti reflux characteristic.
As a result, can improve the reliability of semiconductor device.
According to the present invention, another kind of semiconductor device is provided, it comprises: have flexible member body that is placed on the semiconductor chip first type surface and the flexible member footing that extends in semiconductor chip first type surface outside, and have the flexible member that therefrom exposes the window that is produced on the splicing ear on the semiconductor chip first type surface; The lead-in wire that extends to the chip outside from the semiconductor chip first type surface is equipped with, the one end is electrically connected to splicing ear and the other end is electrically connected to the salient pole as outside terminal, and comprises the band-shaped substrate material and have the tape substrates of the window that therefrom exposes splicing ear; Be used for sealing semiconductor chips splicing ear and be connected to the hermetic unit of the lead-in wire of splicing ear; And be placed on the semiconductor chip first type surface and the salient pole as outside terminal of semiconductor chip outside, the salient pole that wherein is placed in the semiconductor chip outside is supported by the flexible member footing of tape substrates and flexible member and is reinforced.
According to the present invention, a kind of semiconductor device also is provided, it comprises: be placed on the semiconductor chip first type surface and a plurality of salient poles of chip first type surface outside; Have the flexible member body that is placed on the semiconductor chip first type surface and extend in the flexible member footing of semiconductor chip first type surface outside, and wherein be constructed for exposing the flexible member of window of the splicing ear of semiconductor chip; Be equipped with the lead-in wire that extends to chip outside from the semiconductor chip first type surface, the one end is electrically connected to splicing ear and the other end is electrically connected to salient pole, and wherein is constructed for exposing the tape substrates of the window of splicing ear; And be used for the hermetic unit of lead-in wire of the splicing ear of sealing semiconductor chips and tape substrates, wherein flexible member is made into the thickness that thickness is equal to or greater than tape substrates, and with the support of reinforcing band shape substrate to the salient pole that is placed in semiconductor chip outside of assigning to of thick flexible member reinforcing portion.
According to the present invention, a kind of semiconductor device also is provided, it comprises: extend in semiconductor chip first type surface outside and have the poroelasticity element that therefrom exposes the window that is produced on the splicing ear on the semiconductor chip first type surface; Be equipped with the lead-in wire that extends to chip outside from the semiconductor chip first type surface, the one end is electrically connected to splicing ear and the other end is electrically connected to the salient pole as outside terminal, and has the tape substrates of the window that is used for exposing splicing ear; Be used for the hermetic unit of lead-in wire of the splicing ear of sealing semiconductor chips and tape substrates; And be placed on the semiconductor chip first type surface and a plurality of salient poles of chip first type surface outside as outside terminal, wherein the band-shaped substrate material in the tape substrates is made into thicklyer than the core layer of poroelasticity element, and strengthens the support of tape substrates to the salient pole that is placed in semiconductor chip outside with thick band-shaped substrate material.
According to the present invention, provide a kind of manufacturing wherein to be positioned on the semiconductor chip first type surface and the method for the semiconductor device of chip outside as the salient pole of outside terminal, it comprises the following step: preparation is equipped with lead-in wire on one face, and wherein makes the tape substrates of the window of placing portion lead-in wire; Preparation is made into thickness and is equal to or greater than tape substrates, and has the flexible member body part of wherein making the shape window substantially the same with the window in the tape substrates and be produced on the two flexible member of flexible member footing outside the flexible member body part; Under the window in aiming at tape substrates and the situation of the window in the flexible member, that tape substrates and flexible member is bonded to each other; From two windows, expose the splicing ear of semiconductor chip, the flexible member body part is placed on the first type surface of semiconductor chip, make the flexible member footing can extend in semiconductor chip first type surface outside, and the first type surface of semiconductor chip bonded to each other and flexible member; With the splicing ear of semiconductor chip be placed in tape substrates in window in corresponding lead-in wire be connected to each other; With the splicing ear and the lead-in wire that is connected to splicing ear of resin-encapsulated semiconductor chip, thereby form hermetic unit; Making treats to be connected to the salient pole of the lead-in wire on the tape substrates one side; And with the tape substrates dicing, the support of reinforcing band shape substrate of wherein can enough thick flexible member reinforcing portion assigning to the salient pole that is placed in the semiconductor chip outside.
According to the present invention, also provide a kind of manufacturing wherein to be positioned on the semiconductor chip first type surface and the method for the semiconductor device of chip outside as the salient pole of outside terminal, it comprises the following step: preparation is equipped with lead-in wire on one face, and has the wherein tape substrates of the window of placing portion lead-in wire; The poroelasticity element of the shape window substantially the same with the window in the tape substrates is wherein made in preparation; Preparation is used for strengthening the fastening element of tape substrates to the support of the salient pole that is placed in the semiconductor chip outside; Under the window in aiming at tape substrates and the situation of the window in the flexible member, that tape substrates and flexible member is bonded to each other; Tape substrates and fastening element is bonded to each other; From two windows, expose the splicing ear of semiconductor chip, fastening element is placed in around the semiconductor chip, and the first type surface of semiconductor chip bonded to each other and flexible member; With the splicing ear of semiconductor chip be placed in tape substrates in window in corresponding lead-in wire be connected to each other; Splicing ear and the lead-in wire that is connected to splicing ear by means of with the resin-encapsulated semiconductor chip form hermetic unit; Making treats to be connected to the salient pole of the lead-in wire on side of tape substrates; And, wherein can enough fastening elements strengthen the support of tape substrates to the salient pole that is placed in the semiconductor chip outside with the tape substrates dicing.
Fig. 1 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to first embodiment of the invention, wherein not shown hermetic unit.
Fig. 2 is the profile along the A-A line of semiconductor device shown in Figure 1.
Fig. 3 is a process chart, shows the example of the process of producing semiconductor device shown in Figure 1.
Fig. 4 A-4D respectively shows the structure in each step in the technology that is used for producing semiconductor device shown in Figure 1; Fig. 4 A is a perspective view, shows tape substrates, and Fig. 4 B perspective view shows the state that flexible member is fixed, and Fig. 4 C is a perspective view, show the state that fastening element is fixed, and Fig. 4 D is a perspective view, shows the state that chip is bonded.
Fig. 5 A-5C respectively shows the structure in each step in the technology that is used for producing semiconductor device shown in Figure 1; Fig. 5 A is a perspective view, shows the state that lead-in wire is bonded, and Fig. 5 B perspective view show sealing state, and Fig. 5 C is a perspective view, shows the salient pole installment state.
Fig. 6 is a plane graph, shows the example of semiconductor device shown in Figure 1 installment state on printed circuit board (PCB) (mounting panel).
Fig. 7 is a profile, shows the installment state of semiconductor device on printed circuit board (PCB) shown in Figure 6 (mounting panel).
Fig. 8 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 1 (fan-in and fan-out CSP), wherein not shown hermetic unit.
Fig. 9 is the profile along the B-B line of semiconductor device shown in Figure 8.
Figure 10 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to second embodiment of the invention, wherein not shown hermetic unit.
Figure 11 is the profile along the C-C line of semiconductor device shown in Figure 10.
Figure 12 is a process chart, shows the example of the process of producing semiconductor device shown in Figure 10.
Figure 13 A-13C respectively shows the structure in each step in the technology that is used for producing semiconductor device shown in Figure 10; Figure 13 A is a perspective view, shows tape substrates, and Figure 13 B perspective view show the state that flexible member is fixed, and Figure 13 C is a perspective view, shows the state that chip is bonded.
Figure 14 A-14C respectively shows the structure in each step in the technology that is used for producing semiconductor device shown in Figure 10; Figure 14 A is a perspective view, shows the state that lead-in wire is bonded, and Figure 14 B perspective view show sealing state, and Figure 14 C is a perspective view, shows the salient pole installment state.
Figure 15 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 10 (fan-in and fan-out CSP), wherein not shown hermetic unit.
Figure 16 is the profile along the D-D line of semiconductor device shown in Figure 15.
Figure 17 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to third embodiment of the invention, wherein not shown hermetic unit.
Figure 18 is the profile along the E-E line of semiconductor device shown in Figure 17.
Figure 19 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 17 (fan-in and fan-out CSP), wherein not shown hermetic unit.
Figure 20 is the profile along the F-F line of semiconductor device shown in Figure 19.
Figure 21 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to fourth embodiment of the invention, wherein not shown hermetic unit.
Figure 22 is the profile along the G-G line of semiconductor device shown in Figure 21.
Figure 23 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 21 (fan-in and fan-out CSP), wherein not shown hermetic unit.
Figure 24 is the profile along the H-H line of semiconductor device shown in Figure 23.
Figure 25 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to fifth embodiment of the invention, wherein not shown hermetic unit.
Figure 26 is the profile along the I-I line of semiconductor device shown in Figure 25.
Figure 27 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 25 (fan-in and fan-out CSP), wherein not shown hermetic unit.
Figure 28 is the profile along the J-J line of semiconductor device shown in Figure 27.
Figure 29 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to sixth embodiment of the invention, wherein not shown hermetic unit.
Figure 30 is the profile along the K-K line of semiconductor device shown in Figure 29.
Describe embodiments of the invention with reference to the accompanying drawings in detail.In institute's drawings attached, specify element with identical function and the description of omitting its repetition with identical reference number.
First embodiment
The plane graph of Fig. 1 shows semiconductor device (fan-in and the fan-out CSP) example of structure according to first embodiment of the invention, wherein not shown hermetic unit.Fig. 2 is the profile along the A-A line of semiconductor device shown in Figure 1.Fig. 3 is a process chart, shows the example of the process of producing semiconductor device shown in Figure 1.Fig. 4 A-4D respectively shows the structure in each step in the technology that is used for producing semiconductor device shown in Figure 1; Fig. 4 A is a perspective view, shows tape substrates, and Fig. 4 B perspective view shows the state that flexible member is fixed, and Fig. 4 C is a perspective view, show the state that fastening element is fixed, and Fig. 4 D is a perspective view, shows the state that chip is bonded.Fig. 5 A-5C respectively shows the structure in each step in the technology that is used for producing semiconductor device shown in Figure 1; Fig. 5 A is a perspective view, shows the state that lead-in wire is bonded, and Fig. 5 B perspective view show sealing state, and Fig. 5 C is a perspective view, shows the salient pole installment state.Fig. 6 is a plane graph, shows the example of semiconductor device shown in Figure 1 installment state on printed circuit board (PCB) (mounting panel).Fig. 7 is a profile, shows the installment state of semiconductor device on printed circuit board (PCB) shown in Figure 6 (mounting panel).Fig. 8 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 1 (fan-in and fan-out CSP), wherein not shown hermetic unit.Fig. 9 is the profile along the B-B line of semiconductor device shown in Figure 8.
Semiconductor device shown in Fig. 1 and 2 (CSP 11) is the small size device that package dimension is slightly greater than chip size.CSP 11 is fan-in and fan-out type device, and wherein the first type surface 1a that is positioned in semiconductor chip 1 as a plurality of salient poles 2 of outside terminal goes up and the outside of semiconductor chip 1.
Though adopting without limits, the example of this CSP 11 is rambus DRAM (dynamic random access memory), direct rambus DRAM and so on.
The structure of CSP 11 is described below.CSP 11 comprises: the first type surface 1a that is placed in semiconductor chip 1 goes up and wherein is constructed for exposing the porous elastomers 3 (flexible member) of window 3c of the electrode pads 1b (splicing ear) of semiconductor chip 1; Extend to the chip outside and respectively have an end that is electrically connected to electrode pads 1b and a plurality of leads 4c that is electrically connected to the other end of salient pole 2 from the first type surface 1a of semiconductor chip 1; Wherein be constructed for the tape substrates 4 of the window 4e of exposed electrode solder joint 1b; Be used for strengthening fastening element 6 to the support of the salient pole 2 that is placed in semiconductor chip 1 outside; And be used for the hermetic unit 5 of lead-in wire 4c of the electrode pads 1b of sealing semiconductor chips 1 and tape substrates 4.Strengthened the support that 4 pairs of tape substrates are placed in the salient pole 2 of semiconductor chip 1 outside with fastening element 6.
Specifically, in fan-in and fan-out CSP 11, the support that 4 pairs of tape substrates are installed in the salient pole 2 in the fan-out zone (chip outside zone) is reinforced element 6 and has strengthened, thereby has improved the flatness of tape substrates 4.As a result, improved the installation reliability of CSP 11.
In the plane graph of the CSP 11 of Fig. 1,, hermetic unit shown in Figure 25 is not shown for electrode pads 1b on the semiconductor chip 1 and the lead-in wire 4c on the tape substrates 4 are shown.
Though in the plane graph of the CSP 11 of Fig. 1, omitted hermetic unit 5, in fact in the window 4e of the tape substrates 4 of CSP shown in Figure 1 11, made hermetic unit shown in Figure 25.
In the CSP 11 of first embodiment, the electrode pads 1b on the semiconductor chip 1 is positioned to a pair of side in opposite directions among the first type surface 1a that almost is parallel to semiconductor chip 1, the middle body between this opposite side.
That is the semiconductor chip 1 that is assemblied among the CSP 11 has central solder joint location.
A plurality of salient poles 2 as the outside terminal of CSP 11 (on every side 12,24 altogether) also are provided on two sides of hermetic unit 5, have become the lattice array form.Because this CSP 11 is fan-in and fan-out type, so the salient pole 2 on the first type surface 1a that is placed in semiconductor chip 1 is provided and has been placed in salient pole 2 outside the first type surface 1a of semiconductor chip 1.
As shown in Figure 2, the fastening element 6 among the CSP 11 of first embodiment is fixed to tape substrates 4 via the adhesive layer 8 in the zone, semiconductor chip 1 outside.As shown in Figure 1, fastening element 6 is continuous stiffening frames.Therefore, as shown in Figure 2, semiconductor chip 1 and elastomer 3 are positioned in the framework inboard.
Fastening element 6 needn't always continuous element.Also might use two or more a plurality of divided element, and always not disperse and be fixed to the tape substrates 4 of chip outside equably, thereby strengthen the support that 4 pairs of tape substrates are placed in the salient pole 2 in the zone, chip outside.
Fastening element 6 is made by for example polyimide resin, and is made thick for reinforcing.When the band-shaped substrate material 4g in the tape substrates 4 is made by polyimide resin, preferably will be set at about 100-175 micron as the gross thickness of the polyimide resin of the band-shaped substrate material 4g in fastening element of making by polyimide resin 6 and the tape substrates 4.Arrange with this, can strengthen the support that 4 pairs of tape substrates are placed in the salient pole 2 of chip outside.
Fastening element 6 also can be by making such as the metal material of aluminium or copper.At this moment, fastening element 6 can be made thinlyyer.
In the tape substrates 4 of the CSP 11 of first embodiment, the rectangular window 4e that is elongated that almost is parallel to a pair of profile side in opposite directions is fabricated on the mid portion between the side.Therefore, when the first type surface 1a of semiconductor chip 1 is fixed to elastomer 3, as shown in Figure 1, aims at a plurality of electrode pads 1b that are placed in the line with central solder joint and be exposed from window 4e.
Tape substrates 4 among the CSP 11 of first embodiment has corresponding to the substrate bulk 4a in the zone of the first type surface 1a of semiconductor chip 1 and the substrate ledge 4b in zone that extends to the outside corresponding to the first type surface 1a from semiconductor chip 1.When semiconductor chip 1 was adhered to elastomer 3, substrate bulk 4a, elastomer 3 and semiconductor chip 1 were stacked, and the substrate ledge 4b of tape substrates 4 is outstanding around semiconductor chip.The fastening element 6 of frame shape is fixed on the opposite face of the face with salient pole is installed of substrate ledge 4b via adhesive layer 8.
Elastomer 3 is made into little as to be enough to place within the framework of fastening element 6.Elastomer 3 is to be placed between tape substrates 4 and the semiconductor chip 1 and the insulation flexible member that is used for supporting semiconductor chip 1 that contacts with the first type surface 1a of semiconductor chip 1.
Below describe the structure and material of each element in detail.
At first, in tape substrates 4, on salient pole installation side, provide to be electrically connected to lead-in wire 4c and a plurality of projection island 4f of installation salient pole 2 it on as the band-shaped substrate material 4g of the base material of tape substrates 4.
Tape substrates 4 also has the band-shaped substrate material 4g that is made by polyimide resin.As shown in Figure 2, on the face side of band-shaped substrate material 4g, make the lead-in wire 4c (comprising projection island 4f) that makes by the metal forming such as Copper Foil.Cover lead-in wire 4c with thin Au coating, Au/Ni coating or Pd coating.Use dielectric film such as scolder protective layer 4h to cover the face side of the band-shaped substrate material 4g comprise coating.The coating that covers lead-in wire 4c is that for example thickness is (for example, Au/Ni=3.0/0.5 micron (semiconductor chip side) and 0.3/0.5 micron (salient pole side)) coating that 1.5 microns two-sided Au coating or the thickness on its semiconductor chip side and the thickness on the salient pole side differ from one another.
The lip-deep wire structures of making the tape substrates 4 of lead-in wire 4c on it of this band-shaped substrate material 4g is called as the surface wiring structure.In CSP shown in Figure 2 11, tape substrates 4 has the surface wiring structure.Tape substrates 4 among the CSP 11 of first embodiment can also have the back wiring structure, and lead-in wire 4c is fabricated on the rear side of band-shaped substrate material 4g.
By this way, the window 4d of projection is fabricated among the scolder protective layer 4h position corresponding to projection island 4f.By means of salient pole 2 being placed among the window 4d of projection, salient pole 2 is electrically connected to each other via projection island 4f with lead-in wire 4c.
Elastomer 3 is a kind of multihole devices and has by core layer 3d (being also referred to as basalis etc.) and be produced on the surface of core layer 3d and three-decker (referring to Figure 11) that the adhesive layer 3e on the back side forms.At this moment, core layer 3d is made by porous fluoroplastics and so on, and adhesive layer 3e is made by epoxy resin impregnated porous fluoroplastics and so on.
Core layer 3d by means of forming the elastomer of being made up of the porous fluoroplastics 3 can improve air permeability and drainage.
Elastomer that the porous fluoroplastics are made 3 is made of three dimensional network structure, and this is a kind of by means of the non-woven fibre made from three dimensional constitution entangled fiber compound.
Form hermetic unit 5 (referring to Fig. 5) by means of sealing with electrode pads 1b on 9 pairs of semiconductor chips 1 of sealing resin and the lead-in wire 4c that is connected to electrode pads 1b.
Though the sealing resin 9 as the encapsulant of hermetic unit 5 has than higher viscosity, but it is longer by means of the traveling time that makes pouring nozzle 10 (referring to Fig. 5) when applying, make coating time lengthening, sealing resin is heated etc., still can use sealing resin 9 with high viscosity.
The residual stress that is caused by contraction when solidifying in order to suppress sealing resin is preferably used and is contained the resin of silica as sealing resin 9.
The examples of material of salient pole 2 is low eutectic solder, other scolders such as the Ni of Sn/Ag, Sn/Ag/Cu, Sn/Ag/Bi/Cu, Sn/Ag/Bi and Sn/Bi/Cu, plating Au that Sn/Pb forms.The diameter of material is about 0.3-0.6mm.
The embodiment of the CSP 11 of first embodiment is described below with reference to Fig. 6 and 7.
Fig. 6 and 7 shows the example that CSP 11 is installed on the circuit board product such as memory printed circuit.Use reflow method, a plurality of CSP 11 are installed on the same mounting panel 22 with the surface installing type packaging part such as QFP (quad flat package part) 21.Mounting panel 22 is printed circuit board (PCB)s for example.Treat that a plurality of outside contact lead-wire 22a that will be electrically connected to external devices is provided on the end of mounting panel 22.
With reference to Fig. 1-5, describe according to the production fan-in of first embodiment and the technology of fan-out CSP 11 (semiconductor device) according to the process chart of Fig. 3 below.
At first, preparation has the 4c that wherein goes between shown in Fig. 4 A is provided at the surface wiring structure on the face (owing to use the surface wiring structure, being the surface) and is mounted with the part of each 4c that goes between in first embodiment the tape substrates 4 (being also referred to as flexible distributing board) of window 4e.
The a plurality of lead-in wire 4c that are provided on the tape substrates 4 are made along the Width of rectangular window 4e, so that extend in inside and outside the window 4e.
Again on tape substrates 4, on surface, make the lead-in wire 4c that makes by the metal forming such as Copper Foil as the band-shaped substrate material 4g of the base material of tape substrates 4.Cover lead-in wire 4c with thin Au coating, Au/Ni coating or Pd coating.Use dielectric film such as scolder protective layer 4h to cover the face side of the band-shaped substrate material 4g comprise coating.
Be used for the band-shaped substrate material 4g of the tape substrates 4 of CSP 11, make by for example polyimide resin.
On the other hand, the preparation porous elastomers 3, window 3c wherein have with tape substrates 4 in the almost completely identical shape of window 4e.
Preparation is used for strengthening the frame shape fastening element 6 of support that 4 pairs of tape substrates are placed in the salient pole 2 of semiconductor chip 1 outside again.
Make by for example polyimide resin though be used for the fastening element 6 of the CSP 11 of this embodiment, also can use element of making by the metal material outside the polyimide resin or the element that obtains by means of with Ni, Sn, on hardware, carrying out the anticorrosion electroplating technology such as aluminium (Al) or copper (Cu).
And, when fastening element 6 is made by polyimide resin, also can use becoming the gross thickness of the polyimide resin of the polyimide resin of fastening element 6 and band-shaped substrate material 4g is 100 microns or thicker, preferably the tape substrates 4 of 100-175 micron and fastening element 6.
Then, window 4e in the aligning tape substrates 4 and the window 3c in the elastomer 3, and tape substrates 4 and elastomer 3 is bonded to each other.
In this stage, " the bonding elastomer " in the execution graph 3 among the step S1.
Specifically, window 4e in the tape substrates 4 and the window 3c in the elastomer 3 are aligned, and elastomer 3 is bonded to tape substrates 4 via adhesive layer 8, thereby obtain the state shown in Fig. 4 B.
Then, frame shape fastening element 6 is positioned in around the elastomer 3, and tape substrates 4 is bonded via adhesive layer 8 with fastening element 6.
That is by means of " bonding fastening element " among the execution in step S2, frame shape fastening element 6 is bonded to the ledge 4b of tape substrates 4.
Therefore, shown in Fig. 4 C, obtained the state in the framework that elastomer 3 is positioned in fastening element 6.
Can with bonding elastomer 3 simultaneously or before it, carry out the bonding of fastening element 6 and tape substrates 4.
That is, can following change step S1 shown in Figure 3 and the order of S2.Before bonding elastomer 3, at first via adhesive layer 8 bonding tape substrates 4 and fastening element 6.Then, elastomer 3 is placed in the inside of frame shape fastening element 6, and under the situation of alignment windows 4e and 3e, makes tape substrates 4 and elastomer 3 bonded to each other.
In step S3, carry out then " bonding chip ".
Specifically, be positioned in the frame shape fastening element 6 at semiconductor chip 1, and under the situation that a plurality of electrode pads 1b on the first type surface 1a of semiconductor chip 1 are exposed by 3c and two windows of 4e, the first type surface 1a of semiconductor chip 1 and elastomer 3 via adhesive layer 3e by (referring to Figure 11) bonded to each other.
Therefore, shown in Fig. 4 D, obtained frame shape fastening element 6 be positioned in semiconductor chip 1 around, and semiconductor chip 1 is adhered to the state of elastomer 3.
In step S4, carry out then " bonding wire ".
Specifically, the electrode pads 1b on the semiconductor chip 1 and be placed in that the lead-in wire 4c among the respective window 4e is connected to each other in the tape substrates 4.
Shown in Fig. 5 A, the window 4e in the tape substrates 4 is arranged to up.By means of the single-point leading wire bonding that uses bonding tool 7, lead-in wire 4c is connected to electrode pads 1b.
At this moment, bonding tool 7 at first is positioned in the predetermined leads 4c top among the window 4e, descends then, so that pressurization and load is applied to lead-in wire 4c.Lead-in wire 4c is loaded to pressurize and cutting.
Relend and help continued operation bonding tool 7, the lead-in wire 4c that is cut is pressed towards the electrode pads 1b on the semiconductor chip 1.By means of thermocompression bonding (use ultrasonic wave) and so on, lead-in wire 4c and electrode pads 1b are connected to each other.
Carry out the operation of bonding tool 7 on the 4c repeatedly at each lead-in wire, thus one by one connection electrode solder joint 1b and corresponding lead-in wire 4c.
In step S5, form then " sealing ".
Specifically, with resin electrode pads 1b on the semiconductor chip 1 and the lead-in wire 4c that is connected to electrode pads 1b are sealed, thereby form hermetic unit shown in Figure 25.
Shown in Fig. 5 B, use irrigation method, will be as the sealing resin 9 of encapsulant, drip to window 4e the tape substrates 4 from pouring nozzle 10, thereby with the lead-in wire 4c that is connected to electrode pads 1b on electrode pads 1b on the resin-encapsulated semiconductor chip 1 and the tape substrates 4.
After the process preset time, sealing resin 9 is cured, thereby forms hermetic unit 5.In step S6, carry out then " making projection ".
Specifically, be fabricated on the projection island 4f of the lead-in wire 4c on the face (surface) for the treatment of to be connected to tape substrates 4 as the salient pole 2 of outside terminal.
At first, shown in Fig. 5 C, solder ball 23 is supplied to the projection window 4d among the scolder protective layer 4h of tape substrates 4.Then, as shown in Figure 2, reflux by means of carrying out, salient pole 2 is fabricated on the projection island 4f.
Then, in step S7, mark.
For example, on fastening element and so on, the mark of printed product model and so on.
In step S8, carry out then " cutting into packaging part ".
Specifically, utilize cutter and so on, tape substrates 4 is cut into packaging part, thereby obtain the CSP 11 of required size in the precalculated position.
In step S9, carry out then " test ", thereby finish CSP 11.
By this way, can access fan-in and fan-out CSP 11, wherein the support that is placed in the salient pole 2 of semiconductor chip 1 outside of 4 pairs of tape substrates is reinforced element 6 and has strengthened.
According to the fan-in of first embodiment and the method for fan-out CSP 11 and manufacturing CSP 11.Can access following effect and effect.
That is by means of the fastening element 6 that is placed in semiconductor chip 1 outside is provided, tape substrates is reinforced element 6 to the support of the salient pole 2 of chip outside and has strengthened.So, a plurality of salient poles 2 of supporting chip outside reliably.
And, by means of porous elastomers 3 being placed on the first type surface 1a of semiconductor chip 1, in the reflux course of making salient pole, or in the reflux course that CSP 11 is installed, in elastomer 3, do not form the cavity.Because the steam that produces in the hermetic unit 5 can be discharged to the outside effectively, so can prevent that backflow is broken that is appearance that CSP bothers in installing.
So, can access fan-in that prevents reflux characteristic and fan-out CSP 11 with excellence.
And, because the drainage of the fluorine in the porous fluoroplastics of elastomer 3 invades among the CSP 11 so can prevent moisture.So can reduce degenerating of fan-in and fan-out CSP 11 characteristics.
As a result, can realize having excellent fan-in that prevents reflux characteristic and high reliability and fan-out CSP 11, wherein a plurality of salient poles 2 of supporting chip outside reliably.
In the fan-in and fan-out CSP 11 of first embodiment, gross thickness by means of the polyimides of the band-shaped substrate material 4g in fastening element that polyimide resin is made 6 and the tape substrates 4 is set at the 100-175 micron, tape substrates 4 can be reinforced element 6 and reinforce, thereby can strengthen the robustness of tape substrates 4 itself.
As a result, the salient pole 2 of chip outside can be supported more reliably by tape substrates 4.
In the fan-in and fan-out CSP 11 of first embodiment, used the tape substrates 4 of surface wiring structure.Therefore, can in scolder protective layer 4h, make the window 4d of projection, and need not in band-shaped substrate material 4g, make window 4d.
Because band-shaped substrate material 4g thereby can be made thick, so can strengthen the part that is projected into semiconductor chip 1 outside in the tape substrates 4 that is the intensity of substrate ledge 4b.
So, can strengthen support with fastening element 6 to the salient pole 2 that is placed in chip outside.As a result, can improve the reliability of fan-in and fan-out CSP 11.
Owing to can in fan-in and fan-out CSP 11, strengthen being placed in the support of the salient pole 2 outside the chip, so littler and thinner CSP 11 can be installed in the portable little and thin electronic device such as cell-phone.
Structure (referring to Fig. 8 and 9) as a kind of improved CSP 12 of the CSP 11 of first embodiment is described below.
CSP 11 has central solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is positioned in middle body.On the contrary, the CSP 12 shown in Fig. 8 and 9 has peripheral solder joint location, and wherein electrode pads 1b is positioned in the periphery of semiconductor chip 1.
In the improved CSP 12 as first embodiment, as shown in Figure 8, the electrode pads 1b on the semiconductor chip 1 is positioned to a pair of side in opposite directions among the first type surface 1a that almost is parallel to semiconductor chip 1, so that in the periphery of first type surface 1a toward each other.
Fig. 9 is the profile along the B-B line of the CSP 12 of Fig. 8.
Central solder joint location by means of the electrode pads 1b on the semiconductor chip 1 that replaces with peripheral solder joint location among the CSP 11 shown in Fig. 1 and 2 has obtained the improved CSP 12 shown in Fig. 8 and 9.
In CSP 12, a pair of side in opposite directions along the first type surface 1a of semiconductor chip 1 is aligned electrode pads 1b in first type surface 1a periphery.Therefore, therefrom expose the window 4e of two elongations of the electrode pads 1b in the row, be fabricated in the tape substrates 4.Zone between two window 4e is corresponding to substrate bulk 4a, and the zone of window 4e outside is substrate ledge 4b.
As shown in Figure 9, because porous elastomers 3 is positioned between in opposite directions the electrode pads group 1b, so electrode pads group 1b can be positioned in two sides of elastomer 3.In the elastomer 3 in CSP 12, do not make the window 3c among the CSP 11.
Because the structural similarity of the electrode pads 1b among the CSP 12 except aiming at is in CSP11, so located to omit the description that repeats.
Because effect that the method for manufacturing CSP 12 and CSP 12 and manufacture method thereof obtain and effect are also similar in appearance to CSP 11, so located to omit the description that repeats.
Second embodiment
Figure 10 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to second embodiment of the invention, wherein not shown hermetic unit.Figure 11 is the profile along the C-C line of semiconductor device shown in Figure 10.Figure 12 is a process chart, shows the example of the process of producing semiconductor device shown in Figure 10.Figure 13 A-13C respectively shows the structure in each step in the technology that is used for producing semiconductor device shown in Figure 10; Figure 13 A is a perspective view, shows tape substrates, and Figure 13 B perspective view show the state that flexible member is fixed, and Figure 13 C is a perspective view, shows the state that chip is bonded.Figure 14 A-14C respectively shows the structure in each step in the technology that is used for producing semiconductor device shown in Figure 10; Figure 14 A is a perspective view, shows the state that lead-in wire is bonded, and Figure 14 B perspective view show sealing state, and Figure 14 C is a perspective view, shows the salient pole installment state.Figure 15 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 10 (fan-in and fan-out CSP), wherein not shown hermetic unit.Figure 16 is the profile along the D-D line of semiconductor device shown in Figure 15.
The CSP 13 (semiconductor device) of second embodiment is fan-in and the fan-out type device similar in appearance to the central solder joint of having of the CSP 11 of first embodiment shown in Figure 1 location.The difference of the CSP 13 of second embodiment and the CSP 11 of first embodiment is as follows.Fastening element 6 is not provided, but makes the core layer 3d of elastomer 3 of polyimide resin.Change relevantly therewith, determine the gross thickness of polyimide resin with the band-shaped substrate material 4g of tape substrates 4 of core layer 3d, thereby 4 pairs of tape substrates of enhancing are placed in the support of the salient pole 2 outside the chip.
Therefore, elastomer 3 comprises elastomeric body (body of the elastomer element) 3a on the first type surface 1a that is placed in semiconductor chip 1 and extends in the elastomer footing 3b of the first type surface 1a outside of semiconductor chip 1.
Elastomeric body 3a is corresponding to the substrate bulk 4a of the tape substrates 4 on the first type surface 1a that is placed in semiconductor chip 1.And elastomer footing 3b is positioned to the substrate ledge 4b that extends corresponding to the first type surface 1a from semiconductor chip 1.As a result, to the support of the salient pole 2 that is placed in semiconductor chip 1 outside, strengthened by strip material substrate 4g in the tape substrates 4 and the elastomer footing 3b in the elastomer 3.
In CSP 13, the two is made the band-shaped substrate material 4g of the core layer 3d of elastomer 3 and tape substrates 4 by polyimide resin.For example, to be deposited into thickness be 50-125 micron (such as 50 microns, 75 microns or 125 microns) to the core layer 3d of elastomer 3.On the other hand, the band-shaped substrate material 4g of tape substrates 4 is made into thickness and is about 50 microns.Therefore, the gross thickness of the polyimide resin of the band-shaped substrate material 4g of the polyimide resin of the core layer 3d of elastomer 3 and tape substrates 4 is set to the 100-175 micron.
Utilize the gross thickness of two polyimide resin layers, can strengthen the holding strength that 4 pairs of tape substrates are placed in the salient pole 2 of semiconductor chip 1 outside.
Because the polyimide resin of band-shaped substrate material 4g must be made thickly, so the wire structures of the tape substrates 4 among the CSP 13 is surface wiring structures.
Specifically, utilize the surface wiring structure, the lead-in wire 4c that is made by Copper Foil is fabricated on the surface (face opposite with the face that is bonded to elastomer 3) of band-shaped substrate material 4g, the window 4d of projection can be fabricated among the scolder protective layer 4h.Therefore, band-shaped substrate material 4g can be made thick.
Therefore, CSP 13 has used the tape substrates 4 of surface wiring structure.
Because other structural similarity among the CSP 13 of second embodiment is in the described CSP 11 of first embodiment, so located to omit the description that repeats.
With reference to Figure 10-14, describe according to the production fan-in of second embodiment and the technology of fan-out CSP 13 (semiconductor device) according to the process chart of Figure 12 below.
At first, in the mode similar in appearance to first embodiment, the tape substrates 4 (being also referred to as flexible distributing board) of the surface wiring structure shown in preparation Figure 13 A wherein provides lead-in wire 4c on a face (surface), and makes the wherein window 4e of placing portion lead-in wire 4c.
In the tape substrates 4 that is used for CSP 13, band-shaped substrate material 4g is made by for example polyimide resin.And, because band-shaped substrate material 4g must make thickly, so adopted the surface wiring structure.
On the other hand, the preparation elastomer 3, wherein make shape almost with tape substrates 4 in the identical window 3c of window 4e.The core layer 3d that elastomer 3 comprises elastomeric body 3a and elastomer footing 3b and made by polyimide resin.
For example, use tape substrates 4 and elastomer 3, making the core layer 3d of elastomer 3 be made into thickness is the 50-125 micron, and being made into thickness, the band-shaped substrate material 4g of tape substrates 4 is about 50 microns, so that the gross thickness of the polyimide resin of the band-shaped substrate material 4g of the polyimide resin of the core layer 3d of elastomer 3 and tape substrates 4 becomes the 100-175 micron.
Then, window 4e in the aligning tape substrates 4 and the window 3c in the elastomer 3, and tape substrates 4 and elastomer 3 is bonded to each other.
In this stage, carry out " elastomer bonding " among the step S1 among Figure 12.
Specifically, window 4e in the tape substrates 4 and the window 3c in the elastomer 3 are aligned, and elastomer 3 is bonded to tape substrates 4 via adhesive layer 8, thereby obtain the state shown in Figure 13 B.
In step S2, carry out then " bonding of chip ".
Specifically, under the situation that a plurality of electrode pads 1b on the first type surface 1a of semiconductor chip 1 are exposed by 3c and two windows of 4e, the first type surface 1a and the elastomer 3 of semiconductor chip 1 are bonded via adhesive layer 3e.
Therefore, shown in Figure 11 and 13C, be extended under the situation around the semiconductor chip 1 at substrate ledge 4b and elastomer footing 3b, semiconductor chip 1 is adhered to elastomer 3.
In step S3, carry out then " bonding of lead-in wire ".
Specifically, electrode pads 1b on the semiconductor chip 1 and the respective lead 4c that is placed among the corresponding window 4e in the tape substrates 4 are connected to each other.
Shown in Figure 14 A, the window 4e in the tape substrates 4 is arranged to up.By means of the single-point leading wire bonding that uses bonding tool 7, lead-in wire 4c is connected to electrode pads 1b.
At this moment, in the mode similar in appearance to first embodiment, bonding tool 7 is positioned on the predetermined leads 4c among the window 4e, descends then, so that pressurization and load is applied to lead-in wire 4c.Lead-in wire 4c is loaded to pressurize and cutting.
Relend and help continued operation bonding tool 7, the lead-in wire 4c that is cut is pressed towards the electrode pads 1b on the semiconductor chip 1.By means of thermocompression bonding (use ultrasonic wave) and so on, lead-in wire 4c and electrode pads 1b are connected to each other.
Carry out the operation of bonding tool 7 on the 4c repeatedly at each lead-in wire, thus one by one connection electrode solder joint 1b and corresponding lead-in wire 4c.
In step S4, form then " sealing ".
Specifically, with resin electrode pads 1b on the semiconductor chip 1 and the lead-in wire 4c that is connected to electrode pads 1b are sealed, thereby form hermetic unit shown in Figure 11 5.
As shown in Figure 14B, use irrigation method, will be as the sealing resin 9 of encapsulant, drip to window 4e the tape substrates 4 from pouring nozzle 10, thereby with the lead-in wire 4c that is connected to electrode pads 1b on electrode pads 1b on the resin-encapsulated semiconductor chip 1 and the tape substrates 4.
After the process preset time, sealing resin 9 is cured, thereby forms hermetic unit 5.In step S5, carry out " making of projection " then.
Specifically, be fabricated on the projection island 4f of the lead-in wire 4c on the face (surface) for the treatment of to be connected to tape substrates 4 as the salient pole 2 of outside terminal.
At first, shown in Figure 14 C, solder ball 23 is supplied to the projection window 4d among the scolder protective layer 4h of tape substrates 4.Then, as shown in figure 11, salient pole 2 is fabricated on the projection island 4f.
Then, in step S6, mark.
For example, on elastomer 3 grades, do the mark of product type and so on.
In step S7, carry out then " cutting into packaging part ".
Specifically, utilize cutter and so on, tape substrates 4 is cut into packaging part, thereby obtain the CSP 13 of required size in the precalculated position.
In step S8, carry out then " test ", thereby finish CSP 13.
By this way, can access fan-in and fan-out CSP 13, wherein the support that is placed in the salient pole 2 of semiconductor chip 1 outside of 4 pairs of tape substrates has been strengthened by the core layer 3d of the band-shaped substrate material 4g of tape substrates 4 and elastomer 3.
According to the fan-in of second embodiment and the method for fan-out CSP 13 and manufacturing CSP 13.Can access following effect and effect.
That is, by means of provide tape substrates 4 and from semiconductor chip 1 extend to the outside elastomer 3, and being set at the 100-175 micron by means of gross thickness with the polyimide resin of the polyimide resin of the band-shaped substrate material 4g in the tape substrates 4 and the core layer 3d in the elastomer 3, the salient pole 2 that is placed in the chip outside can be supported reliably and need not be provided for the fastening element 6 of CSP shown in Figure 1 11.
Owing in CSP 13, used the tape substrates 4 of surface wiring structure, so the band-shaped substrate material 4g that is made by polyimide resin in the tape substrates 4 can be made thick, as a result, can strengthen the support that 4 pairs of tape substrates are placed in the salient pole 2 of chip outside.
Owing to need not use fastening element 6 just can assemble CSP 13, so can simplify the production (assembling) of fan-in and fan-out CSP 13.
Therefore, can realize fan-in and fan-out CSP 13 that produce easily and that a plurality of salient poles 2 its chips outside are supported reliably.
Because CSP 13 does not use fastening element 6, so than it CSP shown in Figure 1 11, cost has been lowered.
And, owing to the core layer 3d in the elastomer 3 is made by polyimide resin, so the porous elastomers 3 that compares can reduce cost.Thereby can reduce the cost of CSP 13.
Structure (referring to Figure 15 and 16) as the improved CSP 14 of the CSP 13 of second embodiment is described below.
CSP 13 has central solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is aligned at middle body.On the contrary, the CSP 14 shown in Figure 15 and 16 has peripheral solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is aligned at the periphery.
In the improved CSP 14 as second embodiment, as shown in figure 15, the electrode pads 1b on the semiconductor chip 1 is positioned to a pair of side in opposite directions among the first type surface 1a of the semiconductor chip 1 in the periphery that almost is parallel to first type surface 1a, so that toward each other.
Figure 16 is the profile along the D-D line of the CSP 14 of Figure 15.
Central solder joint location by means of aim at the electrode pads 1b on the semiconductor chip 1 that replaces among the CSP 13 shown in Figure 10 and 11 with peripheral solder joint has obtained the improved CSP 14 of the conduct shown in Figure 15 and 16.
In CSP 14, electrode pads 1b is aligned along a pair of side in opposite directions among the first type surface 1a of semiconductor chip 1 in first type surface 1a periphery.Therefore, therefrom expose the window 4e of two elongations of the electrode pads 1b in the row, be fabricated in the tape substrates 4.Zone between two window 4e is corresponding to substrate bulk 4a, and the zone of window 4e outside is substrate ledge 4b.
As shown in figure 16, corresponding to tape substrates 4, elastomer 3 comprises: be placed in elastomeric body part 3a on the first type surface 1a of semiconductor chip 1 (two window 3c between zone); And the footing 3b (zone of window 3c outside) that extends in the first type surface 1a outside of semiconductor chip 1.
That is, elastomeric body part 3a is corresponding to the substrate bulk part 4a in the tape substrates 4 on the first type surface 1a that is placed in semiconductor chip 1, and elastomer footing 3b is positioned in from the substrate ledge 4b of the first type surface 1a extension of semiconductor chip 1.Therefore, 4 pairs of tape substrates are placed in the support of the salient pole 2 of semiconductor chip 1 outside, have been strengthened by band-shaped substrate material 4g in the tape substrates 4 and the elastomer footing 3b in the elastomer 3.
Because the structural similarity of the electrode pads 1b among the CSP 14 except the location is in CSP13, so located to omit the description that repeats.
Because effect that the method for manufacturing CSP 14 and CSP 14 and manufacture method thereof obtain and effect are also similar in appearance to CSP 13, so located to omit the description that repeats.
The 3rd embodiment
Figure 17 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to third embodiment of the invention, wherein not shown hermetic unit.Figure 18 is the profile along the E-E line of semiconductor device shown in Figure 17.Figure 19 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 17 (fan-in and fan-out CSP), wherein not shown hermetic unit.Figure 20 is the profile along the F-F line of semiconductor device shown in Figure 19.
The CSP 15 (semiconductor device) of the 3rd embodiment is fan-in and the fan-out type device similar in appearance to the central solder joint of having of the CSP 13 of second embodiment shown in Figure 11 location.The difference of the CSP 15 of the 3rd embodiment and the CSP 13 of second embodiment is: utilize the elastomer 3 make thickly, strengthened the support that 4 pairs of tape substrates are placed in the salient pole 2 of chip outside.
Similar to CSP 13, elastomer 3 comprises elastomeric body (body of the elastomer element) 3a on the first type surface 1a that is placed in semiconductor chip 1 and extends in the elastomer footing 3b (elastomer element footing) of the first type surface 1a outside of semiconductor chip 1.
Elastomeric body 3a is corresponding to the substrate bulk 4a in the tape substrates 4 on the first type surface 1a that is placed in semiconductor chip 1.And elastomer footing 3b is positioned in from the substrate ledge 4b of the first type surface 1a extension of semiconductor chip 1.As a result, to the support of the salient pole 2 that is placed in semiconductor chip 1 outside, be made thick elastomer footing 3b and strengthen.
Elastomer 3 among the CSP 15 has by core layer 3d and is produced on the three-decker that the adhesive layer 3e on two faces of core layer 3d forms.These layers example of thickness separately are as follows.Core layer 3d is 50 micron thickness, and the adhesive layer 3e on the chip side is 50 micron thickness, and the adhesive layer 3e on the band side is 75 micron thickness (175 micron thickness altogether).In another example, core layer 3d is 75 micron thickness, and the adhesive layer 3e on the chip side is 50 micron thickness, and the adhesive layer 3e on the band side is 75 micron thickness (200 micron thickness altogether).In another example, core layer 3d is 125 micron thickness, and the adhesive layer 3e on the chip side is 50 micron thickness, and the adhesive layer 3e on the band side is 75 micron thickness (250 micron thickness altogether).
In CSP 15, the core layer 3d in the elastomer 3 is made by polyimide resin.Band-shaped substrate material 4g in the tape substrates 4 is also made by polyimide resin.For example, as mentioned above, it is the 50-125 micron that the core layer 3d in the elastomer 3 is made into thickness.On the other hand, the band-shaped substrate material 4g in the tape substrates 4 is made into thinner, and thickness is about 50 microns.
In the CSP 15 of the 3rd embodiment, about the relation of the thickness of the thickness of elastomer 3 and tape substrates 4, it is just enough that the thickness of elastomer 3 is equal to or greater than the thickness of tape substrates 4.
Therefore, utilize the elastomer footing 3b in the elastomer of making thickly 3, can strengthen the holding strength that 4 pairs of tape substrates are placed in the salient pole 2 of semiconductor chip 1 outside.
Tape substrates 4 among the CSP 15 has back of the body surface wiring structure.
That is the lead-in wire 4c that is made by Copper Foil is fabricated on the back side (being bonded to the face of elastomer 3) of the band-shaped substrate material 4g in the tape substrates 4.
Because other structural similarity among the CSP 15 of the 3rd embodiment is in the structure of the described CSP 13 of second embodiment, so located to omit the description of its repetition.
The method of making CSP 15 among the 3rd embodiment is identical with the method for manufacturing CSP13 among second embodiment basically.Its difference is as follows.Owing to used the tape substrates 4 of back wiring structure, so when the salient pole 2 as outside terminal is produced on the tape substrates 4, salient pole 2 is electrically connected to lead-in wire 4c via the projection window 4d in the projection installation site that is provided among the band-shaped substrate material 4g.
When tape substrates 4 and semiconductor chip 1 via making thickly elastomer 3 when bonded, substrate ledge 4b in the tape substrates 4 and the elastomer footing 3b in the elastomer 3 extend to the outside from the whole periphery of semiconductor chip 1.
Because except that above-mentioned, the manufacture method of the CSP 15 of the 3rd embodiment is repeated in this description so locate to have omitted it similar in appearance to the manufacture method of the CSP 13 of second embodiment.
According to the fan-in of the 3rd embodiment and the method for fan-out CSP 15 and manufacturing CSP 15, can access following effect and effect.
That is, by means of the tape substrates 4 that extends to the outside from semiconductor chip 1 is provided, and the tape substrates 4 of utilizing the back wiring structure, it is thick that elastomer 3 can be made.As a result, even when tape substrates 4 is made thin, also can supports to be placed in the salient pole 2 of chip outside reliably, and the fastening element that is used for CSP 11 6 shown in Figure 1 need not be provided.
Utilize the tape substrates 4 of back wiring structure, it is thick that elastomer 3 can be made, and the window 4d of projection directly is produced among the band-shaped substrate material 4g and such scolder protective layer 4h in need not the surface wiring structure.So, can simplify the manufacturing process of the tape substrates 4 in the technology of producing CSP 15.
As a result, can reduce the cost of producing CSP 15.
And, because tape substrates 4 do not need scolder protective layer 4h, thus the cost of tape substrates 4 own can be reduced, thereby can reduce the cost of CSP 15.
Band-shaped substrate material 4g in the tape substrates 4 can be made thick.At this moment, because elastomer 3 also is made thick, so can strengthen substrate ledge 4b in the tape substrates 4 and the robustness of elastomer footing 3b.As a result, can support to be placed in the salient pole 2 of chip outside reliably.
Because the core layer 3d in the elastomer 3 is made by polyimide resin, so the porous elastomers 3 that compares, cost can be lower.Thereby can reduce the cost of CSP 15.
Structure (referring to Figure 19 and 20) as the improved CSP 16 of the CSP 15 of the 3rd embodiment is described below.
CSP 15 has central solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is aligned at middle body.On the contrary, the CSP 16 shown in Figure 19 and 20 has peripheral solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is aligned at the periphery.
In the improved CSP 16 as the 3rd embodiment, as shown in figure 19, the electrode pads 1b on the semiconductor chip 1 is positioned to a pair of side in opposite directions among the first type surface 1a of the semiconductor chip 1 in the periphery that almost is parallel to first type surface 1a, so that toward each other.
Figure 20 is the profile along the F-F line of the CSP 16 of Figure 19.
Central solder joint location by means of the electrode pads 1b on the semiconductor chip 1 that replaces with peripheral solder joint location among the CSP 15 shown in Figure 17 and 18 has obtained the improved CSP 16 of the conduct shown in Figure 19 and 20.
In CSP 16, electrode pads 1b is aligned along a pair of side in opposite directions among the first type surface 1a of semiconductor chip 1 in first type surface 1a periphery.Therefore, therefrom expose the window 4e of two elongations of the electrode pads 1b in the row, be fabricated in the tape substrates 4.Zone between two window 4e is corresponding to substrate bulk 4a, and the zone of window 4e outside is substrate ledge 4b.
As shown in figure 20, corresponding to tape substrates 4, elastomer 3 comprises: be placed in elastomeric body part 3a on the first type surface 1a of semiconductor chip 1 (two window 3c between zone); And the elastomer footing 3b (zone of window 3c outside) that extends in the first type surface 1a outside of semiconductor chip 1.
That is elastomeric body part 3a is corresponding to the substrate bulk part 4a in the tape substrates 4 on the first type surface 1a that is placed in semiconductor chip 1, and, the substrate ledge 4b that elastomer footing 3b extends corresponding to the first type surface 1a from semiconductor chip 1.Therefore, 4 pairs of tape substrates are placed in the support of the salient pole 2 of semiconductor chip 1 outside, by the band-shaped substrate material 4g in the tape substrates 4 and the elastomer footing 3b in making thickly elastomer 3 strengthened.
Because the structural similarity among the CSP 16 except the location of electrode pads 1b is in CSP15, so located to omit the description that repeats.
Because effect that the method for manufacturing CSP 16 and CSP 16 and manufacture method thereof obtain and effect are also similar in appearance to CSP 15, so located to omit the description that repeats.
The 4th embodiment
Figure 21 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to fourth embodiment of the invention, has wherein omitted hermetic unit.Figure 22 is the profile along the G-G line of semiconductor device shown in Figure 21.Figure 23 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 21, has wherein omitted hermetic unit.Figure 24 is the profile along the H-H line of semiconductor device shown in Figure 23.
The CSP 17 (semiconductor device) of the 4th embodiment is fan-in and the fan-out type device similar in appearance to the central solder joint of having of the CSP 13 of second embodiment shown in Figure 10 location.Be to have used porous elastomers 3 with the difference of the CSP 17 of the CSP 13 of second embodiment and the 4th embodiment.Therefore, strengthened support by means of making thick tape substrates 4 to the salient pole 2 that is placed in the chip outside.
Elastomer 3 has by core layer 3d and is produced on the three-decker that the adhesive layer 3e on two faces of core layer 3d forms.Core layer 3d is made by the porous fluoroplastics, and adhesive layer 3e is made by epoxy resin impregnated porous fluoroplastics.
Elastomer 3 among the CSP 17 has the size substantially the same with tape substrates 4.The first type surface 1a that elastomer 3 is positioned in semiconductor chip 1 go up and the substrate ledge 4b of tape substrates 4 on.
Make in the reflux course of salient pole being used for, or be used for installing in the reflux course of CSP 17, in elastomer 3 thereby do not form the cavity.
And, by means of the drainage of the fluorine in the porous fluoroplastics of elastomer 3, can prevent that moisture from invading among the CSP 17.
Because the polyimide resin of band-shaped substrate material 4g must be made thickly, so the tape substrates 4 among the CSP 17 has the surface wiring structure.
Specifically, utilize the surface wiring structure, the lead-in wire 4c that Copper Foil is made is fabricated on the surface (face opposite with the bonding face of elastomer 3) of band-shaped substrate material 4g, can make window 4d in protective layer 4h.So band-shaped substrate material 4g can be made thick.
At this moment, the thickness of the band-shaped substrate material 4g that is made by polyimide resin that is used for the tape substrates 4 of CSP 17 is for example 100 microns or thicker.
By this way, band-shaped substrate material 4g can be made thick, and can strengthen the support to the salient pole 2 that is placed in the chip outside.
Because other structural similarity of the CSP 17 of the 4th embodiment is repeated in this description so locate to have omitted it in the structure of the described CSP 13 of second embodiment.
Because the manufacture method of the CSP 17 of the 4th embodiment is repeated in this description so locate to have omitted it similar in appearance to the manufacture method of the CSP 13 of second embodiment.
According to the fan-in of the 4th embodiment and the method for fan-out CSP 17 and manufacturing CSP 17, can access following effect and effect.
That is, by means of tape substrates 4 being provided and extending to the elastomer 3 of outside from semiconductor chip 1, and the tape substrates 4 of utilizing the surface wiring structure, the band-shaped substrate material 4g that is made by polyimide resin in the tape substrates 4 can be made thick.Utilizing band-shaped substrate material 4g wherein to be made into thickness is 100 microns tape substrates 4, can strengthen the robustness of tape substrates 4.
As a result, can strengthen support to the salient pole 2 that is placed in chip outside.
Core layer 3d in the elastomer 3 is made by the porous fluoroplastics, and adhesive layer 3e is made by epoxy resin impregnated porous fluoroplastics, and porous elastomers 3 is placed on the first type surface 1a of semiconductor chip 1.Therefore, make in the reflux course of salient pole being used for, or, in elastomer 3, do not form the cavity being used for installing in the reflux course of CSP 17.Because the steam that produces in the hermetic unit 5 can be discharged to the outside effectively, thus can prevent that backflow is broken that is the CSP installation in the appearance of trouble.
So, can access fan-in and fan-out CSP 17 with excellent anti reflux characteristic.
And, because the drainage of the fluorine in the porous fluoroplastics of elastomer 3 invades among the CSP 17 so can prevent moisture.Therefore, can reduce the degenerating of electrology characteristic of fan-in and fan-out CSP 17.
As a result, can realize having the fan-in and the fan-out CSP17 of excellent anti reflux characteristic and high reliability, wherein a plurality of salient poles 2 of supporting chip outside reliably.
Owing to such fastening element 6 in can CSP 11 shown in Figure 1 is produced CSP17, so can simplify the production (assembling) of fan-in and fan-out CSP 17.
Can realize the fan-in and the fan-out CSP 17 of production easily, a plurality of salient poles 2 of its chips outside are supported reliably.
Because do not use fastening element 6 among the CSP 13, so the CSP 11 that compares, cost has been lowered.
Structure (referring to Figure 23 and 24) as the improved CSP 18 of the CSP 17 of the 4th embodiment is described below.
CSP 17 has central solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is aligned at middle body.On the contrary, the CSP 18 shown in Figure 23 and 24 has peripheral solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is aligned at the periphery.
In the improved CSP 18 as the 4th embodiment, as shown in figure 23, the electrode pads 1b on the semiconductor chip 1 is positioned to a pair of side in opposite directions among the first type surface 1a of the semiconductor chip 1 in the periphery that almost is parallel to first type surface 1a, so that toward each other.
Figure 24 is the profile along the H-H line of the CSP 18 of Figure 23.
Central solder joint location by means of the electrode pads 1b on the semiconductor chip 1 that replaces with peripheral solder joint location among the CSP 17 shown in Figure 21 and 22 has obtained the improved CSP 18 of the conduct shown in Figure 23 and 24.
In CSP 18, electrode pads 1b is aligned along a pair of side in opposite directions among the first type surface 1a of semiconductor chip 1 in first type surface 1a periphery.Therefore, therefrom expose the window 4e of two elongations of the electrode pads 1b in the row, be fabricated in the tape substrates 4.Zone between two window 4e is corresponding to substrate bulk 4a, and the zone of window 4e outside is substrate ledge 4b.
Elastomer 3 has the size almost completely identical with tape substrates 4.Two window 3c corresponding to two window 4e are fabricated in the elastomer 3.Elastomer 3 comprises the part corresponding to substrate bulk part 4a and substrate ledge 4b, that is is placed in the part (elastomeric body part 3a) of the first type surface 1a of semiconductor chip 1 and extends to the part (elastomer footing 3b) of chip outside from first type surface 1a.
Therefore, 4 pairs of tape substrates are placed in the support of the salient pole 2 of semiconductor chip 1 outside, are made into thickness and are 100 microns or thicker band-shaped substrate material 4g and strengthened.
Because except the aligning of electrode pads 1b, the structural similarity among the CSP 18 is in CSP17, so located to omit the description that repeats.
Because effect that the method for manufacturing CSP 18 and CSP 18 and manufacture method thereof obtain and effect are also similar in appearance to CSP 17, so located to omit the description that repeats.
The 5th embodiment
Figure 25 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to fifth embodiment of the invention, wherein not shown hermetic unit.Figure 26 is the profile along the I-I line of semiconductor device shown in Figure 25.Figure 27 is a plane graph, shows the improvement structure of semiconductor device shown in Figure 25 (fan-in and fan-out CSP), wherein not shown hermetic unit.Figure 28 is the profile along the J-J line of semiconductor device shown in Figure 27.
The CSP 19 (semiconductor device) of the 5th embodiment is fan-in and the fan-out type device similar in appearance to the central solder joint of having of the CSP 17 of second embodiment shown in Figure 21 location.The difference of the CSP 19 of the 5th embodiment and the CSP 17 of the 4th embodiment is not use porous elastomers 3 and uses not elastomer 3f with the core layer elastomer of core layer (not with).
Therefore, by means of making thick tape substrates 4, strengthened support to the salient pole 2 that is placed in the chip outside in mode similar in appearance to the CSP 17 of the 4th embodiment.
The elastomer 3f that does not have core layer is a kind of element of for example being made and having adhesive function by acrylic acid/epoxy resin.Because elastomer 3f does not have the such core layer 3d of CSP 17, so very cheap and can be made thin.
In mode similar in appearance to CSP 17, do not have the elastomer 3 of core layer to have and tape substrates 4 size much at one, and the first type surface 1a that is positioned in semiconductor chip 1 goes up and the substrate ledge 4b of the tape substrates 4 of outside on.
Because the polyimide resin of band-shaped substrate material 4g must be made thickly, so the tape substrates 4 among the CSP 19 has the surface wiring structure.
The lead-in wire 4c that utilizes Copper Foil wherein to make is fabricated on the lip-deep surface wiring structure of band-shaped substrate material 4g, can make the window 4d of projection in the mode similar to CSP 17 in scolder protective layer 4h.So band-shaped substrate material 4g can be made thick.
At this moment, the thickness of the band-shaped substrate material 4g that is made by polyimide resin that is used for the tape substrates 4 of CSP 19 is for example 100 microns or thicker.
By this way, band-shaped substrate material 4g can be made thick, and can strengthen the support to the salient pole 2 that is placed in the chip outside.
Because other structural similarity of the CSP 19 of the 5th embodiment is repeated in this description so locate to have omitted it in the structure of the described CSP 17 of the 4th embodiment.
Because the manufacture method of the CSP 19 of the 5th embodiment is repeated in this description so locate to have omitted it similar in appearance to the manufacture method of the CSP 13 of second embodiment.
According to the fan-in of the 5th embodiment and the method for fan-out CSP 19 and manufacturing CSP 19, can access following effect and effect.
That is, by means of provide tape substrates 4 and from semiconductor chip 1 extend to the outside the elastomer that does not have core layer 3, and the tape substrates 4 of utilizing the surface wiring structure, the band-shaped substrate material 4g that is made by polyimide resin in the tape substrates 4 can be made thick.Utilizing wherein band-shaped substrate material 4g to be made into thickness is 100 microns or thicker tape substrates 4, can strengthen the robustness of tape substrates 4.
As a result, can strengthen support to the salient pole 2 that is placed in chip outside.
Utilization does not have the elastomer 3f of core layer, and it is thin that elastomer 3f can be made, thereby can reduce cost.
Therefore, it is thinner that CSP 19 can be made, thereby can reduce cost.
Owing to such fastening element 6 in can CSP 11 shown in Figure 1 is produced CSP19, so can simplify the production (assembling) of fan-in and fan-out CSP 19.
Can realize the fan-in and the fan-out CSP 19 of production easily, a plurality of salient poles 2 of its chips outside are supported reliably.
Because do not use fastening element 6 among the CSP 19, so the CSP 11 that compares, cost has been lowered.
Structure (referring to Figure 27 and 28) as the improved CSP 20 of the CSP 19 of the 5th embodiment is described below.
CSP 19 has central solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is aligned at middle body.On the contrary, the CSP 20 shown in Figure 27 and 28 has peripheral solder joint location, and wherein the electrode pads 1b on the semiconductor chip 1 is aligned at the periphery.
In the improved CSP 20 as the 5th embodiment, as shown in figure 27, the electrode pads 1b on the semiconductor chip 1 is aligned to a pair of side in opposite directions among the first type surface 1a of the semiconductor chip 1 in the periphery that almost is parallel to first type surface 1a, so that toward each other.
Figure 28 is the profile along the J-J line of the CSP 20 of Figure 27.
Central solder joint location by means of the electrode pads 1b on the semiconductor chip 1 that replaces with peripheral solder joint location among the CSP 19 shown in Figure 25 and 26 has obtained the improved CSP 20 of the conduct shown in Figure 27 and 28.
In CSP 20, electrode pads 1b is aligned along a pair of side in opposite directions among the first type surface 1a of semiconductor chip 1 in first type surface 1a periphery.Therefore, therefrom expose the window 4e of two elongations of the electrode pads 1b in the row, be fabricated in the tape substrates 4.Zone between two window 4e is corresponding to substrate bulk 4a, and the zone of window 4e outside is substrate ledge 4b.
There is not the elastomer 3f of core layer to have the size almost completely identical with tape substrates 4.Two window 3c corresponding to two window 4e are fabricated among the elastomer 3f.Elastomer 3f comprises the part corresponding to substrate bulk part 4a and substrate ledge 4b, that is be placed in semiconductor chip 1 first type surface 1a part and extend to the part of chip outside from first type surface 1a.
4 pairs of tape substrates are placed in the support of the salient pole 2 of semiconductor chip 1 outside, are made into thickness and are 100 microns or thicker thick band-shaped substrate material 4g and strengthened.
Because except the aligning of electrode pads 1b, the structural similarity among the CSP 20 is in CSP19, so located to omit the description that repeats.
Because effect that the method for manufacturing CSP 20 and CSP 20 and manufacture method thereof obtain and effect are also similar in appearance to CSP 19, so located to omit the description that repeats.
The 6th embodiment
Figure 29 is a plane graph, shows the example of structure of the semiconductor device (fan-in and fan-out CSP) according to sixth embodiment of the invention, wherein not shown hermetic unit.Figure 30 is the profile along the K-K line of semiconductor device shown in Figure 29.
The CSP30 of the 6th embodiment (semiconductor device) is fan-in and the fan-out type device similar in appearance to the central solder joint of having of the CSP 11 of first embodiment shown in Figure 1 location.The difference of the CSP 11 of the CSP30 of the 6th embodiment and first embodiment is by means of the wire bonds of using bonding wire 24, and the electrode pads 1b on the semiconductor chip 1 is connected to respective lead 4c on the tape substrates 4.
Specifically, as shown in figure 30, the bonding window 4i that therefrom exposes the end (part) of each lead-in wire 4c is fabricated among the scolder protective layer 4h of tape substrates 4.The end of each lead-in wire 4c that exposes from bonding window 4i is connected to electrode pads 1b on the semiconductor chip 1 via wire 24.
Though each lead-in wire 4c on the tape substrates 4 extends to the window 4e that exposes the electrode pads 1b on the semiconductor chip 1, lead-in wire 4c is not positioned among the window 4e, but ends at the state that is covered by scolder protective layer 4h.
Because the end (end opposite with the side that is connected to salient pole 2) to each lead-in wire 4c on the tape substrates 4 carries out wire bonds, so the also sealed part 5 of the not only window 4e in the tape substrates 4, and the tie point between lead-in wire 4c and the wire 24 covers.
That is, the tie point between the window 4e in the tape substrates 4 and lead-in wire 4c and the wire 24, sealed part 5 covers in CSP30.Hermetic unit 5 thereby be formed on than in the wideer scope of the hermetic unit among the CSP 11 5.
With the terminal opposite end of bonding wire 24, be electrically connected to salient pole 2 among each lead-in wire 4c in mode similar in appearance to CSP11.
As shown in figure 30, the CSP30 that is used for the 6th embodiment has the surface wiring structure, and the 4c that wherein goes between is fabricated on the surface of band-shaped substrate material 4g.
The wire 24 that is used for wire bonds is for example a kind of wires.Also can use copper wire and so on.
Because other structural similarity among the CSP30 of the 6th embodiment is repeated in this description so locate to have omitted it in the structure of the described CSP 11 of first embodiment.
The production technology of the CSP30 of the 6th embodiment is described below.
The resemble process of producing CSP30 is in the technology of CSP 11, but following difference is arranged.In " bonding of lead-in wire " of Fig. 3 step S4, carry out wire bonds, thereby via electrode pads 1b on the 24 connection semiconductor chips 1 of the bonding wire such as wire and the lead-in wire 4c on the tape substrates 4.
" bonding of chip " in completing steps S3 utilizes the wire bonds device afterwards, carries out wire bonds in step S4.By means of wire bonds, the associated end (part) of the lead-in wire 4c on the electrode pads 1b on the semiconductor chip 1 that window 4e from tape substrates 4 exposes and the tape substrates 4 that exposes from bonding window 4i is connected via bonding wire 24.
In step S5, carry out then " sealing ".
Specifically, encapsulant is dripped to the window 4e in the tape substrates 4, so that with the electrode pads 1b on the resin-encapsulated semiconductor chip 1 be connected to the bonding wire 24 of electrode pads 1b.Encapsulant also is dripped to the lead-in wire 4c and the junction between the wire 24 around the window 4e, thus formation hermetic unit 5.
Then, to make the mode of CSP 11 similar in appearance to first embodiment, carry out step S6-S9, thereby finish CSP30.
According to the fan-in of the 6th embodiment and the method for fan-out CSP30 and manufacturing CSP30, following effect and effect have been obtained.
In CSP30, because electrode pads 1b on the semiconductor chip 1 and the wire bonds method bonding that is used wire 24 of the respective lead 4c on the tape substrates 4, so in production technology, can use assembling device such as having the wire bonds machine now.The manufacturing cost that can suppress as a result, CSP30.
Because other effect and effect are repeated in this description so locate to have omitted it similar in appearance to the CSP 11 of first embodiment.
Though the CSP30 of the 6th embodiment shown in Figure 29 and 30 is central solder joint location, but connect electrode pads 1b on the semiconductor chip 1 and the structure of the respective lead 4c on the tape substrates 4 by means of wire bonds, and the method for making this structure, also can be applied to the CSP of peripheral solder joint location in the mode of similar in appearance to first to the 5th embodiment.Effect that is obtained by peripheral solder joint location and effect are similar in appearance to effect and the effect of the CSP30 of central solder joint location.
Though first to the 6th embodiment according to the present invention has described the present invention that the inventor obtains particularly, the present invention is not limited to above-mentioned first to the 6th embodiment of the present invention, but can do various improvement and do not surmount its main idea.
For example, have the situation of rectangular shape though described semiconductor chip 1 in first to the 6th embodiment, semiconductor chip 1 also can have square shape.
And under the situation of weld all around point location, the installation site that offers the electrode pads 1b of semiconductor chip 1 is not limited to two ends, but can be provided at any position outside, as long as be arranged in the outer peripheral areas of the first type surface 1a of semiconductor chip 1.For example, electrode pads 1b can be provided in the whole outer peripheral areas among the first type surface 1a.
The number of the number of electrode pads 1b and salient pole 2 is not limited to the number among first to the 6th embodiment, but can adopt any number.
The shape of window 4e in the tape substrates 4 and the shape of the window 3c in the elastomer 3 are not limited to rectangle.As long as can expose the electrode pads 1b on the semiconductor chip 1, also can adopt other shape.
Though having described the tape substrates 4 among the CSP30 in the 6th embodiment is situations of surface wiring structure, the tape substrates 4 that is used for CSP30 also can be the back wiring structure.In the tape substrates 4 of wire structures, bonding window 4i is fabricated among the band-shaped substrate material 4g overleaf.
And the CSP structure that the wire bonds described in the 6th embodiment obtains can be applied to the CSP 11,12,13,14,15,16,17,18,19 and 20 among first to the 5th embodiment.As the structure of this moment, the lead-in wire 4c that is connected to the electrode pads 1b on the semiconductor chip 1 is replaced by wire 24.
The coating that is used for the described CSP 11 of first embodiment and is had as the lead-in wire 4c on the tape substrates 4 of the improved CSP 12 of CSP 11 also is applied to each CSP among second to the 6th embodiment.
Described fan-in of first to the 6th embodiment and fan-out semiconductor device (CSP) can be used to synchronous dram, fast storage, ASIC (application-specific integrated circuit), CPU (central processing unit), grid array of for example DRAM (dynamic random access memory), synchronous dram, static RAM (SRAM), rambus DRAM, direct rambus DRAM, DDR (Double Data Rate) system or the like.The product of using above-mentioned various devices is such as module and magnetic card or portable little and thin electronic device.
This CSP can be widely used in the product outside module, magnetic card and the portable little and thin electronic device.
The effect that obtains with the disclosed representative device of the present invention of this specification is summarized as follows.
(1) in fan-in and fan-out semiconductor devices (CSP), is placed in half by means of providing The fastening element of conductor chip outside, reliably a plurality of salient poles of supporting chip outside.
(2) by means of with the poroelasticity component positioning on the first type surface of semiconductor chip, the peace Carry out during the dress semiconductor devices and reflux, in flexible member, do not form the cavity, cause and to access Semiconductor devices with excellent anti-reflux characteristic. That as a result, can improve semiconductor devices can Lean on property.
(3) by means of provide tape substrates and from semiconductor chip extend to the outside elasticity unit Part, and by means of polyimide resin and elasticity with the band-shaped substrate material in the tape substrates The gross thickness of the polyimide resin of the core layer in the element is set at the 100-175 micron, can The salient pole of supporting chip outside and fastening element need not be provided reliably. As a result, simplified The production of fan-in and fan-out semiconductor devices (CSP), and supporting chip outside reliably A plurality of salient poles.

Claims (53)

1. semiconductor device, it comprises:
Be placed on the first type surface of semiconductor chip and a plurality of salient poles of chip first type surface outside;
Be placed on the first type surface of semiconductor chip, and wherein make the poroelasticity element of the window of the splicing ear that therefrom exposes semiconductor chip;
Be equipped with the lead-in wire that extends to chip outside from the first type surface of semiconductor chip, the one end is electrically connected to splicing ear and the other end is electrically connected to salient pole, and wherein is constructed for exposing the tape substrates of the window of splicing ear;
Be used for reinforcing fastening element to the support of the salient pole that is placed in the semiconductor chip outside; And
Be used for the hermetic unit of lead-in wire of the splicing ear of sealing semiconductor chips and tape substrates.
2. according to the semiconductor device of claim 1, fastening element is wherein made by polyimide resin, and is made thick.
3. according to the semiconductor device of claim 1, fastening element is wherein made by metal material.
4. according to the semiconductor device of claim 1, fastening element wherein is made into frame shape, and semiconductor chip and flexible member are positioned in the framework.
5. according to the semiconductor device of claim 1, during wherein the splicing ear of semiconductor chip is positioned in zone line between the side along a pair of side in opposite directions in the semiconductor chip first type surface.
6. according to the semiconductor device of claim 1, wherein the splicing ear of semiconductor chip is positioned in the first type surface periphery of semiconductor chip along arbitrary side of first type surface.
7. according to the semiconductor device of claim 1, poroelasticity element wherein has the three-decker of being made up of core layer and the adhesive layer on two faces that are produced on core layer, core layer is made by the porous fluoroplastics, and adhesive layer is made by epoxy resin impregnated fluoroplastics.
8. according to the semiconductor device of claim 1, wherein the band-shaped substrate material in the tape substrates is made by polyimide resin, and is fabricated on the tape substrates by the lead-in wire that Copper Foil is made.
9. according to the semiconductor device of claim 1, wherein the gross thickness of the band-shaped substrate material of being made by polyimide resin in fastening element of being made by polyimide resin and the tape substrates is in the 100-175 micrometer range.
10. semiconductor device, it comprises:
Have flexible member body that is placed on the semiconductor chip first type surface and the flexible member footing that extends in semiconductor chip first type surface outside, and have the flexible member that therefrom exposes the window that is produced on the splicing ear on the semiconductor chip first type surface;
The lead-in wire that extends to the chip outside from the semiconductor chip first type surface is equipped with, the one end is electrically connected to splicing ear and the other end is electrically connected to salient pole and the band-shaped substrate material as outside terminal, and has the tape substrates of the window that is used for exposing splicing ear;
Be used for sealing semiconductor chips splicing ear and be connected to the hermetic unit of the lead-in wire of splicing ear; And
Be placed on the semiconductor chip first type surface and the salient pole as outside terminal of semiconductor chip outside,
The salient pole that wherein is placed in the semiconductor chip outside is supported and reinforcing by the flexible member footing of tape substrates and flexible member.
11. according to the semiconductor device of claim 10, flexible member wherein has the core layer of being made by polyimide resin.
12. semiconductor device according to claim 10, flexible member wherein has the core layer of being made by polyimide resin, band-shaped substrate material in the tape substrates is made by polyimide resin, and the gross thickness of core layer of being made by polyimide resin and band-shaped substrate material is in the 100-175 micrometer range.
13. according to the semiconductor device of claim 12, wherein the thickness of the polyimide resin of band-shaped substrate material is 50 microns, and the thickness of the polyimide resin of the core layer in the flexible member is in the 50-125 micrometer range.
14. according to the semiconductor device of claim 10, during wherein the splicing ear of semiconductor chip is positioned in zone line between the side along a pair of side in opposite directions in the semiconductor chip first type surface.
15. according to the semiconductor device of claim 10, wherein the splicing ear of semiconductor chip is positioned in the first type surface periphery of semiconductor chip along arbitrary side of first type surface.
16. according to the semiconductor device of claim 10, wherein the band-shaped substrate material in the tape substrates is made by polyimide resin, and is fabricated on by the lead-in wire that Copper Foil is made on the face of band-shaped substrate material.
17. according to the semiconductor device of claim 16, wherein the lead-in wire of making by Copper Foil be fabricated on band-shaped substrate material in the tape substrates with the one side opposite surfaces that is connected to flexible member on.
18. a semiconductor device, it comprises:
Be placed on the semiconductor chip first type surface and a plurality of salient poles of chip first type surface outside;
Have flexible member body that is placed on the semiconductor chip first type surface and the flexible member footing that extends in semiconductor chip first type surface outside, and wherein make the flexible member of the window of the splicing ear that exposes semiconductor chip;
Be equipped with the lead-in wire that extends to chip outside from the semiconductor chip first type surface, the one end is electrically connected to splicing ear and the other end is electrically connected to salient pole, and wherein makes the tape substrates of the window that exposes splicing ear; And
Be used for the hermetic unit of lead-in wire of the splicing ear of sealing semiconductor chips and tape substrates,
Wherein flexible member is made into the thickness that thickness is equal to or greater than tape substrates, and strengthens the support of tape substrates to the salient pole that is placed in the semiconductor chip outside with thick flexible member footing.
19. according to the semiconductor device of claim 18, wherein the splicing ear of semiconductor chip is placed in the zone line between a pair of side in opposite directions in the semiconductor chip first type surface, so that almost be parallel to side.
20. according to the semiconductor device of claim 18, wherein the splicing ear of semiconductor chip is placed in semiconductor chip first type surface periphery, so that almost be parallel to arbitrary side of first type surface.
21. according to the semiconductor device of claim 18, wherein the band-shaped substrate material in the tape substrates is made by polyimide resin, and is fabricated on by the lead-in wire that Copper Foil is made on the face of band-shaped substrate material.
22. according to the semiconductor device of claim 21, wherein the lead-in wire of being made by Copper Foil is fabricated on the surface that is bonded with flexible member of the band-shaped substrate material in the tape substrates.
23. according to the semiconductor device of claim 18, wherein the thickness of the polyimide resin of band-shaped substrate material is 50 microns, and the thickness of the polyimide resin of flexible member is in the 50-125 micrometer range.
24. a semiconductor device, it comprises:
Extend in semiconductor chip first type surface outside and have the poroelasticity element that therefrom exposes the window that is produced on the splicing ear on the semiconductor chip first type surface;
Be equipped with the lead-in wire that extends to chip outside from the semiconductor chip first type surface, the one end is electrically connected to splicing ear and the other end is electrically connected to the salient pole as outside terminal, and has the tape substrates of the window that therefrom exposes splicing ear;
Be used for the hermetic unit of lead-in wire of the splicing ear of sealing semiconductor chips and tape substrates; And
Be placed on the semiconductor chip first type surface and a plurality of salient poles of chip first type surface outside as outside terminal,
Wherein the band-shaped substrate material in the tape substrates be made into thicker than the core layer of poroelasticity element, and with of the support of the material reinforced tape substrates of thick band-shaped substrate to the salient pole that is placed in semiconductor chip outside.
25. according to the semiconductor device of claim 24, wherein the band-shaped substrate material in the tape substrates is made by polyimide resin, and is fabricated on by the lead-in wire that Copper Foil is made on the face of band-shaped substrate material.
26. according to the semiconductor device of claim 25, wherein the lead-in wire of being made by Copper Foil is fabricated on the opposite face of the one side with being bonded with flexible member of band-shaped substrate material.
27. according to the semiconductor device of claim 24, wherein the splicing ear of semiconductor chip almost is parallel to a pair of side in opposite directions in the semiconductor chip first type surface and is placed in the zone line between the side.
28. according to the semiconductor device of claim 24, wherein the splicing ear of semiconductor chip arbitrary side of almost being parallel to first type surface is placed in semiconductor chip first type surface periphery.
29. semiconductor device according to claim 24, poroelasticity element wherein has the three-decker of being made up of core layer and the adhesive layer on two faces that are produced on core layer, core layer is made by the porous fluoroplastics, and adhesive layer is made by epoxy resin impregnated fluoroplastics.
30. according to the semiconductor device of claim 24, wherein the thickness of the band-shaped substrate material in the tape substrates is 100 microns or thicker.
31. a semiconductor device, it comprises:
Be placed on the semiconductor chip first type surface and a plurality of salient poles of chip first type surface outside;
Extend in semiconductor chip first type surface outside and wherein be constructed for exposing the flexible member that does not have core layer of window of the splicing ear of semiconductor chip;
Be equipped with the lead-in wire that extends to chip outside from the semiconductor chip first type surface, the one end is electrically connected to splicing ear and the other end is electrically connected to salient pole, and wherein is constructed for exposing the tape substrates of the window of splicing ear; And
Be used for the hermetic unit of lead-in wire of the splicing ear of sealing semiconductor chips and tape substrates,
Wherein to be made into thickness be 100 microns or thicker to the band-shaped substrate material of tape substrates, and be that 100 microns or thicker band-shaped substrate material strengthen the support of tape substrates to the salient pole that is placed in the semiconductor chip outside with thickness.
32. according to the semiconductor device of claim 31, wherein the splicing ear of semiconductor chip almost is parallel to a pair of side in opposite directions in the semiconductor chip first type surface and is placed in the zone line between the side.
33. according to the semiconductor device of claim 31, wherein the splicing ear of semiconductor chip arbitrary side of almost being parallel to first type surface is placed in semiconductor chip first type surface periphery.
34. a semiconductor device, it comprises:
Be placed on the first type surface of semiconductor chip and a plurality of salient poles of chip first type surface outside;
Be placed on the first type surface of semiconductor chip, and wherein make the poroelasticity element of the window of the splicing ear that therefrom exposes semiconductor chip;
Be equipped with the lead-in wire that extends to chip outside from the first type surface of semiconductor chip, its part is exposed and the one end is electrically connected to salient pole, and wherein is constructed for exposing the tape substrates of the window of splicing ear;
Being used for splicing ear with semiconductor chip is bonded to the bonding wire of expose portion of the lead-in wire of tape substrates;
Be used for reinforcing fastening element to the support of the salient pole that is placed in the semiconductor chip outside; And
Be used for the splicing ear and the hermetic unit wiry of sealing semiconductor chips.
35. according to the semiconductor device of claim 34, wherein the band-shaped substrate material in the tape substrates is made by polyimide resin, and is fabricated on one of the surface of band-shaped substrate material and back side by the lead-in wire that Copper Foil is made.
36. a method of making semiconductor device, it comprises the following step:
Preparation has the semiconductor chip of a plurality of splicing ears on its first type surface;
Preparation is equipped with lead-in wire on one face, and wherein makes the tape substrates of the window that is mounted with the part lead-in wire;
Preparation is made into thickness and is equal to or greater than tape substrates, and has the flexible member body part of wherein making the shape window substantially the same with the window in the tape substrates and be produced on the two flexible member of flexible member footing outside the flexible member body part;
Under the window in aiming at tape substrates and the situation of the window in the flexible member, that tape substrates and flexible member is bonded to each other;
From two windows, expose the splicing ear of semiconductor chip, the flexible member body part is placed on the first type surface of semiconductor chip, the flexible member footing can be extended in outside the first type surface of semiconductor chip, and the first type surface of semiconductor chip bonded to each other and flexible member;
With the splicing ear of semiconductor chip be placed in tape substrates in window in corresponding lead-in wire be connected to each other;
With the splicing ear and the lead-in wire that is connected to splicing ear of resin-encapsulated semiconductor chip, thereby form hermetic unit;
Making treats to be connected to the salient pole of the lead-in wire on the tape substrates one side; And
With the tape substrates dicing,
Wherein can be enough thick flexible member footing strengthens the support of tape substrates to the salient pole that is placed in the semiconductor chip outside.
37. according to the method for the manufacturing semiconductor device of claim 36, wherein the band-shaped substrate material is made by polyimide resin and is fabricated on tape substrates on the face of band-shaped substrate material by the lead-in wire that Copper Foil is made, and is used as tape substrates.
38. method according to the manufacturing semiconductor device of claim 36, wherein the band-shaped substrate material is made by polyimide resin and is fabricated on tape substrates on the face of connection flexible member of band-shaped substrate material by the lead-in wire that copper film is made, be used as tape substrates, and making on the tape substrates under the situation of salient pole, salient pole is electrically connected to lead-in wire by being provided at the projection window in the projection installation site in the band-shaped substrate material.
39. according to the method for the manufacturing semiconductor device of claim 36, wherein when tape substrates and semiconductor chip via flexible member when bonded to each other, tape substrates extends to the outside from the whole periphery of semiconductor chip.
40. a method of making semiconductor device, it comprises the following step:
Prepare the semiconductor chip that has a plurality of splicing ears on its first type surface;
Preparation has lead-in wire on one face, and wherein makes the tape substrates of the window that is mounted with the part lead-in wire;
The poroelasticity element of the shape window substantially the same with the window in the tape substrates is wherein made in preparation;
Under the window in aiming at tape substrates and the situation of the window in the flexible member, that tape substrates and flexible member is bonded to each other;
From two windows, expose the splicing ear of semiconductor chip, make tape substrates and flexible member can extend to outside and the first type surface of semiconductor chip bonded to each other and flexible member from the first type surface of semiconductor chip;
With the splicing ear of semiconductor chip be placed in tape substrates in window in corresponding lead-in wire be connected to each other;
Splicing ear and the lead-in wire that is connected to splicing ear by means of with the resin-encapsulated semiconductor chip form hermetic unit;
Making treats to be connected to the salient pole of the lead-in wire on face of tape substrates; And
With the tape substrates dicing,
Wherein can enoughly be made into the band-shaped substrate material in the tape substrates that is thicker than the core layer in the flexible member, strengthen the support of tape substrates the salient pole that is placed in the semiconductor chip outside.
41. according to the method for the manufacturing semiconductor device of claim 40, wherein the flexible member made by the porous fluoroplastics of its core layer is used as the poroelasticity element.
42. according to the method for the manufacturing semiconductor device of claim 40, wherein the band-shaped substrate material lead-in wire being made by polyimide resin and wherein made by metal forming is fabricated on the tape substrates on the face of band-shaped substrate material, is used as tape substrates.
43. according to the method for the manufacturing semiconductor device of claim 42, wherein the lead-in wire of tape substrates is the lead-in wire that Copper Foil is made.
44. according to the method for the manufacturing semiconductor device of claim 42, wherein the band-shaped substrate material is made by polyimide resin and thickness is 100 microns or thicker tape substrates, is used as tape substrates.
45. according to the method for the manufacturing semiconductor device of claim 42, wherein lead-in wire is fabricated on the tape substrates on the face opposite with face bonding flexible member the band-shaped substrate material, is used as tape substrates.
46. a method of making semiconductor device, it comprises the following step:
Prepare the semiconductor chip that has a plurality of splicing ears on its first type surface;
Preparation has lead-in wire on one face, and has the tape substrates of the window that wherein is mounted with the part lead-in wire;
The poroelasticity element of the shape window substantially the same with the window in the tape substrates is wherein made in preparation;
Preparation is used for strengthening the fastening element of tape substrates to the support of the salient pole that is placed in the semiconductor chip outside;
Under the window in aiming at tape substrates and the situation of the window in the flexible member, that tape substrates and flexible member is bonded to each other;
Tape substrates and fastening element is bonded to each other;
From two windows, expose the splicing ear of semiconductor chip, fastening element is placed in around the semiconductor chip, and the first type surface of semiconductor chip bonded to each other and flexible member;
With the splicing ear of semiconductor chip be placed in tape substrates in window in corresponding lead-in wire be connected to each other;
Splicing ear and the lead-in wire that is connected to splicing ear by means of with the resin-encapsulated semiconductor chip form hermetic unit;
Making treats to be connected to the salient pole of the lead-in wire on face of tape substrates; And
With the tape substrates dicing,
Wherein can be enough fastening element strengthen the support of tape substrates to the salient pole that is placed in the semiconductor chip outside.
47. according to the method for the manufacturing semiconductor device of claim 46, wherein after tape substrates bonded to each other and flexible member, fastening element is positioned in around the flexible member, and tape substrates and fastening element are by bonded to each other.
48. according to the method for the manufacturing semiconductor device of claim 46, wherein after tape substrates bonded to each other and fastening element, flexible member is positioned in fastening element inside, and tape substrates and flexible member are by bonded to each other.
49. according to the method for the manufacturing semiconductor device of claim 46, wherein fastening element is made into frame shape, and semiconductor chip is positioned in the framework inside of fastening element.
50. the method according to the manufacturing semiconductor device of claim 46 wherein is used as fastening element by the fastening element that metal material is made.
51. the method according to the manufacturing semiconductor device of claim 46 wherein is used as fastening element by the fastening element that polyimide resin is made.
52. according to the method for the manufacturing semiconductor device of claim 51, the tape substrates of wherein using the band-shaped substrate material to make by polyimide resin, and the gross thickness of fastening element in the band-shaped substrate material and polyimide resin is 100 microns or thicker.
53. a method of making semiconductor device, it comprises the following step:
Prepare the semiconductor chip that has a plurality of splicing ears on its first type surface;
Preparation has lead-in wire on one face, and has the splicing ear that is used for exposing semiconductor chip, and the tape substrates of the window of expose portion lead-in wire wherein;
The poroelasticity element of the shape window substantially the same with the window in the tape substrates is wherein made in preparation;
Preparation is used for strengthening the fastening element of tape substrates to the support of the salient pole that is placed in the semiconductor chip outside;
Under the window in aiming at tape substrates and the situation of the window in the flexible member, that tape substrates and flexible member is bonded to each other;
Tape substrates and fastening element is bonded to each other;
From two windows, expose the splicing ear of semiconductor chip, fastening element is placed in around the semiconductor chip, and the first type surface of semiconductor chip bonded to each other and flexible member;
Use the wire bonds method, the expose portion of the respective lead of the splicing ear of semiconductor chip and tape substrates is connected to each other;
Splicing ear and the bonding wire that is bonded to splicing ear by means of with the resin-encapsulated semiconductor chip form hermetic unit;
Making treats to be connected to the salient pole of the lead-in wire on face of tape substrates; And
With the tape substrates dicing,
Wherein can be enough fastening element strengthen the support of tape substrates to the salient pole that is placed in the semiconductor chip outside.
CN00126862A 1999-09-17 2000-09-07 Semiconductor device and production technology thereof Pending CN1289143A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP263016/1999 1999-09-17
JP26301699A JP2001085565A (en) 1999-09-17 1999-09-17 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
CN1289143A true CN1289143A (en) 2001-03-28

Family

ID=17383723

Family Applications (1)

Application Number Title Priority Date Filing Date
CN00126862A Pending CN1289143A (en) 1999-09-17 2000-09-07 Semiconductor device and production technology thereof

Country Status (5)

Country Link
JP (1) JP2001085565A (en)
KR (1) KR20010070081A (en)
CN (1) CN1289143A (en)
SG (1) SG90155A1 (en)
TW (1) TW504778B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103079352A (en) * 2012-12-29 2013-05-01 中国航空工业集团公司第六三一研究所 Reinforcing method for printed plate
CN107978583A (en) * 2016-10-21 2018-05-01 力成科技股份有限公司 Encapsulating structure and its manufacture method
CN109075089A (en) * 2016-05-18 2018-12-21 三菱电机株式会社 Power semiconductor device and its manufacturing method

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10014305C2 (en) * 2000-03-23 2002-02-07 Infineon Technologies Ag Electronic component with a large number of contact bumps
US6589820B1 (en) 2000-06-16 2003-07-08 Micron Technology, Inc. Method and apparatus for packaging a microelectronic die
US6483044B1 (en) 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6838760B1 (en) * 2000-08-28 2005-01-04 Micron Technology, Inc. Packaged microelectronic devices with interconnecting units
KR100694425B1 (en) * 2002-05-06 2007-03-12 앰코 테크놀로지 코리아 주식회사 manufacturing method of semiconductor package
KR200453796Y1 (en) * 2009-04-03 2011-05-27 주식회사 마그마 Metal dome switch for keypad
JP6162428B2 (en) * 2013-02-27 2017-07-12 日本特殊陶業株式会社 Support device

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3639088B2 (en) * 1997-06-06 2005-04-13 株式会社ルネサステクノロジ Semiconductor device and wiring tape
JPH11145345A (en) * 1997-11-12 1999-05-28 Hitachi Ltd Semiconductor device and its manufacture

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103079352A (en) * 2012-12-29 2013-05-01 中国航空工业集团公司第六三一研究所 Reinforcing method for printed plate
CN109075089A (en) * 2016-05-18 2018-12-21 三菱电机株式会社 Power semiconductor device and its manufacturing method
CN107978583A (en) * 2016-10-21 2018-05-01 力成科技股份有限公司 Encapsulating structure and its manufacture method
CN107978583B (en) * 2016-10-21 2020-11-17 力成科技股份有限公司 Package structure and method for manufacturing the same

Also Published As

Publication number Publication date
SG90155A1 (en) 2002-07-23
JP2001085565A (en) 2001-03-30
KR20010070081A (en) 2001-07-25
TW504778B (en) 2002-10-01

Similar Documents

Publication Publication Date Title
CN1187822C (en) Semiconductor device, method of manufacture thereof, and electronic device
CN1218392C (en) Semiconductor device and manufacturing method thereof
CN1527370A (en) Method for producing semiconductor device
CN1248308C (en) Semiconductor device, method of manufacturing the same, and structure for mounting semiconductor device
CN1145206C (en) Film carrier tape, semiconductor assembly, semiconudctor device, manufacturing method therefor, mounting board and electronic equipment
CN100342533C (en) Semiconductor device and its manufacturing method
CN1193253C (en) Platform and optical module, and producing method and optical transmission device
CN1259200C (en) Card type recording medium and production method therefor
CN1215537C (en) Elements with resin shell capsulation and making method
CN1163058C (en) Camera device
CN1146029C (en) Electronic component and method of production thereof
CN1222037C (en) Memory assembly and its making method
CN1275312C (en) Semiconductor device and its producing method, laminated semiconductor device and circuit base board
CN1237785A (en) Semiconductor device, and method of producing semiconductor device
CN1993001A (en) Semiconductor device
CN1967853A (en) Semiconductor device and manufacturing method of the same
CN1941348A (en) Relay board and semiconductor device having the relay board
CN1669138A (en) Semiconductor device
CN1214464C (en) Semiconductor device and method of manufacture thereof
CN1568546A (en) Semiconductor device and method of manufacturing the same
CN1638076A (en) Semiconductor chip and manufacturing method for the same, and semiconductor device
CN1677776A (en) Optical pick-up device, semiconductor laser device for same and housing thereof
CN101055857A (en) Semiconductor apparatus and method of producing the same
CN1275783A (en) Packaged solid electrolyte capacitor and making method thereof
CN1656611A (en) Semiconductor device mounting board, method of manufacturing the same, method of inspecting the same, and semiconductor package

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication
REG Reference to a national code

Ref country code: HK

Ref legal event code: GR

Ref document number: 1049617

Country of ref document: HK