CN1287438C - Wafer base and plasma technology using the same - Google Patents
Wafer base and plasma technology using the same Download PDFInfo
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- CN1287438C CN1287438C CN 200410034716 CN200410034716A CN1287438C CN 1287438 C CN1287438 C CN 1287438C CN 200410034716 CN200410034716 CN 200410034716 CN 200410034716 A CN200410034716 A CN 200410034716A CN 1287438 C CN1287438 C CN 1287438C
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Abstract
The present invention discloses a wafer pedestal and a plasma body technology which uses the wafer pedestal, wherein the wafer pedestal is used for carrying a wafer in a plasma body reaction chamber, the wafer pedestal comprises an insulating body with the first width and a conductor layer with a second width which is not larger than the first width, the second width is not smaller than the diameter of the wafer, and the conductor layer is embedded in the insulating body. The plasma body technology comprises a feeding step, the semiconductor wafer is placed on the wafer pedestal, and the position of the semiconductor wafer on the wafer pedestal is contained in an area right above the conductor layer.
Description
Technical field
The present invention relates to a kind of semiconductor manufacturing equipment, more particularly, relate to wafer base (pedestal) that is used for bearing wafer in a kind of plasma-reaction-chamber and the plasma process that uses this wafer base.
Background technology
As shown in Figure 1, the figure shows the situation that a conventional wafer pedestal 100 moves in a plasma reative cell.Action situation shown in Fig. 1 is with the source of argon gas as inert gas plasma 42, to remove Si oxide or the metal oxide on the semiconductor wafer 10, particularly semiconductor wafer 10 is used to remove the oxide step of interlayer hole (via) the metal level (not shown) that (not shown) exposed to the open air in metallization process.
Plasma-reaction-chamber shown in Fig. 1 includes a quartz bell cover 220, as the outer wall of plasma-reaction-chamber; And the coil 240 that is positioned at quartz bell cover 220 outsides, wherein a coil 240 and a radio-frequency power supply 232 electrically connect, and conductor layer 120 also electrically connects with a radio-frequency power supply 234, can make the argon gas (not shown) ionizations in the quartz bell cover 220 form inert gas plasma 42, and drive that inert gas plasma 42 bombards on the semiconductor wafer 10 and the oxide skin(coating) of removing a predetermined thickness on the semiconductor wafer 10.In addition, quartz is a kind of crystalline form of silicon dioxide, so quartz bell cover 220 helps to adsorb the oxide particle (not shown) that is produced in the above-mentioned plasma process, avoids above-mentioned oxide particle to fall within semiconductor wafer 10 surfaces, pollutes.
When semiconductor wafer 10 was one 8 inches wafer, the width of wafer base 100 or typically have a diameter from about 9 inches, and the width of conductor layer 120 or typically have a diameter from about 190mm were less than the diameter of semiconductor wafer 10.And as shown in Figure 1, in above-mentioned plasma process, plasma 42 is incident on the surface of semiconductor wafer 10 with vertical direction, uniform density usually.Yet, in above-mentioned traditional wafer base 100, because of the width of conductor layer 120 or diameter less than the diameter of semiconductor wafer 10, cause near the edge of semiconductor wafer 10, attract density bigger inert gas plasma 42 with non-perpendicular angle incident, caused following point to take place:
1. as shown in Figure 3, the edge of semiconductor wafer 10 is far surpassed above-mentioned predetermined thickness value by the thickness that inert gas plasma 42 etches away; Wherein, above-mentioned predetermined etched thickness is about 180 dusts, etched thickness surpasses 300 dusts and at semiconductor wafer 10 edges, caused the apparent size of semiconductor wafer 10 inhomogeneous, increase the degree of difficulty of subsequent technique, and reduced the qualification rate of semiconductor technology indirectly, and increase the cost of semiconductor technology;
2. make the lateral margin of semiconductor wafer 10 be subjected to abnormal etching, and make the silicon effusion in the semiconductor wafer 10 produce some Silicon-rich particles (silicon-rich particle), as shown in Figure 4, above-mentioned Silicon-rich particle is not easy by quartz bell cover 220 adsorbed, cause the surface of semiconductor wafer 10 that particle pollution takes place, thereby reduce the qualification rate of semiconductor technology, the reliability of reduction product, or must increase another road cleaning again, to remove above-mentioned Silicon-rich particle, just can increase the cost and the complexity of semiconductor technology thus; And
3. make and be subjected to abnormal etching with the cap layer 112 that is close to semiconductor wafer 10, and the formation of etched recesses 116 shown in Fig. 1 and Fig. 2 is exactly to be subjected to undesired etched result because of the cap layer 112 that is close to semiconductor wafer 10, cause reduce the useful life of cap layer 112, on average produce 9 approximately, just must change after the 000 chip semiconductor wafer, increase the cost of semiconductor technology.
Fig. 4 is the electron micrograph of Silicon-rich particle described in above-mentioned 2, the upper limb of Fig. 4 wherein, and what arrow was indicated is the interlayer hole of semiconductor wafer 10.With respect to above-mentioned interlayer hole size, the size of the Silicon-rich particle among Fig. 4 seems quite huge, as not avoided or removing, can cause suitable adverse influence to the qualification rate of follow-up semiconductor technology.
In addition, come contained component in the composition of Silicon-rich particle shown in the analysis chart 4 with energy dispersed light spectrometer (EDS), its result as shown in Figure 5, wherein the abscissa among Fig. 5 is an energy, each element all can have a specific energy value; And ordinate is each atoms of elements number count value.The quantity of the silicon atom in the Silicon-rich particle in the displayed map as a result 4 among Fig. 5 far surpasses the due quantity of silicon atom in the general silicon dioxide, proves that therefore shown among Fig. 4 is a Silicon-rich particle.
In conventional art,, in order to improve the pollution problem of dust fall particle on the semiconductor wafer 10, and some solutions have been proposed at the plasma process shown in Fig. 1:
For example United States Patent (USP) the 5th, 410, in the plasma process that No. 122 propose, when reaction finishes, radio-frequency power supply 232,234 supply of can cutting off the electricity supply at once, make the electric charge on the semiconductor wafer 10 revert to neutrality rapidly, and the particle that is produced in the above-mentioned plasma process is dropped on rapidly on the surface of semiconductor wafer 10.Therefore, United States Patent (USP) the 5th, 410, in No. 122 disclosed technology contents, when above-mentioned plasma process finishes, still have positive charge, negative electrical charge or positive and negative staggered electric charge on the semiconductor wafer 10, make particle suspension in the top of semiconductor wafer 10 and do not drop on the surface of semiconductor wafer 10; And add horizontal applied forces such as high velocity air or magnetic field, the above-mentioned particle that is suspended in semiconductor wafer 10 tops is removed.
United States Patent (USP) the 6th for another example, 270, in No. 621 disclosed technology contents, be to make the interface equipment (not shown) of wafer base 100 charged, help capturing the particle (not shown) that is produced in the plasma process that shows among Fig. 1, re-use an extract system above-mentioned particle is detached plasma-reaction-chamber.
And for example United States Patent (USP) the 6th, 423, in No. 175 disclosed technology contents, be to make the interface equipment of wafer base shown in Fig. 1 100 impose blasting treatment, to strengthen its surface roughness, help capturing the particle that is produced in the plasma process shown in Fig. 1, and reduce peeling off of above-mentioned particle and drop on the surface of semiconductor wafer 10.
And for example United States Patent (USP) the 6th, 482, and in the plasma process that No. 331 propose, when the temperature of quartz bell cover 220 was reduced to below 100 ℃, particle attached to it can be peeled off because shrink, thereby drops on the surface of semiconductor wafer 10; Therefore, at United States Patent (USP) the 6th, 482, in No. 331 disclosed technology contents, be on quartz bell cover 220, to add a heater, to keep the temperature of quartz bell cover 220, prevent particle attached to it and peel off, thereby drop on the surface of semiconductor wafer 10 because shrink.
And for example United States Patent (USP) the 6th, 551, in No. 520 disclosed technology contents, it is the extract system of strengthening plasma-reaction-chamber, set up an aspirating hole in the wafer base 100 under semiconductor wafer 10, make the particle that is produced in the plasma process along with the air-flow of bleeding is discharged outside the plasma-reaction-chamber, drop in semiconductor wafer 10 lip-deep quantity to reduce above-mentioned particle.
In above-mentioned conventional art, drop in semiconductor wafer 10 lip-deep number of particles though can both reduce effectively, do not improve at the source of the particle that is produced in the plasma process shown in Fig. 1, and the generation of minimizing particle.Above-mentioned conventional art is also at being improved because of wafer base conductor layer 120 causes the cap layer 113 of 42 pairs of wafer bases of inert gas plasma and the undesired erosion that semiconductor wafer 10 edges are caused among Fig. 1.
Summary of the invention
In view of this, the plasma process that main purpose of the present invention is to provide a kind of wafer base and uses this wafer base, be applicable in the plasma reative cell and carry semiconductor wafer, can reduce the generation of minuteness particle in the plasma process, with the qualification rate that promotes technology, the reliability that reduces technology cost, lifting product.
The plasma process that another object of the present invention is to provide a kind of wafer base and use this wafer base, be applicable in the plasma reative cell and carry semiconductor wafer, can avoid in plasma process, the edge of semiconductor wafer is subjected to over etching, make semiconductor wafer be maintained uniform apparent size, reducing the degree of difficulty of subsequent technique, thus promote technology qualification rate, reduce the technology cost.
The plasma process that another purpose of the present invention is to provide a kind of wafer base and uses this wafer base, be applicable in the plasma reative cell and carry semiconductor wafer, can avoid in the plasma process, the cap layer of wafer base is subjected to abnormal etching and quickens consume, thereby prolong cap layer useful life, reduce the replacing frequency of cap layer, further to reduce the technology cost.
Wafer base among the present invention is applicable to carrying one wafer in the plasma reative cell, and comprise: an insulator has one first width; And a conductor layer, have one second width that is not more than above-mentioned first width, and second width is not less than the diameter of wafer, and conductor layer is embedded in the described insulator.
Preferably, described insulator more comprises a cap layer and a basalis.
Use the plasma process of this wafer base to comprise the following step among the present invention:
One plasma reative cell and semiconductor wafer is provided, wherein plasma-reaction-chamber comprises a wafer base, and wafer base comprises an insulator and a conductor layer, described insulator has one first width, and described conductor layer has one second width that is not more than first width, and second width is not less than the diameter of semiconductor wafer, and conductor layer is embedded in the insulator;
One pan feeding step places semiconductor wafer on the wafer base, and makes in the scope of semiconductor wafer directly over conductor layer; And
Produce a gaseous plasma with plasma-reaction-chamber, the bombarding semiconductor wafer.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment among the present invention is described in further detail.
Fig. 1 is a generalized section, the figure shows the action situation of a conventional wafer pedestal in a plasma reative cell;
Fig. 2 is the vertical view of conventional wafer pedestal;
Fig. 3 is a schematic diagram, the figure shows the conventional semiconductors wafer at the plasma process shown in Fig. 1, and the etched thickness in its edge far surpasses the problem of predetermined etched thickness value;
Fig. 4 is an electron micrograph, and this photo shows shown in Fig. 1 that the lateral margin of semiconductor wafer is subjected to abnormal etching in the plasma process, and the Silicon-rich particle that makes the silicon in the semiconductor wafer overflow and produce;
Fig. 5 is a schematic diagram, the figure shows the result who forms with contained element in the Silicon-rich particle composition shown in energy dispersed light spectrometer (EDS) analysis chart 4;
Fig. 6 is a generalized section, the figure shows the action situation of wafer base of the present invention in a plasma reative cell;
Fig. 7 A and Fig. 7 B are the drawing of a series of counter tube, the figure shows to implement among Fig. 1 conventional art and wafer base of the present invention and use after the plasma process of this wafer base, respectively semiconductor wafer and semiconductor wafer are detected the result of its dust fall amount;
Fig. 8 is a schematic diagram, and this figure has showed the plasma process that the uses wafer base of the present invention etched thickness to semiconductor wafer.
Embodiment
Shown in Fig. 6 is in the metallization process with semiconductor wafer 20, and the step that is used to remove the oxide of interlayer hole (via) the metal level (not shown) that (not shown) exposed to the open air is an example.In above-mentioned steps, as the source of inert gas plasma 44, remove the oxide or the metal oxide of the silicon on the semiconductor wafer 20 with argon gas (also can other gases).In other processing step, for example reactive ion etching or other can be used the semiconductor technology of plasma, the personnel that are familiar with this technology can be applied to wafer base of the present invention wherein, reach the effect that follow-up disclosed wafer base of the present invention can reach.
Comprise cylindrical insulator 610 and the conductor layer 620 that is embedded in the insulator 610 at the wafer base shown in Fig. 6 600.Insulator 610 can be subdivided into cap layer 612 and basalis 614 again.Wherein, the material of basalis 614 is preferably silicon dioxide, and has a groove 615 usually, and conductor layer 620 is embedded in the width or diameter range of groove 615.And the material of cap layer 612 is preferably quartzy, and is generally an interchangeable expendable parts (consumable parts), is covered on conductor layer 620 and the basalis 614, is used for bearing semiconductor wafer 20.In addition, the material of conductor layer 620 is preferably titanium, electrically connects and produce electric field with a radio-frequency power supply 234, and attraction inert gas plasma 44 hits on the semiconductor wafer 20.
Plasma-reaction-chamber among Fig. 6 still includes a quartz bell cover 220, as the outer wall of plasma-reaction-chamber; And the coil 240 that is positioned at quartz bell cover 220 outsides, wherein a coil 240 and a radio-frequency power supply 232 electrically connect, and conductor layer 620 also electrically connects with radio-frequency power supply 234, can make the argon gas ionization in the quartz bell cover 220 and form inert gas plasma 44, and drive that inert gas plasma 44 bombards on the semiconductor wafer 20 and the oxide skin(coating) of removing a predetermined thickness on the semiconductor wafer 20.In addition, quartz is a kind of crystalline form of silicon dioxide, so quartz bell cover 220 helps to adsorb the oxide particle that is produced in the above-mentioned plasma process, avoids above-mentioned oxide particle to fall within on the surface of semiconductor wafer 20, pollutes.
In the wafer base 600 of the present invention, the width of insulator 610 or diameter be greater than the diameter of semiconductor wafer 20, and the width of conductor layer 620 or diameter are not less than the diameter of semiconductor wafer 20 and be not more than the width of insulator 610 or diameter and being embedded in the insulator 610; The width of conductor layer 620 or diameter are preferably the diameter greater than semiconductor wafer 20, so that semiconductor wafer 20 pan feedings and when being placed on the wafer base 600, make things convenient for the aligning of semiconductor wafer 20, and make semiconductor wafer 20 can coincide with fully conductor layer 620 directly over.If when placing semiconductor wafer 20 on the wafer base 600 to have any part to exceed the area just above of conductor layer 620, this part will be as conventional art shown in Fig. 1, attract the bigger inert gas plasma 44 of density with non-perpendicular angle incident, the lateral margin that causes semiconductor wafer 20 etched uneven thickness, cap layer 612 to be subjected to undesired etching, semiconductor wafer 20 is subjected to undesired etching and produces the problem that suffers from the conventional arts such as surface of Silicon-rich particle pollution semiconductor wafer 20.In addition, the width of conductor layer 620 or diameter are more preferably less than the width or the diameter of insulator 610; If the width of conductor layer 620 or diameter are greater than the width or the diameter of insulator 610 or conductor layer 620 is not embedded in the insulator 610, and the conductor layer 620 of part is exposed to outside the insulator 610, the part that above-mentioned conductor layer 620 exposes to the open air will be subjected to the erosion of inert gas plasma 44, and can produce extra particle, pollute the surface of semiconductor wafer 20.
When semiconductor wafer 20 is one 8 inches wafers, the width of insulator 610 or typically have a diameter from about 9 inches, and the width of conductor layer 620 or typically have a diameter from 8 inches～9 inches, and the width of the conductor layer 620 shown in Fig. 6 or diameter are about 210mm.
In addition, when semiconductor wafer 20 was one 12 inches wafers, the width of insulator 610 or typically have a diameter from about 13 inches, and the width of conductor layer 620 or typically have a diameter from 12 inches～13 inches were preferably about 310mm.
Next the plasma process that uses wafer base 600 of the present invention shown in Fig. 6 is described.
At first, with semiconductor wafer 20 pan feedings, place on the cap layer 612 of the wafer base 600 in the plasma-reaction-chamber, will notice that semiconductor wafer 20 is placed in the position on the cap layer 612 this moment, must make semiconductor wafer 20 be contained in zone directly over the conductor layer 610 fully.Next, argon gas is imported in the plasma-reaction-chamber, and opened radio-frequency power supply 232,234, to produce inert gas plasma 44, the surface of bombarding semiconductor wafer 20.After reaction is finished, cut off the supply of argon gas and close radio-frequency power supply 232,234.At last, the semiconductor wafer 20 of finishing plasma process is withdrawed from outside the plasma-reaction-chamber, or use same plasma-reaction-chamber, carry out the plasma process of next stage.In addition, the personnel that are familiar with this technology also can be replaced into a reacting gas and a reactive ion plasma with above-mentioned argon gas and inert gas plasma 44, to carry out the technology of a reactive ion etching.
As shown in Figure 6, the width of conductor layer 620 or diameter are not less than the diameter of the semiconductor wafer 20 that wafer base 600 carried, make the density and the incident direction of near the inert gas plasma 44 semiconductor wafer 20 edges, do not have tangible change with the density and the incident direction of inert gas plasma 44 in other zone of semiconductor wafer 20.Therefore, the edge of semiconductor wafer 20 and cap layer 613 are not subjected to abnormal etching.
Shown in Fig. 7 A and Fig. 7 B, after relatively implementing conventional art shown in Figure 1 and the present invention, respectively the dust fall amount of semiconductor wafer 10 with semiconductor wafer 20 detected, wherein the ordinate shown in Fig. 7 A and Fig. 7 B is represented the number of particles on every wafer, and abscissa is represented inspected wafer.Can find out by Fig. 7 A and Fig. 7 B, the left side of separator bar 700 is the detection data of the semiconductor wafer 10 of enforcement conventional art, and the right side of separator bar 700 is the detection data of the semiconductor wafer 20 of the plasma process of enforcement wafer base of the present invention and use wafer base.And Fig. 7 A shows the total amount of particle on the inspected wafer; And Fig. 7 B shows the above-mentioned diameter of being examined on the wafer in the particle greater than the quantity of the particle of 2 μ m.
In Fig. 7 A, relatively separator bar 700 left sides implement the detection data of the semiconductor wafer 10 of conventional art among Fig. 1, implement wafer base of the present invention with separator bar 700 right sides and use this wafer base plasma process semiconductor wafer 20 the detection data as can be known: the number of particles of implementing on the semiconductor wafer 10 of conventional art shown in Fig. 1 is more, and distribution pattern is unstable, often has the situation of approaching upper control limit among the figure to take place; Implement wafer base of the present invention and use the number of particles on the semiconductor wafer 20 of plasma process of this wafer base that obvious minimizing is then arranged.And see it with mean value, number of particles mean value shown in enforcement Fig. 1 on the semiconductor wafer 10 of conventional art is about 5.2, and implement wafer base of the present invention and use the number of particles mean value on the semiconductor wafer 20 of plasma process of this wafer base to be about 2.9, have clear improvement than conventional art.
In Fig. 7 B, show quantitative aspects, conventional art and the of the present invention as a result no significant difference of diameter greater than the particle of 2 μ m.See it with mean value: on the semiconductor wafer 10 of implementing conventional art shown in Fig. 1, diameter is about 1.0 greater than the number of particles mean value of 2 μ m; And implementing wafer base of the present invention and using on the semiconductor wafer 20 of plasma process of this wafer base, diameter is about 0.8 greater than the number of particles mean value of 2 μ m, and hence one can see that, and enforcement of the present invention is to the quality of product and have no adverse effects.
Yet, in the control chart of Fig. 7 A and Fig. 7 B, all list all particles of being examined on the wafer in calculating, therefore the number of particles that these particles are produced in being included in conventional art or plasma process of the present invention, still during technology, just dropped on the number of particles of being examined wafer before being included in.Therefore, creator among the present invention has prepared each one group of the plasma-reaction-chamber shown in the plasma-reaction-chamber shown in Fig. 1 and Fig. 6, get semiconductor wafer 9, in 000 each half (4,500) implement the wafer base of the present invention shown in conventional art shown in Fig. 1 and Fig. 6 respectively and use the plasma process of this wafer base, special detection above-mentioned 9,000 wafer sees if there is the particle pollution from plasma-reaction-chamber shown in Fig. 1 or Fig. 6 ionic medium precursor reactant chamber.Wherein, in 4, the 500 chip semiconductor wafers of implementing conventional art shown in Fig. 1, check wherein 20 batches (totally 60), have 24 semiconductor wafer be subjected to from implement among Fig. 1 the particle pollution that do not produced during conventional art; And implementing wafer base of the present invention shown in Fig. 6 and using in 4,500 the semiconductor wafer of plasma process of this wafer base, check wherein 18 batches (totally 54) all to find no new particle pollution situation.
In sum, wafer base of the present invention and use the plasma process of this wafer base, can be reduced in the generation of minuteness particle in the plasma process effectively, promote technology qualification rate, reduce the technology cost and promote the reliability of product, reach the main purpose of the invention described above.
As shown in Figure 8, shown in this figure use among the present invention the etched thickness situation of semiconductor wafer 20 behind the wafer base 600 and plasma process.In Fig. 8, the predetermined etched thickness of semiconductor wafer 20 is about 180 dusts, and the zone beyond at semiconductor wafer 20 edges, the variation of etched thickness is little, all maintain about about 180 dusts, and at the edge of semiconductor wafer 20, etched thickness is brought up to a little and is about 210～220 dusts.Compare with the result of conventional art shown in Fig. 3, wafer base of the present invention and use the plasma process of this wafer base, can effectively avoid in plasma process, the edge of semiconductor wafer 20 is subjected to over etching, make semiconductor wafer 20 be maintained uniform apparent size, to reduce the difficulty in process degree in the subsequent technique, promote qualification rate, the reduction technology cost of technology, reach another purpose of the invention described above.
In addition, as shown in Figure 6, wafer base 600 among the present invention, has a conductor layer 620, wherein the width of conductor layer 620 or diameter are not less than the diameter of the semiconductor wafer 20 that wafer base 600 carried, thereby can avoid in plasma process, the cap layer 612 of wafer base 600 is subjected to abnormal etching and quickens consume, thereby prolong cap layer 612 useful life (as extending to 13000～30000), reduce the replacing frequency of above-mentioned cap layer, further to reduce the technology cost.Realize another object of the present invention.
In addition; though the above is described the preferred embodiment among the present invention; but can not be as protection scope of the present invention; promptly should be understood that to those skilled in the art; do not breaking away from variation and the modification that to make equivalence under the design spirit of the present invention to it; therefore, every not breaking away from the equivalence variation of having done under the design spirit of the present invention and modification, all should think to fall into protection scope of the present invention.
Claims (32)
1. a wafer base is applicable in the plasma reative cell and carries semiconductor wafer, comprises:
One insulator has one first width; And
One conductor layer has one second width that is not more than this first width, and this second width is not less than the diameter of semiconductor wafer, and this conductor layer is embedded in the described insulator.
2. according to the wafer base described in the claim 1, it is characterized in that: described insulator comprises a cap layer and a basalis, and wherein said conductor layer is between cap layer and basalis.
3. according to the wafer base described in the claim 2, it is characterized in that: described basalis comprises a groove, this groove has described second width, and described conductor layer is positioned at the width range of groove, and described cap layer is covered on described conductor layer and the basalis.
4. according to the wafer base described in the claim 1, it is characterized in that: described insulator is a silicon dioxide.
5. according to the wafer base described in the claim 1, it is characterized in that: described insulator is cylindrical.
6. according to the wafer base described in the claim 1, it is characterized in that: described conductor layer is a titanium.
7. according to the wafer base described in the claim 2, it is characterized in that: described cap layer is for quartzy.
8. according to the wafer base described in the claim 2, it is characterized in that: described basalis is a silicon dioxide.
9. according to the wafer base described in the claim 1, it is characterized in that: the diameter of described semiconductor wafer is 8 inches.
10. according to the wafer base described in the claim 1, it is characterized in that: described first width is 9 inches.
11. the wafer base according to described in the claim 1 is characterized in that: described second width is 8 inches～9 inches.
12. the wafer base according to described in the claim 1 is characterized in that: described second width is 210mm.
13. the wafer base according to described in the claim 1 is characterized in that: the diameter of described semiconductor wafer is 12 inches.
14. the wafer base according to described in the claim 1 is characterized in that: described first width is 13 inches.
15. the wafer base according to described in the claim 1 is characterized in that: described second width is 12 inches～13 inches.
16. the wafer base according to described in the claim 1 is characterized in that: described second width is 310mm.
17. a plasma process that uses this wafer base comprises the following step:
One plasma reative cell and semiconductor wafer is provided, wherein plasma-reaction-chamber comprises a wafer base, and wafer base comprises an insulator and a conductor layer, described insulator has one first width, and described conductor layer has one second width that is not more than first width, and second width is not less than the diameter of semiconductor wafer, and conductor layer is embedded in the insulator;
One pan feeding step places semiconductor wafer on the wafer base, and makes in the scope of semiconductor wafer directly over conductor layer; And
Produce a gaseous plasma with plasma-reaction-chamber, the bombarding semiconductor wafer.
18. the plasma process according to described in the claim 17 is characterized in that: described insulator more includes a cap layer and a basalis, and this conductor layer is between described cap layer and basalis.
19. according to plasma process described in the claim 18, it is characterized in that: described basalis comprises a groove, and this groove has described second width, and conductor layer is positioned at the width range of groove, and cap layer is covered on conductor layer and the basalis.
20. the plasma process according to described in the claim 17 is characterized in that: described insulator is a silicon dioxide.
21. the plasma process according to described in the claim 17 is characterized in that: described insulator is cylindrical.
22. the plasma process according to described in the claim 17 is characterized in that: described conductor layer is a titanium.
23. the plasma process according to described in the claim 18 is characterized in that: described cap layer is for quartzy.
24. the plasma process according to described in the claim 18 is characterized in that: described basalis is a silicon dioxide.
25. the plasma process according to described in the claim 17 is characterized in that: the diameter of described semiconductor wafer is 8 inches.
26. the plasma process according to described in the claim 17 is characterized in that: described first width is 9 inches.
27. the plasma process according to described in the claim 17 is characterized in that: described second width is 8 inches～9 inches.
28. the plasma process according to described in the claim 17 is characterized in that: described second width is 210mm.
29. the plasma process according to described in the claim 17 is characterized in that: the diameter of described semiconductor wafer is 12 inches.
30. the plasma process according to described in the claim 17 is characterized in that: described first width is 13 inches.
31. the plasma process according to described in the claim 17 is characterized in that: described second width is 12 inches～13 inches.
32. the plasma process according to described in the claim 17 is characterized in that: described second width is 310mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410034716 CN1287438C (en) | 2003-07-29 | 2004-04-26 | Wafer base and plasma technology using the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN03150013.7 | 2003-07-29 | ||
| CN03150013 | 2003-07-29 | ||
| CN 200410034716 CN1287438C (en) | 2003-07-29 | 2004-04-26 | Wafer base and plasma technology using the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1577790A CN1577790A (en) | 2005-02-09 |
| CN1287438C true CN1287438C (en) | 2006-11-29 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200410034716 Expired - Lifetime CN1287438C (en) | 2003-07-29 | 2004-04-26 | Wafer base and plasma technology using the same |
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| CN (1) | CN1287438C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157590B (en) * | 2014-08-21 | 2017-03-01 | 上海华力微电子有限公司 | electron beam defect scanning device and method |
| CN108206153B (en) * | 2016-12-16 | 2021-02-09 | 台湾积体电路制造股份有限公司 | Wafer bearing device and semiconductor equipment |
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| Publication number | Publication date |
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| CN1577790A (en) | 2005-02-09 |
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