CN1287333A - Improved method for simulating silicon device on insulator - Google Patents
Improved method for simulating silicon device on insulator Download PDFInfo
- Publication number
- CN1287333A CN1287333A CN 00126190 CN00126190A CN1287333A CN 1287333 A CN1287333 A CN 1287333A CN 00126190 CN00126190 CN 00126190 CN 00126190 A CN00126190 A CN 00126190A CN 1287333 A CN1287333 A CN 1287333A
- Authority
- CN
- China
- Prior art keywords
- voltage
- circuit
- model
- analysis
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
To simulate an SOI element by setting a floating body voltage to an optional desired value at the optional point of time during simulation by an electronic design model encoded by design software for the FET logic design of an SOI base. An ideal voltage source having a desired floating body voltage value is added to a model serially to an ideal current source having the value of the constant multiple of a voltage applied to itself. In the case a constant is zero, a current does not flow and an additional element does not affect a circuit. If the constant is not zero, the ideal current source is considered the same as a resistor, the current flows into a floating body node or flows out from there and the voltage is set.
Description
The present invention relates to the silicon-on-insulator integrated circuit, particularly relate in the time-delay of creating circuit design is calculated and be used to solve SOI FET buoyancy aid voltage method.
The application is the USSN 08/938,676 that submitted on September 26th, 1997, now is improvement and the part continuation of laid-open U.S. Patents US6023577 on the 8th February in 2000, and has required the right of priority of this application.Denomination of invention is the method that is used to simulate the SOI device, and the inventor is George E.Smith, III, etc.
Here inventor George E.Smith, III is included in the U.S.S.N.09/294 that submitted on April 19th, 1999 with the application of other relevant unexamined of other people, and 045, be used for improving one's methods of static regularly SOI device and circuit; The U.S.S.N.09/294 that on April 19th, 1999 submitted to, 163, be used for improving one's methods of static regularly SOI device and circuit; With the U.S.S.N.09 that submitted on April 19th, 1999,294,178, be used for improving one's methods of static regularly SOI device and circuit.
The application of these unexamined and the application have same assignee-New York A Mengke International Business Machines Corporation.
Therefore incorporate the instructions of these unexamined applications into the application as a reference.
Trade mark: S/390 and IBM are the registered trademarks of USA New York A Mengke International Business Machines Corporation.Other name may be the registered trademark or the name of product of International Business Machines Corporation or other company.
As background technology that will describing method, analogue technique has been used to produce silicon device, comprises that explained hereafter thin-film device by usually said silicon-on-insulator (also being called SOI) is to produce the SOI device.The performance of SOI device depends on the current voltage of this device (comprising circuit) buoyancy aid.And bulk voltage depends on the switching history of device (or circuit).The simulation that is used to produce silicon device (comprising circuit) comprises traditional Time delay measurement technology, but before the technical development that relates to of related application, does not solve the analogue technique of current bulk voltage influence.Solve the existing method of current bulk voltage historical influence or need under discussion simulation rule accurately, perhaps attempt to skip this problem.Two kinds of methods all are not suitable for the time-delay rule.Two kinds of methods do not allow to correct once operating simulation order.In theory, wholely switch the historical influence that can solve current bulk voltage by simulating, but this is unpractiaca, does not have the mode that solves this influence so technology is estimated in traditional time-delay.In addition, because some unequally loaded time-delays in dry run of common process measurement use simulation history not to be accepted.To depend on the difference of dry run order and provide the result who is difficult to expect simulating historical dependence.
We think needs a kind of method of simulating influence, can be used in the system of analog electrical time-delay, and such as the United States Patent (USP) 5,396,615 of Mitsubishi Denki K.K. and the United States Patent (USP) 5,384 of HitachiMicro Systems Inc., 720 is illustrated.These two is the general example as electric analogy and design system, and the present invention also can be used for other unconsummated so far system.
Should be noted that has now that a large amount of what how to utilize SOI device and use about other people is the publication and the patent of what analogue technique.Comprising the publication of in this patent disclosure, quoting with in first to file, be included in the Messrs.Dubois of International Business Machines Corporation, (E.) unpublished report in January, 1993; Shahidi, (G.G.) and Sun (J.Y.C.) the speed ability analysis of oscillator " the film CMOS/SOI diagnosis ", after being used for the feature performance benefit of small-sized analytic model analysed film SOI/CMOS ring oscillator to their body silicon counterpart of breadboardin, use points out that wherein the raising of the speed compared in body silicon of SOI in time can be held the viewpoint that reduces with threshold voltage, body doping coefficient and economize on electricity and explain.Also can utilize their tabulation model to obtain higher precision based on the DC current measurement of each device.In two kinds of methods, all found the remaining deviation between propagation delay simulation and that measure.Relatively overall current and the charge stored in ring oscillator recognized the root that this difference produces when underestimating charge/discharge current.These researchists determine that by analyzing impressed voltage and transmission delay the moment enhancing of electric current is not the reason of described difference.They discuss and find that the DC current characteristics of SOI device is very sensitive to grounding rule, have systematically explained inaccurate prediction to the time-delay of each grade by current analog.This report is the internal report of IBM, but its shows the influence of in the design of the SOI device current bulk voltage of simulation of having no idea, and has stated that the inaccurate prediction of by breadboardin time-delay having been done in this field gives dejected that the researchist caused.
We reach a conclusion, and need a kind of method of simulating current bulk voltage influence in the design of SOI circuit devcie, but up to the present also do not have other people to realize this method.In the achievement described in the application in IBM past, the SOI device of part depletion has kept the stored charge in the device body.This electric charge causes " bulk voltage ".Bulk voltage and then influenced the threshold voltage (VT) of device and influenced the performance of circuit thus.
In the past, for the body silicon device, this influence is unimportant.First related application of quoting is the USSN 08/938 of application on September 26th, 1997,676, now be laid-open U.S. Patents No.6023577 on February 8th, 2000, this application has been described and a kind of bulk voltage can be set randomly, or the method for bulk voltage is set by the variation of technology.The bulk voltage of actual measurement is not a completely random.Other relevant open in this method of demonstration show the method that trial shows the influence of bulk voltage more accurately.
Need to improve in the past obtained progress, we will introduce a kind of more special method with estimated body voltage.Though this method and so general unlike in the mother application, it is more accurate in its application.
As described below, we develop a kind of method, are used for during simulating the value that buoyancy body voltage at any time is set to any needs.The method of the analysis circuit that provides in existing application is that the SOI transistor body selects a voltage, this voltage limit institute might voltage.How many methods in the application that other are mentioned has dwindled possibility.Here, we may be in the AC balance at which part of analysis circuit, and this part is carried out special processing.We consider that also the different piece of analyzed circuit has the situation of different history, and recognize that now the history that all transistors of hypothesis have " soon " or " slowly " is not enough.
In addition, which part by analysis circuit may be in the AC balance, and is regular by using the obtained improvement of this method to allow the designer easily to set up their the practicable time-delay of current design method.Once in service, the designer can repeatedly simulate, and obtains identical result, and and sequence independence.Because our method is now known restricted in performance, but the designer needn't constantly attempt importing and historical various combination to find best and value worst condition.The improvement of these and other will be set forth in detailed description subsequently.Advantage for a better understanding of the present invention and feature, the drawings and detailed description that reference is following:
Fig. 1 shows our said buoyancy aid and current bulk voltage is the current bulk voltage of B point (internal buoyancy node), and wherein the B point is a body.
Fig. 2 shows the open improvement of being done of Fig. 1.
According to the present invention, with reference to figure 1, we have developed a kind of method that is used to simulate the model of SOI device, generally include following step: by in model, increasing the ideal current source of an ideal voltage source and series connection with it, any time buoyancy aid voltage during simulating is set to the value of any needs, wherein the value of voltage source is required bulk voltage, and a constant of the value of current source (being called GJ) multiply by the voltage at its two ends.Said as us, Fig. 1 shows our said buoyancy aid and current bulk voltage is the current bulk voltage of B point (internal buoyancy node), and wherein the B point is a body.This figure not only is applicable to NFET but also be applicable to PFET.In Fig. 1, shown in element below Fig. 1, be illustrated by label.In Fig. 1, numeral 1 expression ideal voltage source, numeral 2 expression ideal current sources.
When constant GJ is zero, there is not electric current to flow, additional element is to not influence of circuit.When constant GJ non-zero, it is the same with resistance that ideal current source seems.Therefore, electric current can flow to or flow out body node so that the voltage of body node to be set.
Constant GJ remains zero always except when needs change bulk voltage.
Select the value of ideal voltage source to need two steps so that required buoyancy aid voltage to be set.At first, can calculate static body voltage uniquely by terminal voltage and the temperature of considering device.This voltage is not for carrying out for a long time the voltage that body is determined naturally behind the change action.
By this benchmark quiescent voltage, dissimilar according to possible change action can be found the boundary that this voltage changes.For example, increase the grid voltage of device, keep source electrode and drain voltage constant simultaneously, can produce specific influence bulk voltage.
Consider that all possible switching type will provide the possible scope that voltage changes around static body voltage.According to desirable analog type, we can at random select one and change quiescent voltage from these voltages, to represent the switching history of this device the unknown,, perhaps select value preferably given or the worst condition time-delay perhaps according to value of the historical selection of known switching.
Owing to can reset bulk voltage in any moment that we need, we can solve continuous latency issue in a simulation process by resetting voltage before beginning at each Time delay measurement.
In order to solve the problem of prediction time-delay in time-delay precursor (for example, the regular generator of delaying time), can be by the skew of bulk voltage a part as definite best-case/worst condition.For example, the fastest time-delay of circuit be found, except selecting the fastest technology and environmental variance, the bulk voltage of given the fastest time-delay can also be selected.For example, these can be finished automatically by the AS/X (explanation below) that IBM sells.
This method by the AS/X system of IBM or for example other circuit simulator of SPICE adopt the model of simulation SOI to realize, and use any SOI designer can use this method based on the FET logic.These methods can be encoded in the Electronic Design software of standard, and describe in their file usually.
Now, we must understand that in fact voltage is not at random.With reference to figure 2, below us in the described improvement, compared to Figure 1, we will illustrate in Fig. 2 and show circuit in the drawings and describing subsequently.This is the part of a latch cicuit of widely used standard in our circuit.
Find out easily that by Fig. 2 the path that we were concerned about is by a right side to circuit in two inputs.All have slow history if suppose all transistors, obviously the time-delay of path also can be slow, and also similar for fast history, time-delay also can be fast.Yet in this circuit, time-delay is not unique item of being concerned about.We also are concerned about the relative time by the signal arrival of " clock " and " data " input.For example, this can be used for calculating the Time Created of latch.
In most system, the mode long-time running of clock to repeat.Therefore, will soon understand that for example, transistor T 0 and T3 must be in the bulk voltage state of AC steady state (SS).
Yet the data input is uncertain.Its value will obtain according to the accurate Calculation of carrying out in the circuit.Therefore, need the numeric data code type of hypothesis in the transistor of for example T2 and T5 for example to have slow history.In addition, also fast history can be arranged, perhaps other any possible history between these values for these transistors.
Therefore, we can classify all transistors by simple topological analysis according to transistorized end signal.Here, we can be called " clock " transistor to T0 and T3.This is because their grid is connected to clock signal, and their source electrode and drain electrode are connected to power supply.
Similarly, T2 and T5 can be categorized as " data " transistor.This is because their grid is connected to data-signal, and their source electrode and drain electrode are connected to power supply.Remaining transistor T 1 and T4.Source electrode and drain electrode have the characteristic of class likelihood data because their grid depends on clock signal, and we are called them in " mixing " transistor.Though can't see usually, " mixing " transistor of another kind of type have on the grid data-signal and the drain electrode on clock signal.
Therefore, we have revised disclosed transistorized model in the past, to allow specifying historical type clearly.By realizing from the scope that is worth fast value slowly.The above topology analysis is told us which kind of transistor belongs to.For example, " clock " transistor only need be appointed as equilibrium value.Because grid voltage is switching, so we can do so always.On the other hand, owing to do not know history, must allow the four corner of hypothesis " data " transistorized bulk voltage value.
Can simplify by merging transistorized " clock " and " mixing " group.According to our simulation, can produce a spot of mistake like this, and allow to simplify topological analysis.This step is optionally, can keep all transistors of four types to carry out detail analysis.
Our method can be used as one group of AS/X model and realizes, is used for the time-delay rule generator of java standard library usage.
Though described the preferred embodiments of the present invention, should be understood that the present and the future those skilled in the art can do various improvement and raising in the scope of subsequently claims.These claims are used to explain the at first of the present invention suitable protection domain of explanation.
Claims (18)
1. one kind comprises the method for using in the model of SOI device of SOI circuit in simulation, may further comprise the steps:
The ideal current source which part by analysis circuit may be in the AC balance and increase an ideal voltage source and series connection with it in model, any moment buoyancy aid voltage during simulating is set to the value of any needs, wherein the value of voltage source is required bulk voltage, and the value of current source is that a constant multiply by the voltage at its two ends.
2. the method for using according to the model in the claim 1 wherein when constant is zero, does not have electric current to flow, and any additional element is to not influence of circuit.
3. according to the method for the use of the model in the claim 2, wherein when the constant non-zero, it is the same with resistance that described ideal current source seems, electric current can flow to or flow out body node thus, and the voltage of body node is set.
4. according to the method for the use of the model in the claim 3, wherein said constant remains zero always except when needs change bulk voltage.
5. the method for using according to the model in the claim 4, wherein required buoyancy aid voltage will be set by the value of selecting ideal voltage source, wherein at first, can only calculate static body voltage by terminal voltage and the temperature of considering device, be the definite naturally voltage of body after not carrying out change action for a long time at static body voltage described in this step.
6. the method for using according to the model in the claim 5, wherein by described benchmark quiescent voltage, dissimilar according to possible change action can be found the boundary that this voltage changes.
7. the method for using according to the model in the claim 6 wherein by increasing the grid voltage of this device, keeps simultaneously that source electrode and drain voltage are constant will to produce specific influence to bulk voltage, can find the boundary that described static body voltage changes.
8. the method for using according to the model in the claim 6 is wherein considered all possible switching type and after considering all switching types, is given in the possible scope of the change of voltage on every side of static body voltage.
9. the method for using according to the model in the claim 5 comprises that the skew that bulk voltage is provided is as the step of determining best-case/worst condition.
10. the method for using according to the model in the claim 5 comprised before beginning at each Time delay measurement and resets voltage, and any moment that needs in simulation is reset the step of described bulk voltage.
11. according to the process of claim 1 wherein that described method is encoded in the design software of use based on the SOI of FET logical design.
12. method according to claim 1, wherein be equilibrated at the value that any moment during the simulation can buoyancy aid voltage be set to any needs when which part by analysis circuit may be in AC, the end signal by the testing circuit element carries out the topological analysis of device by the affiliated type of the circuit component determining to be analyzed.
13. according to the method for claim 12, wherein said topological analysis is in order to analyze grid element, and determines in analysis whether described grid element is connected to periodic signal.
14. according to the method for claim 13, if determine during topological analysis that wherein grid element switches repeatedly, determines that then grid element is the AC balance.
15. according to the method for claim 12, wherein said topological analysis is in order to analyze drain elements, and determines in analysis whether described drain elements is connected to periodic signal.
16.,, determine that then drain elements is the AC balance if wherein determine of the switching of described drain elements at the topological analysis period according to the method for claim 15.
17. method according to claim 12, wherein said topological analysis comprises a plurality of circuit components of test, and determine in analysis whether described element is connected to periodic signal, if the both does not connect periodic signal, then can not suppose the affiliated type of being analyzed of circuit component.
18. method according to claim 12, wherein said topological analysis comprises that test comprises the analysis circuit of a plurality of circuit components, and determine in analysis whether described element is connected to periodic signal, if in the described element one connects periodic signal and another does not connect periodic signal, determine that then the circuit of being analyzed belongs to the circuit component of mixed type.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/388,594 | 1999-09-02 | ||
| US09/388,594 US6141632A (en) | 1997-09-26 | 1999-09-02 | Method for use in simulation of an SOI device |
| FR09/388,594 | 1999-09-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1287333A true CN1287333A (en) | 2001-03-14 |
| CN1171168C CN1171168C (en) | 2004-10-13 |
Family
ID=23534750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB001261908A Expired - Fee Related CN1171168C (en) | 1999-09-02 | 2000-08-31 | Improved method for simulating silicon device on insulator |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP3418975B2 (en) |
| CN (1) | CN1171168C (en) |
| IL (1) | IL137596A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1649120B (en) * | 2004-01-04 | 2010-09-29 | 泰拉丁公司 | Silicon-on-insulator channel architecture for automatic test equipment |
| CN101989542A (en) * | 2009-07-29 | 2011-03-23 | 国际商业机器公司 | Method of fabricating a device |
-
2000
- 2000-07-31 IL IL13759600A patent/IL137596A/en not_active IP Right Cessation
- 2000-08-31 JP JP2000263994A patent/JP3418975B2/en not_active Expired - Fee Related
- 2000-08-31 CN CNB001261908A patent/CN1171168C/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1649120B (en) * | 2004-01-04 | 2010-09-29 | 泰拉丁公司 | Silicon-on-insulator channel architecture for automatic test equipment |
| CN101989542A (en) * | 2009-07-29 | 2011-03-23 | 国际商业机器公司 | Method of fabricating a device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001148427A (en) | 2001-05-29 |
| IL137596A0 (en) | 2001-07-24 |
| CN1171168C (en) | 2004-10-13 |
| IL137596A (en) | 2003-11-23 |
| JP3418975B2 (en) | 2003-06-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4603492B2 (en) | System, method and software for analyzing substrate noise | |
| KR100510035B1 (en) | Method of estimating deterioration due to hot carries | |
| US7313771B2 (en) | Computing current in a digital circuit based on an accurate current model for library cells | |
| Ahmadi et al. | Timing analysis in presence of power supply and ground voltage variations | |
| Rao et al. | Switch-level timing simulation of MOS VLSI circuits | |
| US20090119085A1 (en) | Method and system for modeling dynamic behavior of a transistor | |
| US6141632A (en) | Method for use in simulation of an SOI device | |
| US20040054974A1 (en) | Method and system for power node current waveform modeling | |
| CN1171168C (en) | Improved method for simulating silicon device on insulator | |
| US6023577A (en) | Method for use in simulation of an SOI device | |
| Mahapatra et al. | A CAD framework for co-design and analysis of CMOS-SET hybrid integrated circuits | |
| Williams | Temporal qualitative analysis: explaining how physical systems work | |
| US6601220B1 (en) | Method for transistor-level calculation of the precharge time of domino logic circuits with unlocked evaluation paths | |
| US6928626B1 (en) | System and method for modeling of circuit components | |
| JP2004506268A (en) | Automatic verification of periodic operating conditions for SOI circuit simulation | |
| CN110619132B (en) | Method and apparatus for adaptive voltage scaling | |
| Schaefer | A transistor-level logic-with-timing simulator for MOS circuits | |
| Neves et al. | Buffered clock tree synthesis with non-zero clock skew scheduling for increased tolerance to process parameter variations | |
| US6836871B2 (en) | Process and system for developing dynamic circuit guidelines | |
| JP2001357093A (en) | Method and device for simulating circuit, and storage medium | |
| US8904336B1 (en) | Determination of meta-stable latch bias voltages | |
| SCHMID | FWF-Proposal DMAC: Digital Modeling of Asynchronous Integrated Circuits for Fast Dynamic Timing Analysis and Formal Verification | |
| Lee et al. | Fast timing analysis of transistor-level full custom digital circuits | |
| JPH10301983A (en) | Power consumption calculation method | |
| Prasad et al. | University Of Massachusetts Lowell’S Dynamic Switch–Level Simulator For Mos Technology-Based Vlsi Chips |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| REG | Reference to a national code |
Ref country code: HK Ref legal event code: GR Ref document number: 1060425 Country of ref document: HK |
|
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20041013 Termination date: 20110831 |