CN1284221C - Locating structure and locating method thereof - Google Patents
Locating structure and locating method thereof Download PDFInfo
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- CN1284221C CN1284221C CN 200310109858 CN200310109858A CN1284221C CN 1284221 C CN1284221 C CN 1284221C CN 200310109858 CN200310109858 CN 200310109858 CN 200310109858 A CN200310109858 A CN 200310109858A CN 1284221 C CN1284221 C CN 1284221C
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Abstract
The present invention discloses a positioning structure. The present invention comprises a plurality of point patterns and a plurality of ruler-shaped patterns, which are arranged on a semiconductor test sheet. Each ruler-shaped pattern is provided with a straight line pattern and a plurality of scales, wherein the ruler-shaped patterns are used for connecting every two point patterns, and the semiconductor test sheet is divided into a plurality of areas. The present invention also discloses a positioning method. Firstly, the positioning structure is formed on the semiconductor test sheet; the semiconductor test sheet is observed under a microscope, and voltage is applied to make defects of the semiconductor test sheet emit light; finally, a detailed position of the luminous defect is positioned according to the positioning structure.
Description
Technical field
The invention relates to a kind of location structure and localization method thereof, and particularly relevant under microscopic examination in order to the location structure and the localization method thereof of location semiconductor test piece.
Background technology
In order to promote the qualification rate of semiconductor subassembly, wafer must have good gate oxide integrity (GateOxide Integrity; GOI), low p/n engages leakage current (junction leakage) and enough pollutant adsorbances (gettering capacity).Above-mentioned these wafer characteristics are all closely bound up with the manufacture process of wafer.For instance, gate oxide integrity engage with p/n leakage current all with wafer in the lattice particulate of active layers (Crystal Originated Particle, COP) quantity is relevant.The lattice granule amount is many more, and then gate oxide integrity is poor more, and it is big more that p/n engages leakage current.And p/n joint leakage current is also relevant with the pollutant levels of wafer active layers, and pollutant levels are big more, and it is also big more that p/n engages leakage current.
In known technology, earlier with microscope, for example (emission microscope EMMI), observes gate oxide integrity to the low-light microscope usually.If when observing, find to have defective in the gate oxide, then again with ESEM (scanning electron microscope, SEM), focused ion beam, electrically analyze or other physical means characteristic of this defective of measure analysis further.Typical gate oxide integrity test piece size is about 1000 microns * 1000 microns, but the defective of its gate oxide is very small, and actual size is about 0.1 micron * 0.1 micron.On the other hand, along with the increase of microscope enlargement ratio, the visual field of microscopically is contracted to 122 microns * 122 microns, and the luminous defect size that this moment, the low-light microscope can be resolved is about 5 microns * 5 microns.
That is to say, if use the gate oxide integrity test piece of these 1000 microns * 1000 microns of low-light microscopic examinations, 122 microns * 122 microns within sweep of the eye, the defective of 0.1 micron * 0.1 micron size can present the luminous bright spot that size is about 5 microns * 5 microns.Because the size disparity of luminous defective and test piece is too big, therefore though have luminous defective can be from the low-light microscopic examination to test piece, but be difficult to determine the correct provider location of luminous defective on wafer, when so making this luminous defective of further measure analysis, very be difficult to locate the position of this luminous defective.
Known technology provides a kind of method of improving the defect location problem with laser markings.With the position of luminous defective in the low-light microscopic examination test piece, then test piece is moved to the laser board earlier, near the position of this luminous defective, burn mark, to help the position of this luminous defective of location in ensuing measure analysis.Yet, in this process,, therefore must rely on naked eyes to adjust the Position Approximate of laser focusing because low-light microscope and laser board do not combine.This laser burn the position that not only may and the actual defects position between have very big range error, and more may on wafer, cause new artificial defect (artificial defect), thereby influence electrically showing of gate oxide reality with rerum natura.Moreover this orientation problem makes that also (Failure Analysis FA) is difficult to carry out smoothly, reduces the efficient of whole wafer sort process in failure analysis.
Summary of the invention
Therefore purpose of the present invention is providing a kind of location structure exactly, for location semiconductor test piece when microscopic examination, correctly locatees the defective locations in the semiconductor test piece, avoids known artificial defect to influence the characteristic of actual defects.
Another object of the present invention is that a kind of method of locating the defective of gate oxide integrity test piece is being provided, and improves the correctness of semiconductor test piece location, and improves the efficient of the flow process of failure analysis with the enhancement test process.
According to above-mentioned purpose of the present invention, a kind of location structure and localization method thereof are proposed.This location structure comprises several point-like patterns and several chi shape patterns are positioned in this semiconductor test piece.Each chi shape pattern has a straight-line pattern and several scales, wherein connects with one of those chi shape patterns between two adjacent those dot patterns, and this semiconductor test piece is divided into several zones.This localization method comprises: at first, form this location structure in the semiconductor test piece, again with the test piece of microscopic examination semiconductor, apply the defect luminescence that a voltage makes the semiconductor test piece this moment again.At last, according to location structure, locate the detail location of this luminous defective.
According to a preferred embodiment of the present invention, this semiconductor test piece is a gate oxide integrity test piece, this test piece comprises a silicon substrate, and a gate oxide is positioned on this silicon substrate, and a polysilicon layer is positioned on this gate oxide and an oxide layer is positioned on this polysilicon layer.The material of those dot patterns and those chi shape patterns comprises metallic aluminium.This location structure also comprises several reference patterns, is surrounded on those regional outermost to indicate each zone.
Moreover those zones are square region, and each zone is of a size of 10000 square microns, and the size of those dot patterns is less than 25 square microns.Each chi shape pattern has several different types of scales, to indicate the detail location in each zone.In addition, this localization method also comprises according to this location structure, utilizes laser to burn a mark around this luminous defective, to help the detail location of this luminous defective of location.
The present invention forms a location structure in the semiconductor test piece, and utilizes the pattern of location structure to help correctly to locate the detail location of luminous defective under microscopic examination.This location structure is formed in the wafer and originally is the position of metal level, is a simple processing procedure easy to implement, is easy to be integrated among the test process, with the flow process of improving failure analysis and the efficient of promoting test process.And, when wanting this luminous defective of further measure analysis, can clearly find the detail location of luminous defective according to the present invention, and the destruction that can not cause artificial defect to it, therefore can be correctly and intactly finish the detection of gate oxide integrity.
Description of drawings
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Figure 1A is the flow chart of a preferred embodiment of the present invention;
Figure 1B is the side schematic view of the gate oxide integrity test piece in the preferred embodiment of the present invention;
Fig. 2 A is the schematic diagram of a preferred embodiment of location structure of the present invention; And
Fig. 2 B is the enlarged diagram of the location structure of Fig. 2 A.
Embodiment
Figure 1A is the flow chart of a preferred embodiment of the present invention, and Figure 1B is the side schematic view of the gate oxide integrity test piece in this preferred embodiment.This preferred embodiment is the detail location of locating the defective of a gate oxide integrity test piece with location structure of the present invention.Shown in Figure 1B, this gate oxide integrity test piece 110 comprises a silicon substrate 112, and being positioned on this silicon substrate 112 is a gate oxide 114, and being positioned on this gate oxide 114 is a polysilicon layer 116 and to be positioned on this polysilicon layer 116 be an oxide layer 118.
Localization method of the present invention is to form location structure 122 (step 102) earlier in gate oxide integrity test piece 110.Observe gate oxide integrity test piece 110 with low-light microscope 132 again, apply the defect luminescence (step 104) that a voltage makes gate oxide integrity test piece 110 this moment again.Wherein, (Charge Coupled Device, CCD) detector is detected visible light and the infrared light that luminous defective is sent to this low-light microscope 132 with inductance coupling assembly.At last, according to location structure 122 of the present invention, locate the detail location (step 106) of this luminous defective.
Fig. 2 A is the schematic diagram of a preferred embodiment of location structure of the present invention, and Fig. 2 B is the enlarged diagram of the location structure of Fig. 2 A.Shown in Fig. 2 A, location structure 122 of the present invention comprises several point-like patterns 202 and several chi shape patterns 204, and those chi shape patterns 204 connect those dot patterns 202, and gate oxide integrity test piece 110 is divided into several square region 210.The size of whole gate oxide integrity test piece 110 is about 1000 microns * 1000 microns, and the size of each square region 210 is about 100 microns * 100 microns, and promptly 10000 square microns are required with the field range that meets microscopically.
In this preferred embodiment, this location structure 122 also comprises several reference patterns 206, is surrounded on the outermost of those square region 210, and is corresponding to one to one to indicate each square region 210.Moreover in this preferred embodiment, the material of location structure 122 of the present invention comprises metallic aluminium, and be formed at the top of the oxide layer 118 of Figure 1B, be the position of known metal level, so its processing procedure is simple, the test piece preparation process of test process is reached easily.
Shown in Fig. 2 B, each chi shape pattern 204 has a straight-line pattern and several different types of scale 214a, 214b and 214c, represents 50 microns, 10 microns and 5 microns respectively, so at length to indicate the position of luminous defective 212 in each square region 210.In this preferred embodiment, those dot patterns 202 are of a size of 3 microns * 3 microns, and scale 214a is of a size of 0.3 micron * 3 microns, and scale 214b is of a size of 0.3 micron * 2 microns and scale 214c and is of a size of 0.3 micron * 1 micron.Because the luminous defect size that the low-light microscope can be resolved is about 5 microns * 5 microns, therefore the size of each above-mentioned pattern must just can not hinder the low-light microscope and detect luminous defective less than 25 square microns.
Moreover in localization method of the present invention, the step according to the detail location of the luminous defective in location structure 122 location can have multiple different execution mode.For instance, except directly read location structure of the present invention with understand luminous defective locations, the present invention can use microscope collocation routine analyzer, difformity and size with reference to the dot pattern among Fig. 2 A 202, chi shape pattern 204 and reference pattern 206, detected luminous defective locations is stored in the location cache, for another measurement platform with reference to and the position of correctly orienting luminous defective so cooperatively interacts and improves the process of failure analysis.
And because location structure of the present invention is the entity structure that is positioned in the test piece, its fixed-site and be difficult for being destroyed by the measurement process therefore can be for different measurement platform circulation uses according to its defective locations data of orienting.In addition, the present invention can also cooperate location structure by laser, burns a mark around luminous defective, to help the detail location of this luminous defective of location.Because the laser board has the auxiliary of location structure of the present invention when focusing on, therefore its burn the mark that can more approaching luminous defective, and can avoid on wafer, causing artificial defect, therefore reducing known laser markings influences the problem that gate oxide is electrically actual and rerum natura shows.
Claims (11)
1. a location structure supplies location semiconductor test piece when microscopic examination, and this location structure comprises at least:
Several point-like patterns are positioned in this semiconductor test piece; And
Several chi shape patterns, each chi shape pattern has a straight-line pattern and several scales, wherein connects with one of those chi shape patterns between two adjacent those dot patterns, and this semiconductor test piece is divided into several zones.
2. location structure as claimed in claim 1, wherein this semiconductor test piece is a gate oxide integrity test piece, this gate oxide integrity test piece comprises at least:
One silicon substrate;
One gate oxide is positioned on this silicon substrate;
One polysilicon layer is positioned on this gate oxide; And
One oxide layer is positioned on this polysilicon layer.
3. location structure as claimed in claim 1, wherein the material of those dot patterns and those chi shape patterns comprises metallic aluminium.
4. location structure as claimed in claim 1, wherein this location structure also comprises several reference patterns, is surrounded on those regional outermost to indicate each zone.
5. location structure as claimed in claim 1, wherein those zones are square region.
6. location structure as claimed in claim 1, wherein each zone is of a size of 10000 square microns, and the size of those dot patterns is less than 25 square microns.
7. location structure as claimed in claim 1, wherein each chi shape pattern has several different types of scales, to indicate the detail location in each zone.
8. the method for defective of location one a gate oxide integrity test piece, this method comprises at least:
Form a location structure in this gate oxide integrity test piece, this location structure comprises at least:
Several point-like patterns;
Several chi shape patterns, each chi shape pattern has a straight-line pattern and several scales, wherein connects with one of those chi shape patterns between two adjacent those dot patterns, and this gate oxide integrity test piece is divided into several square region; And
Several reference patterns are around the outermost of those square region, to indicate each square region;
With this gate oxide integrity test piece of microscopic examination, and apply the defect luminescence that a voltage makes this gate oxide integrity test piece; And
According to this location structure, locate the detail location of this luminous defective.
9. localization method as claimed in claim 8, wherein this method also comprises:
According to this location structure, utilize laser around this luminous defective, to burn a mark, to help this luminous defective of location.
10. localization method as claimed in claim 8, wherein the material of this location structure comprises metallic aluminium.
11. localization method as claimed in claim 8, wherein each chi shape pattern has several different types of scales, to indicate the detail location in each square region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310109858 CN1284221C (en) | 2003-12-30 | 2003-12-30 | Locating structure and locating method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200310109858 CN1284221C (en) | 2003-12-30 | 2003-12-30 | Locating structure and locating method thereof |
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| Publication Number | Publication Date |
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| CN1635621A CN1635621A (en) | 2005-07-06 |
| CN1284221C true CN1284221C (en) | 2006-11-08 |
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| CN 200310109858 Expired - Fee Related CN1284221C (en) | 2003-12-30 | 2003-12-30 | Locating structure and locating method thereof |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101728293B (en) * | 2009-11-10 | 2013-04-17 | 上海宏力半导体制造有限公司 | Method for gate oxide integrity (GOI) test of MOS transistor devices |
| CN101770070B (en) * | 2009-12-31 | 2016-09-07 | 上海杰远环保科技有限公司 | The survey meter of observation of micro object and operational approach |
| CN106019118A (en) * | 2016-05-18 | 2016-10-12 | 上海华虹宏力半导体制造有限公司 | Method for determining invalid position of power MOS |
| CN107688230B (en) * | 2017-09-26 | 2021-03-12 | 京东方科技集团股份有限公司 | Microscope for marking bad lines of liquid crystal screen |
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| CN1635621A (en) | 2005-07-06 |
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Effective date of registration: 20111205 Address after: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai Zhangjiang Road, Zhangjiang High Tech Park of Pudong New Area No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
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Granted publication date: 20061108 Termination date: 20181230 |