CN1282026A - Automatic switching control device for dynamic random access memory - Google Patents
Automatic switching control device for dynamic random access memory Download PDFInfo
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- CN1282026A CN1282026A CN99111125A CN99111125A CN1282026A CN 1282026 A CN1282026 A CN 1282026A CN 99111125 A CN99111125 A CN 99111125A CN 99111125 A CN99111125 A CN 99111125A CN 1282026 A CN1282026 A CN 1282026A
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Abstract
The automatic switch-over control device of dynamic random access memory is mainly applicable to starting test of input/output system, and when if the first 64 k memory segment of dynamic random access memory bank is failed and unable to start system, it utilizes the software and hardware operation to automatically switch to memory segment of other address, so that when first 64 k memory segment of dynamic radom access memory is failed, the basic input/output system can be crossed, and can be transferred to the memory segment of other address to continuously make test, so that it can prevent that said system is incapable of being started due to the first 64 memory segmemt is failed.
Description
The present invention relates to a kind of automatic switching control device for dynamic random access memory, mainly be to be applied to test in the starting up when basic input/output, in the time of can't start-up system if find first 64K memory paragraph of dynamic RAM memory bank (Bank) to lose efficacy (Fail), will automatically switch to the memory paragraph of other address, so that reach the purpose of start-up system.
General computer system all can be by basic input/output (BIOS) selftest (the Power On Self-Test that starts shooting earlier when starting; POST), the normal program that just can finish the starting up afterwards to be tested.In starting up's test, lost efficacy if run into first 64K memory paragraph of dynamic RAM, then computer system can't start.Owing to being that a fraction of memory paragraph inefficacy causes computer system to start shooting, even user's this moment has many again memory paragraph capacity also lack scope for their abilities, this is a very big problem, must solve.
For this reason, fundamental purpose of the present invention provides a kind of dynamic RAM (DRAM) automatic switching control device, can automatically reach starting up's purpose with other address memory paragraph under the cooperation of hardware and software, to address the above problem.
In order to achieve the above object, the present invention proposes a kind of automatic switching control device for dynamic random access memory, when basic input/output test finds that first 64K memory paragraph of dynamic RAM memory bank (Bank) lost efficacy and can't start-up system the time, just automatically switch to the memory paragraph of other addresses, to reach the purpose of start-up system, it comprises at least:
One output terminal selecting arrangement is in order to select the specific output terminal of gating one;
One switches selecting arrangement, its input end couples one group of first address signal, and according to the output of above-mentioned output terminal, and, export above-mentioned dynamic RAM to above-mentioned first address signal or second address signal that obtains through a certain operations by above-mentioned first address signal;
Wherein, when above-mentioned basic input/output finds that first 64K memory paragraph of above-mentioned dynamic RAM memory bank lost efficacy, above-mentioned basic input/output will write a particular value in register, the above-mentioned above-mentioned output terminal of output terminal selecting arrangement gating and export above-mentioned particular value, impel above-mentioned switching selector to export above-mentioned second address signal, basic input/output is proceeded test afterwards; When basic input/output did not find that memory paragraph lost efficacy, above-mentioned switching selector kept above-mentioned first address signal of output.
Above-mentioned first address signal is the part of memory paragraph address signal in system's address bus, and other memory paragraph address signal then is coupled to above-mentioned dynamic RAM respectively in the address bus.
Above-mentioned output terminal selecting arrangement, its input end coupling system address bus, after above-mentioned basic input/output writes register with above-mentioned particular value, the address signal of above-mentioned output terminal selecting arrangement decoding said system address bus and the above-mentioned output terminal of gating.
Above-mentioned secondary signal by above-mentioned first signal through obtaining after the anti-phase computing.
Above-mentioned output terminal selecting arrangement is the decoding addressing circuit of doing according to the address of above-mentioned output terminal.
Utilize device of the present invention, when the 1st 64K of dynamic RAM lost efficacy, basic input/output can skip over, and skips to the memory paragraph of other address, to proceed test.So, use system of the present invention, do not have again situation about can't start shooting to take place because of the 1st 64K inefficacy.
Fig. 1 represents the part pin signal of its dimm socket of dynamic RAM.
Fig. 2 represents the circuit diagram of one embodiment of the invention.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with the accompanying drawings, describe the present invention in detail by a preferred embodiment.
Embodiment:
Fig. 1 represents the part pin signal of dimm socket.The access of memory paragraph mainly by after address wire (address line) the signal addressing, reads or writes data, MD again from specified storage unit
0～MD
63Be data line.For multiplex's addressing of dynamic RAM, mainly be to utilize 12 address wires (BOMA0～BOMA11), as shown in Figure 1, cooperate rwo address strobe signals (Row Address Strobe signal; RAS) and column address gating signal (Column Address Strobe signal; CAS) (RAS and CAS are all not shown) decodes various possible memory paragraph addresses, so that the action of reading or writing.(BOMA0～BOMA11) is the part of memory paragraph address signal in the system address bus to above-mentioned address wire.
Fundamental purpose of the present invention, be to work as basic input/output in starting up's test, first 64K memory paragraph of finding dynamic RAM memory bank (Bank) lost efficacy and can't start-up system the time, just automatically switch to the memory paragraph of other addresses, to reach the purpose of start-up system.The present invention is provided with one to switch selecting arrangement on the path of dynamic RAM address signal line BOMA8～BOMA10, export new address signal BOMA8S～BOMA10S again to dynamic RAM; And when basic input/output finds that first 64K of memory paragraph lost efficacy, cooperate the operation of control program, address signal line BOMA8～BOMA10 can be changed (for example anti-phase computing) by above-mentioned switching selector, and obtain new address signal BOMA8S～BOMA10S, so basic input/output is promptly skipped the 64K memory paragraph of inefficacy, and proceeds start-up routine with the memory paragraph of other addresses.
Embodiment circuit diagram hereinafter with reference to Fig. 2 describes action of the present invention in detail.
As shown in Figure 2, automatic switching control device for dynamic random access memory of the present invention, it comprises at least: an output terminal selecting arrangement 22, in order to select the specific output terminal of gating one; One switches selecting arrangement 24, its input end couples one group of first address signal line (BOMA8～BOMA10), and the output of the above-mentioned output terminal of foundation, and decision allow above-mentioned first address signal or with second address signal of the above-mentioned first address signal complementation, export above-mentioned dynamic RAM to.
When above-mentioned basic input/output found that first 64K memory paragraph of above-mentioned dynamic RAM memory bank lost efficacy (Data Error), basic input/output can be carried out down the routine formula:
JNC α ；NC=memory?OK
MOV AL 0 ；AL=LO
OUT 22H，AL ；D
0CT=L
0
JMP Test?Again
α Normal?INIT?；memory?OK，go?next
So when finding that first 64K memory paragraph lost efficacy, above-mentioned basic input/output writes earlier a particular value L in register AL
0(being 0 in this embodiment).Determine with L0 to be that the output terminal of 22H is sent from the address again.Above-mentioned output terminal address can be from the optional one of the output terminal corresponding with 22H～2FH.
Because the address of output terminal is 22H, thus the output terminal selecting arrangement 22 in the present embodiment (in this embodiment, mainly being the circuit that constitutes by IC-244), the output terminal of being scheduled in the main matching program and the decoding circuit done; In order to this I/O address 22H that decodes,, and LO can be sent by the output terminal of address 22H so that export a gating signal.The address is that 22H represents system address line A
15～A
8Be 0, and A
7～A
4Be 0010, A
3～A
0Be 0010, AEN (address wire gating signal) and IOW (I/O writes gating signal) are 1 in addition.So the signal E that output terminal selecting arrangement 22 will output logic " 0 " makes L so that make output buffer (for example being IC-374) 26 gatings export 0
0CT becomes 0.
L
0The CT signal is a logical zero, so will make the gating input end (1G, 2G) of IC-244 receive logical zero and " 1 " respectively, so the signal on BOMA8～BOMA10 signal wire (input end 2D) will be sent by output terminal 2Q, after the anti-phase computing of phase inverter, export dynamic RAM again to.So if the part address BOMA10～BOMA8 of inefficacy memory paragraph is 000 (first address signal), then after the above-mentioned processing of process, it is 111 (second address signals) that its part address BOMA10～BOMA8 can be changed.Therefore, for basic input/output, the memory paragraph of its test crash (for example the start address of BOMA11～BOMA0 is x000xxxxxxxx) will be skipped over, and change memory paragraph (start address is x111xxxxxxxx) to test new assigned address, so just can proceed start and testing to finish start-up routine.
The foregoing description was changed the BOMA8 among BOMA0～BOMA11～BOMA10 address signal, but was not limited to this after the 1st 64K memory paragraph of discovery loses efficacy, also the needs of visual practical application change the address signal that changes other into.
In addition, present embodiment obtains second address signal with the anti-phase computing of first address signal, but is not to be defined in this, can be according to the actual needs, first address signal is carried out the computing of other modes, and obtain being different from second address signal of first address signal.
When basic input/output did not find that memory paragraph lost efficacy, program promptly skipped to the α step, and the expression memory is normal, can proceed other test.In addition, when memory paragraph lost efficacy, L
0CT can not become logical zero, so above-mentioned switching selector 22 keeps allowing first address signal of above-mentioned BOMA8～BOMA10 export dynamic RAM to by first output terminal (1Q).
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any personage who is familiar with this technology; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim person of defining.
Claims (5)
1. automatic switching control device for dynamic random access memory, when basic input/output test finds that first 64K memory paragraph of dynamic RAM memory bank (Bank) lost efficacy and can't start-up system the time, just automatically switch to the memory paragraph of other address, it is characterized in that comprising at least:
One output terminal selecting arrangement is in order to select the specific output terminal of gating one;
One switches selecting arrangement, its input end couples one group of first address signal, and according to the output of above-mentioned output terminal, and, export above-mentioned dynamic RAM to above-mentioned first address signal or second address signal that obtains through a certain operations by above-mentioned first address signal;
Wherein, when above-mentioned basic input/output finds that first 64K memory paragraph of above-mentioned dynamic RAM memory bank lost efficacy, above-mentioned basic input/output will write a particular value in register, the above-mentioned above-mentioned output terminal of output terminal selecting arrangement gating and export above-mentioned particular value, make above-mentioned switching selector export above-mentioned second address signal, basic input/output is proceeded test afterwards; When basic input/output did not find that memory paragraph lost efficacy, above-mentioned switching selector kept above-mentioned first address signal of output.
2. device as claimed in claim 1 is characterized in that above-mentioned first address signal is the part of memory paragraph address signal in system's address bus, and other memory paragraph address signal then is coupled to above-mentioned dynamic RAM respectively in the address bus.
3. device as claimed in claim 1, it is characterized in that, its input end coupling system address bus of above-mentioned output terminal selecting arrangement, after above-mentioned basic input/output writes register with above-mentioned particular value, the address signal of above-mentioned output terminal selecting arrangement decoding said system address bus and the above-mentioned output terminal of gating.
4. device as claimed in claim 1 is characterized in that, above-mentioned secondary signal by above-mentioned first signal through obtaining after the anti-phase computing.
5. device as claimed in claim 1 is characterized in that, above-mentioned output terminal selecting arrangement is the decoding addressing circuit of doing according to the address of above-mentioned output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99111125A CN1117324C (en) | 1999-07-26 | 1999-07-26 | Automatic switching control device for dynamic random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN99111125A CN1117324C (en) | 1999-07-26 | 1999-07-26 | Automatic switching control device for dynamic random access memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1282026A true CN1282026A (en) | 2001-01-31 |
| CN1117324C CN1117324C (en) | 2003-08-06 |
Family
ID=5274895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN99111125A Expired - Fee Related CN1117324C (en) | 1999-07-26 | 1999-07-26 | Automatic switching control device for dynamic random access memory |
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| Country | Link |
|---|---|
| CN (1) | CN1117324C (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100395723C (en) * | 2003-07-17 | 2008-06-18 | 鸿富锦精密工业（深圳）有限公司 | Single memory automatic staring back-up system and method |
| CN115757196A (en) * | 2022-11-09 | 2023-03-07 | 超聚变数字技术有限公司 | Memory, memory access method and computing equipment |
-
1999
- 1999-07-26 CN CN99111125A patent/CN1117324C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100395723C (en) * | 2003-07-17 | 2008-06-18 | 鸿富锦精密工业（深圳）有限公司 | Single memory automatic staring back-up system and method |
| CN115757196A (en) * | 2022-11-09 | 2023-03-07 | 超聚变数字技术有限公司 | Memory, memory access method and computing equipment |
| CN115757196B (en) * | 2022-11-09 | 2023-09-01 | 超聚变数字技术有限公司 | Memory, memory access method and computing device |
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| Publication number | Publication date |
|---|---|
| CN1117324C (en) | 2003-08-06 |
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Granted publication date: 20030806 Termination date: 20110726 |