CN1279613C - Metal internal ligature structure - Google Patents
Metal internal ligature structure Download PDFInfo
- Publication number
- CN1279613C CN1279613C CN 02130358 CN02130358A CN1279613C CN 1279613 C CN1279613 C CN 1279613C CN 02130358 CN02130358 CN 02130358 CN 02130358 A CN02130358 A CN 02130358A CN 1279613 C CN1279613 C CN 1279613C
- Authority
- CN
- China
- Prior art keywords
- metal
- copper
- upper strata
- interconnecting structure
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The present invention relates to a metal internal connecting wire structure which comprises an upper-layer metal conducting wire, a lower-layer metal conducting wire, a dielectric layer, a plurality of metal conducting hole plugs and a plurality of first dielectric layer columns, wherein the lower-layer metal conducting wire forms an overlapping region with the upper-layer metal conducting wire; the dielectric layer is arranged between the upper-layer metal conducting wire and the lower-layer metal conducting wire; the metal conducting hole plugs are arranged in the dielectric layer of a first region in the overlapping region for electrically connecting the upper-layer metal conducting wire and the lower-layer metal conducting wire; the first dielectric layer columns are embedded in the upper-layer metal conducting wire of a second region in the overlapping region; the first region and the second region are not mutually overlapped. The present invention causes the metal conducting hole plugs to be regularly connected with the upper-layer and the lower-layer of copper conducting wires by the mode of an array layout of metal conducting holes, works out sufficient quantities of the metal conducting hole plugs by considering an EM rule for bearing current of the wires, can not only improve a copper CMP plate effect but also reduce the density of the copper conducting wires to cause the conducting wires to hardly generate the phenomenon of leakage current, and greatly increases process margins.
Description
Technical field
The present invention relates to technical field of semiconductors, especially a kind of metal interconnecting structure, the copper dual-damascene internal connection-wire structure of importing interlayer post in having the zone of a large amount of metal vias.
Background technology
Because the low-resistivity of copper cooperates dual damascene technology (hereinafter referred to as copper wiring) to become the main flow framework of metal current intraconnections processing procedure with the copper metal as conductor material.Yet known copper wiring is in the plain conductor zone of broad, the power line of peripheral circuit (power line) for example, saucer phenomenon that cmp produces usually can take place or between the higher area discover lead of copper conductor density copper residual.The latter tends to cause leakage current, and reduces the reliability of product.For addressing these problems, the known practice is to settle many interlayer posts in plain conductor, that is the non-copper in the copper plain conductor partly.
See also Fig. 1 and Fig. 2, Fig. 1 shows partly top view of known copper metal interconnecting, and Fig. 2 is the generalized section of Fig. 1 along tangent line A-A '.As shown in Figures 1 and 2, lower metal lead 10 all is about 5 microns (μ m) with the live width of upper strata plain conductor 12, and overlaps to form the overlapping region 50 of one 5 μ m * 5 μ m up and down.Overlapping region 50 can be described as the metal vias district again.Among lower metal lead 10 and upper strata plain conductor 12, be formed with a plurality of interlayer post 10a and 12a respectively.Then arrange full metal vias connector 20 in the dielectric layer 30 between lower metal lead 10 and upper strata plain conductor 12 in the overlapping region 50.For avoiding lower metal lead 10 and upper strata plain conductor 12 to open circuit, the known practice is to forbid the importing of interlayer post pattern in metal vias district 50.Yet this measure but causes the saucer effect of plain conductor easily, as the 40 indication places of label among Fig. 2.
See also Fig. 3, Fig. 3 shows partly top view of known copper metal interconnecting, comprises two upper strata plain conductors 120 and 122, and two lower metal leads 100 and 102.As shown in Figure 3, upper strata plain conductor 120 forms a metal vias district 51 with lower metal lead 100, upper strata plain conductor 120 forms a metal vias district 52 with lower metal lead 102, upper strata plain conductor 122 forms a metal vias district 53 with lower metal lead 100, and upper strata plain conductor 122 forms a metal vias district 54 with lower metal lead 102.Distance between the upper strata plain conductor 120 and 122 is about 0.26 micron.Because there is not any interlayer post in known metal interconnecting structure in metal vias district 51,52,53 and 54, therefore easily at zone 71 and 72 places (shown in oblique line) between upper strata plain conductor 120 and 122, the residual copper metal that has not by CMP removed.
Summary of the invention
In view of the above, main purpose of the present invention is to provide a kind of copper dual-damascene internal connection-wire structure of improvement, to address the above problem.
For reaching above-mentioned purpose, the invention provides a kind of metal interconnecting structure, include a upper strata plain conductor; One lower floor's plain conductor forms an overlapping region with this upper strata plain conductor; One dielectric layer is located between this upper strata plain conductor and this lower metal lead; A plurality of metal vias connectors are located in this dielectric layer of a first area in this overlapping region, in order to be electrically connected this upper strata plain conductor and this lower metal lead; And a plurality of first interlayer posts, be embedded in this upper strata plain conductor of a second area in this overlapping region, wherein this first area and this second area non-overlapping copies.
According to the present invention, these a plurality of first interlayer posts be used for reducing when a cmp (chemical-mechanical polishing, when CMP) processing procedure imposes on this upper strata plain conductor in this overlapping region, the saucer effect that is produced.This first metal vias connector block is one m * n array block.
The present invention makes the metal vias connector connect two-layer copper conductor up and down regularly, and considers the EM rule with the layout type of metal vias array (for example 3 * 3 or 4 * 4 arrays), calculates the electric current of enough metal vias connector quantity with the carrying lead.Thus, can improve copper CMP saucer effect, also can reduce copper conductor density, make to be difficult between the lead producing leakage phenomenon, significantly improve processing procedure allowance (process margin).
Description of drawings
Fig. 1 shows partly top view of known copper metal interconnecting;
Fig. 2 is the generalized section of Fig. 1 along tangent line A-A ';
Fig. 3 shows partly top view of known copper metal interconnecting;
Fig. 4 shows partly top view of copper metal interconnecting of the present invention;
Fig. 5 is the generalized section of Fig. 4 along tangent line B-B ';
Fig. 6 shows that respectively metal vias density is to the mapping to the metal vias array pitch of metal vias array pitch and interlayer column density;
Fig. 7 shows partly top view of copper metal interconnecting of the present invention.
Illustrated symbol description
10 lower metal lead 10a interlayer posts
12 upper strata plain conductor 12a interlayer posts
20 metal vias connectors, 30 dielectric layers
40 saucer phenomenons, 50 metal vias districts
51,71,72 zones, 52,53,54 metal vias districts
100,102 lower metal leads, 120,122 upper strata plain conductors
210 lower metal lead 210a, b interlayer post
212 upper strata plain conductor 212a, b interlayer post
200 metal vias connectors, 300 dielectric layers
250 metal vias district 350m * n metal vias array block
251,271,272 zones, 252,253,254 metal vias districts
600,602 lower metal leads, 220,222 upper strata plain conductors
Embodiment
See also Fig. 4 and Fig. 5, Fig. 4 shows partly top view of copper metal interconnecting of the present invention, and Fig. 5 is the generalized section of Fig. 4 along tangent line B-B '.In preferred embodiment of the present invention, lower metal lead 210 utilizes the copper dual-damascene processing procedure to form with upper strata plain conductor 212, lower metal lead 210 all is about 5 microns (μ m) with the live width of upper strata plain conductor 212, and overlaps to form the metal vias district 250 of one 5 μ m * 5 μ m up and down.Yet the present invention is not limited only to above-mentioned live width, and the metal interconnecting of other live width and metal vias zone may cause the situation of residue problem between CMP saucer effect or plain conductor, all should be within application category of the present invention.As Fig. 4 and shown in Figure 5, among lower metal lead 210 and upper strata plain conductor 212, be formed with a plurality of interlayer post 210a and 212a respectively.In metal vias district 250, include a plurality of m * n metal vias array block 350, and a plurality of interlayer post 212b is distributed among the upper strata plain conductor 212 between the adjacent two metal vias array block 350.Each m * n metal vias array block 350 is made of m * n metal vias connector 200.Generally speaking, m is between 2 to 8, and n is between 2 to 8, and foundation preferred embodiment of the present invention, wherein m=n=4.
Be noted that the layout patterns of interlayer post 212b and metal vias array block 350 patterns are answered non-overlapping.In Fig. 5, a plurality of interlayer post 210b are distributed among the lower metal lead 210 between the adjacent two metal vias array block 350.Similarly, the layout of interlayer post 210b and metal vias array block 350 pattern non-overlappings.Because interlayer post 210b and interlayer post 212b form in different steps, so it may be overlapping up and down, also may be not overlapping.
See also Fig. 6, Fig. 6 shows that respectively metal vias density is to the mapping to the metal vias array pitch of metal vias array pitch and interlayer column density.As shown in Figure 6, metal vias connector 200 numbers in the metal vias district 250 are according to known electromigration rule (the electro-migration rule of the sector person, abbreviate the EM rule as), calculate and to carry required minimum metal guide hole connector 200 quantity of current in wire, be multiplied by a safe number gained again.Among Fig. 6, minimum metal guide hole connector 200 quantity and maximum metal guide hole connector 200 quantity are represented by dotted lines.If with the metal vias array block that adopts one 4 * 4 arrays is example, advise that distance is about 1.2 microns between adjacent two metal vias array block, the metal vias density of this moment is about 2～3 μ m-2, and the interlayer column density is about 4%～6%.
As shown in Figure 7, Fig. 7 shows partly top view of copper metal interconnecting of the present invention, comprises two upper strata plain conductors 220 and 222, and two lower metal leads 600 and 602.As shown in Figure 7, upper strata plain conductor 220 forms a metal vias district 251 with lower metal lead 600, upper strata plain conductor 220 forms a metal vias district 252 with lower metal lead 602, upper strata plain conductor 222 forms a metal vias district 253 with lower metal lead 600, and upper strata plain conductor 222 forms a metal vias district 254 with lower metal lead 602.Distance between the upper strata plain conductor 220 and 222 is about 0.26 micron.Because metal interconnecting structure of the present invention is settled a plurality of interlayer posts in metal vias district 251,252,253 and 254, therefore be difficult at zone 271 and 272 places (shown in oblique line) the residual copper metal that has not by CMP removed between upper strata plain conductor 220 and 222.
In brief, the present invention makes the metal vias connector connect two-layer copper conductor up and down regularly, and considers the EM rule with the layout type of metal vias array (for example 3 * 3 or 4 * 4 arrays), calculates the electric current of enough metal vias connector quantity with the carrying lead.Thus, can improve copper CMP saucer effect, also can reduce copper conductor density, make to be difficult between the lead producing leakage phenomenon, significantly improve processing procedure allowance (process margin).
The above only is preferred embodiment of the present invention, and all equalizations of being done according to the present patent application claim change and modify, and all should belong to the covering scope of patent of the present invention.
Claims (19)
1. metal interconnecting structure is characterized in that: include:
One lower floor's plain conductor;
One upper strata plain conductor forms an overlapping region with this lower metal lead;
One dielectric layer is located between this upper strata plain conductor and this lower metal lead;
A plurality of metal vias connectors are located in this dielectric layer of a first area in this overlapping region, in order to be electrically connected this upper strata plain conductor and this lower metal lead; And
A plurality of first interlayer posts are embedded in this upper strata plain conductor of a second area in this overlapping region, wherein this first area and this second area non-overlapping copies.
2. metal interconnecting structure as claimed in claim 1 is characterized in that: this metal interconnecting structure includes a plurality of second interlayer posts in addition, is embedded in this lower metal lead in this second area.
3. metal interconnecting structure as claimed in claim 1 is characterized in that: these a plurality of first interlayer posts are used for reducing when a cmp processing procedure imposes on this upper strata plain conductor in this overlapping region, the saucer effect that is produced.
4. metal interconnecting structure as claimed in claim 1 is characterized in that: this upper strata plain conductor is made of the copper metal.
5. metal interconnecting structure as claimed in claim 1 is characterized in that: this lower metal lead is made of the copper metal.
6. metal interconnecting structure as claimed in claim 1 is characterized in that: these a plurality of metal vias connectors are aligned at least one first metal vias connector block and one second metal vias connector block.
7. metal interconnecting structure as claimed in claim 6 is characterized in that: this first metal vias connector block is one m * n array block.
8. metal interconnecting structure as claimed in claim 7 is characterized in that: m=n.
9. metal interconnecting structure as claimed in claim 6 is characterized in that: have a minimum range between this first metal vias connector block and the second metal vias connector block.
10. metal interconnecting structure as claimed in claim 9 is characterized in that: this minimum range is 1.2 microns.
11. the copper metal interconnecting structure that can eliminate cmp saucer effect includes:
One upper strata damascene copper lead;
One lower floor's damascene copper lead forms an overlapping region with this upper strata damascene copper lead;
One dielectric layer is located between this upper strata damascene copper lead and this lower floor's damascene copper lead;
A plurality of m * n metal vias connector array block are located in this dielectric layer of this overlapping region, in order to be electrically connected this upper strata damascene copper lead and this lower floor's damascene copper lead;
A plurality of first interlayer posts are embedded in this overlapping region in this upper strata damascene copper lead between adjacent two these m * n metal vias connector array block; And
A plurality of second interlayer posts are embedded in this overlapping region in this lower floor's damascene copper lead between adjacent two these m * n metal vias connector array block.
12. copper metal interconnecting structure as claimed in claim 11 is characterized in that: these a plurality of first interlayer posts are used for reducing when a cmp processing procedure imposes on this upper strata damascene copper lead in this overlapping region, the saucer effect that is produced.
13. copper metal interconnecting structure as claimed in claim 11 is characterized in that: m=n.
14. copper metal interconnecting structure as claimed in claim 11 is characterized in that: m is between 2 to 8.
15. copper metal interconnecting structure as claimed in claim 11 is characterized in that: n is between 2 to 8.
16. copper metal interconnecting structure as claimed in claim 11 is characterized in that: have a minimum range between adjacent two these m * n metal vias connector array block.
17. copper metal interconnecting structure as claimed in claim 16 is characterized in that: this minimum range is 1.2 microns.
18. copper metal interconnecting structure as claimed in claim 11 is characterized in that: this copper metal interconnecting structure includes the side that a copper conductor is located at this upper strata damascene copper lead in addition, and has a distance with this upper strata damascene copper lead.
19. copper metal interconnecting structure as claimed in claim 18 is characterized in that: this distance is greater than 0.26 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02130358 CN1279613C (en) | 2002-08-16 | 2002-08-16 | Metal internal ligature structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02130358 CN1279613C (en) | 2002-08-16 | 2002-08-16 | Metal internal ligature structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1476088A CN1476088A (en) | 2004-02-18 |
| CN1279613C true CN1279613C (en) | 2006-10-11 |
Family
ID=34144453
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02130358 Expired - Lifetime CN1279613C (en) | 2002-08-16 | 2002-08-16 | Metal internal ligature structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1279613C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101539954B (en) * | 2008-03-21 | 2011-01-19 | 奇景光电股份有限公司 | Method for inspecting layout design of integrated circuit |
| CN114613319B (en) * | 2022-03-23 | 2023-11-28 | 深圳市华星光电半导体显示技术有限公司 | Pixel structure of MLED backplate and display panel |
-
2002
- 2002-08-16 CN CN 02130358 patent/CN1279613C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1476088A (en) | 2004-02-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1214462C (en) | Vertical electrical interconnestions in stack | |
| CN1131555C (en) | Contactless chip card | |
| KR100275099B1 (en) | Low resistance contacts between metal layers of integrated circuits and methods of forming them | |
| CN1286173C (en) | Circuit structure for connecting weld-pad and electrostatic protective circuit | |
| CN1639865A (en) | Semiconductor device having a wire bond pad and method therefor | |
| CN1898795A (en) | An integrated circuit package substrate having a thin film capacitor structure | |
| JP2760945B2 (en) | Thin film multilayer wiring structure | |
| CN1295748C (en) | Metal-insulator-metal capacitor in copper | |
| CN1305224A (en) | Weld interface with mechanical strengthened and its method | |
| US7518243B2 (en) | Semiconductor device with multilayer interconnection structure | |
| CN2731711Y (en) | Copper metal inlaid structure | |
| CN1061785C (en) | Multi-layer interlined structure for integrated circuit and mfg. method thereof | |
| CN1279613C (en) | Metal internal ligature structure | |
| CN2854807Y (en) | Integral circuit device | |
| CN1645606A (en) | Active area bonding compatible high current structures | |
| CN1666336A (en) | Semiconductor structure integrated under a pad | |
| JPH1065101A (en) | Semiconductor device | |
| CN1055788C (en) | Method for making internal connecting wires within semiconductor device | |
| CN1264393C (en) | Selective electroplating method | |
| CN100352052C (en) | Internal on-line structure using diagonal layout | |
| TW548793B (en) | Metal interconnect structure | |
| CN1856877B (en) | Conductor track connection structure and associated production method | |
| CN1334604A (en) | Twice fuse density in TV window | |
| CN1499625A (en) | Soldering pad with dual copper inlaid interconnection wire and preparation method | |
| CN2733596Y (en) | Semiconductor structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20061011 |
|
| CX01 | Expiry of patent term |