CN1268085C - Shaking attenuation processor in SDH branch clock restoration - Google Patents
Shaking attenuation processor in SDH branch clock restoration Download PDFInfo
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- CN1268085C CN1268085C CN 200410053999 CN200410053999A CN1268085C CN 1268085 C CN1268085 C CN 1268085C CN 200410053999 CN200410053999 CN 200410053999 CN 200410053999 A CN200410053999 A CN 200410053999A CN 1268085 C CN1268085 C CN 1268085C
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Abstract
The present invention relates to a shaking attenuation processor in SDH branch clock restoration, which comprises an elastic buffer memory reading/writing control circuit, a step computing circuit and a digital frequency synthesizer, wherein the elastic buffer memory reading/writing control circuit comprises a first in first out elastic buffer, a reading address generator, a writing address generator and a phase difference sample circuit; the step computing circuit comprises a bit leakage rate selector, a justification step selector and an adder; the digital frequency synthesizer comprises an adder and a register. Because the present invention uses a full digital method to realize branch clock restoration shaking attenuation processing, clock restoration shaking is reduced to an allowable range, and thus, a phase-locked loop is used to further make shaking attenuation, and branch clocks which satisfy ITU-T standard are restored.
Description
Technical field
The present invention relates to digital communicating field, refer to it is Synchronous Digital Hierarchy (Synchronous DigitalHierarchy, Jitter Attenuation processing unit during SDH) middle branch clock recovers particularly.
Background technology
In SDH, the introducing of pointer notion can realize the location to payload very easily, but the pointer adjustment can bring very big phase jitter, and a pointer adjustment can bring the shake of 8 or 24 bits, makes troubles for like this clock recovery of receiver side.
If (Phase Locked Loop PLL) carries out clock recovery, is difficult to recover a clock that satisfies the ITU-T standard directly to use phase-locked loop at the receiver side clock.So, generally before phase-locked loop, need to carry out earlier the processing of Jitter Attenuation.
In addition, the Another reason for generation shake in the tributary signal in SDH is justification, and a justification meeting brings the shake of 1 bit.
Fig. 1 recovers a kind of common method that Jitter Attenuation is handled for branch clock, and it is a kind of implementation method based on statistical circuit.
At first, calculate the number of clock deduction then according to the number of times of statistics, produce recovered clock by clock deduction circuit at last the adding up of pointer adjustment and justification number of times.
Owing to adopt the foundation of statistical circuit in realizing, so statistical circuit is very big to the jitter performance influence of recovered clock as clock generating.Timing statistics is too short, and the output clock jitter will be very big, is difficult to satisfy the ITU-T standard; Timing statistics is long, brings the complexity and the long problem of frequency-tracking time of realization.
Summary of the invention
The object of the present invention is to provide the Jitter Attenuation processing unit during branch clock recovers among the SDH, by this device the shake of recovered clock is reduced to allowed band, make further Jitter Attenuation by phase-locked loop like this, thereby recover the branch clock that satisfies the ITU-T standard.
Jitter Attenuation processing unit during branch clock recovers in a kind of Synchronous Digital Hierarchy provided by the present invention, it is characterized in that: the read/write control circuit that comprises elastic caching, step size computation circuit and digital frequency synthesizer, wherein: the read/write control circuit of elastic caching, the elastic caching device that comprises first in first out, read address generator, write address generator and phase difference sample circuit, in reading address generator, produce and read the address by reading clock, write clock and in the write address generator, produce write address, output to the elastic caching device and finish read-write operation, read the address simultaneously, write address outputs to the phase difference sample circuit, the phase difference sample circuit is multiframe boundaries the reading of current input of sampling, write address calculates and reads, write of the input of the phase place of clock as the leak rate selector; The step size computation circuit, comprise bit leaking rate selector, justification step-length selector and first adder, this bit leaking rate selector is selected current bit leaking rate according to the input phase difference of phase difference sample circuit, this justification step-length selector is selected the justification step-length according to the positive negative justification indication of input, bit leaking rate and the addition of justification step-length in first adder output to digital frequency synthesizer, as the frequency synthesizer step size increments; Digital frequency synthesizer, it is an accumulator, comprise second adder, the 3rd adder and register, the 3rd adder is used to finish the calculating of frequency synthesizer step-length, that is: the output of first adder is the initial value that the frequency synthesizer step size increments adds the step-length of frequency synthesizer, be the branch clock nominal frequency, and each reference clock that will import by register just along the frequency synthesizer step-length is added up in second adder, accumulation result overflows naturally, and the highest order of accumulator is recovered clock.
Jitter Attenuation processing unit during branch clock recovers among the above-mentioned SDH, wherein, the elastic caching of elastic caching device is in half-full.
Jitter Attenuation processing unit during branch clock recovers among the above-mentioned SDH, wherein, the value of frequency synthesizer step-length initial value is to determine according to applied accumulator figure place, branch clock nominal frequency and reference clock frequency.
Jitter Attenuation processing unit during branch clock recovers among the above-mentioned SDH, wherein, the selection of bit leaking rate is the phase difference according to the reading and writing clock, i.e. the frequency of pointer adjustment is come adaptive selection.
Jitter Attenuation processing unit during branch clock recovers among the above-mentioned SDH, wherein, it is directly according to the justification type selecting that the justification step-length is selected.
Because the present invention adopts digital method to realize that branch clock recovers Jitter Attenuation and handles, and the shake of recovered clock is reduced to allowed band, makes further Jitter Attenuation by phase-locked loop like this, recovers the branch clock that satisfies the ITU-T standard.
Description of drawings
Fig. 1 is the flow chart that branch clock recovers a kind of common method of Jitter Attenuation processing;
Fig. 2 is the functional block diagram of the Jitter Attenuation processing unit during branch clock recovers among the SDH of the present invention.
Embodiment
The present invention is that example illustrates to recover 2M tributary signal clock, but realizes that principle is equally applicable to recover the branch clock of other type.
Reference clock of the present invention is the SDH clock of 77.76M.
According to Fig. 2, implementation structure of the present invention comprises read/write control circuit 1, step size computation circuit 2 and the digital frequency synthesizer 3 of elastic caching.
The read/write control circuit 1 of elastic caching comprises that elastic caching device (FIFO) 101,7 bits of the first in first out of 128 bits read address generator 103,7 bit write address generator 102 and phase difference sample circuits 104.
Step size computation circuit 2 comprises bit leaking rate selector 201, justification step-length selector 202 and adder 203.
The read/write control circuit 1 of elastic caching is read address (Radr) and write address (Wadr) by what read clock, write that clock produces 7 bits in reading address generator 103 and write address generator 102 respectively, output to elastic caching device 101 and finish read-write operation, read the address simultaneously, write address outputs to phase difference sample circuit 104, phase difference sample circuit 104 calculates the input of the phase place of reading and writing clock as leak rate selector 201 at the reading, writing address of the current input of multiframe boundaries (500us) sampling.
Because it is half-full that the elastic caching ideal value of elastic caching device 101 is in, and promptly differs 64 bits, so the reading and writing clock skew is,
Po＝Wadr-Radr-64
The bit leaking rate selector 201 of step size computation circuit 2 is tabled look-up according to the input phase difference of phase difference sample circuit 104 and is selected current bit leaking rate (Br), justification step-length selector 202 is selected justification step-length (Cstep) according to the positive negative justification indication of input, bit leaking rate and the addition of justification step-length in adder 203 output to digital frequency synthesizer 3, as frequency synthesizer step size increments (Deltastep).
Step0＝2^24*2.048/77.76≈441869
Accumulator adds up to frequency synthesizer step-length (Step) on the just edge of each reference clock (77.76M), and accumulation result overflows naturally.The highest order of accumulator is recovered clock.
The bit leaking rate is selected the speed according to the pointer adjustment, and promptly the reading and writing clock skew is selected current leak rate, referring to table 1
| The phase difference (Po) of read-write clock | Leak rate (Br) |
| Po＝0 | 0 |
| 0＜Po＜＝16 | 1 |
| 16＜Po＜＝32 | 2 |
| 32＜Po＜＝48 | 3 |
| 48＜Po＜＝63 | 380 |
| -16＜＝Po＜0 | -1 |
| -32＜＝Po＜-16 | -2 |
| -48＜＝Po＜-32 | -3 |
| -64＜＝Po＜-48 | -380 |
The justification step-length is selected referring to table 2
| Justification | Sign indicating number speed adapts to step-length (Cstep) |
| Positive justification | 432 |
| Negative justification | -430 |
| | 0 |
In the present embodiment, it is according to the differing of reading and writing clock that the bit leaking rate is selected, and promptly the frequency adjusted of pointer is come adaptive selection, adjusts number of times after a little while when pointer, selects less leak rate; When pointer is adjusted often, select bigger leak rate.Like this, guarantee under the situation of error code not that the recovered clock shake is minimum.The step-length of frequency-tracking is directly selected in justification according to the justification indication, guarantee that frequency-tracking speed is quicker.
Test result of the present invention is as follows:
The Mapping jitter test result is referring to table 3
| Bit rate error tolerance scope (1*10 -6) | Mapping jitter | |
| +/-50 | ITU-T G.783 | Test result |
| 0.075UI | ＜0.02UI | |
In conjunction with the jitter test result referring to table 4
| The test sequence of pointers | Low pass (LP) 20HZ-100K | High pass (HP) 18K-100K | ||
| IUT-T G.783 | Test result | ITU-T G.783 | Test result | |
| A | 0.4UI | 0.10UI | 0.075UI | ＜10e-4UI |
| B | 0.10UI | ＜10e-4UI | ||
| C | 0.10UI | ＜10e-4UI | ||
| D | 0.10UI | ＜10e-4UI | ||
By table 3, table 4 as can be known, output jitter of the present invention is much smaller than the ITU-T regulation of standard G.783.
The beneficial effect that technical solution of the present invention is brought
A) to adopt reference clock be 77.76M in the present invention, is the interface clock of SDH Plays, therefore, needn't increase other high-frequency clocks in the design and be used as reference clock, in the minimizing system to the requirement of extra clock.
B) for justification directly according to current justification indicators track clock frequency, therefore, fast to the tracking velocity of frequency.
C) mean value (every multi-frame sampling) of directly using the address of elastic caching has reduced the statistics of pointer adjustment number of times as the selection of slip.
D) adaptive adjustment slip is adopted in the pointer adjustment. The jitter performance that guarantees output clock is as much as possible little under different pointers are adjusted frequency, simultaneously so that the increase of the acquisition performance of system.
Claims (5)
1. the Jitter Attenuation processing unit during branch clock recovers in the Synchronous Digital Hierarchy is characterized in that: comprise read/write control circuit (1), step size computation circuit (2) and the digital frequency synthesizer (3) of elastic caching, wherein:
The read/write control circuit (1) of elastic caching, the elastic caching device (101) that comprises first in first out, read address generator (103), write address generator (102) and phase difference sample circuit (104), in reading address generator (103), produce and read the address by reading clock, write clock and in write address generator (102), produce write address, output to elastic caching device (101) and finish read-write operation, read the address simultaneously, write address outputs to phase difference sample circuit (104), phase difference sample circuit (104) is multiframe boundaries the reading of current input of sampling, write address calculates and reads, write of the input of the phase place of clock as bit leaking rate selector (201);
Step size computation circuit (2), comprise bit leaking rate selector (201), justification step-length selector (202) and first adder (203), this bit leaking rate selector (201) is selected current bit leaking rate according to the input phase difference of phase difference sample circuit (104), this justification step-length selector (202) is selected the justification step-length according to the positive negative justification indication of input, the addition in first adder (203) of bit leaking rate and justification step-length outputs to digital frequency synthesizer (3), as the frequency synthesizer step size increments;
Digital frequency synthesizer (3), it is an accumulator, comprise second adder (301), the 3rd adder (303) and register (302), the 3rd adder (303) is used to finish the calculating of frequency synthesizer step-length, that is: the output of first adder (203) is the initial value that the frequency synthesizer step size increments adds the step-length of frequency synthesizer, be the branch clock nominal frequency, and each reference clock that will import by register (302) just along the frequency synthesizer step-length is added up in second adder (301), accumulation result overflows naturally, and the highest order of accumulator is recovered clock.
2. the Jitter Attenuation processing unit during branch clock recovers in the Synchronous Digital Hierarchy according to claim 1, it is characterized in that: the elastic caching of described elastic caching device (101) is in half-full.
3. the Jitter Attenuation processing unit during branch clock recovers in the Synchronous Digital Hierarchy according to claim 1 is characterized in that: the value of described frequency synthesizer step-length initial value is to determine according to applied accumulator figure place, branch clock nominal frequency and reference clock frequency.
4. the Jitter Attenuation processing unit during branch clock recovers in the Synchronous Digital Hierarchy according to claim 1, it is characterized in that: the selection of described bit leaking rate is the phase difference according to the reading and writing clock, i.e. the frequency of pointer adjustment is come adaptive selection.
5. the Jitter Attenuation processing unit during branch clock recovers in the Synchronous Digital Hierarchy according to claim 1, it is characterized in that: the selection of described justification step-length is directly according to the justification type selecting.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200410053999 CN1268085C (en) | 2004-08-25 | 2004-08-25 | Shaking attenuation processor in SDH branch clock restoration |
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| CN 200410053999 CN1268085C (en) | 2004-08-25 | 2004-08-25 | Shaking attenuation processor in SDH branch clock restoration |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1855786B (en) * | 2005-04-19 | 2010-05-05 | 中兴通讯股份有限公司 | Branch signal recovering method and device based on noninteger leakage rate |
| CN1859052B (en) * | 2005-12-29 | 2011-06-15 | 华为技术有限公司 | Asynchronous clock domain signal processing method and system |
| CN1968063B (en) * | 2006-10-26 | 2010-10-27 | 华为技术有限公司 | Clock recovery method and apparatus |
| CN101136628B (en) * | 2007-03-27 | 2011-09-21 | 中兴通讯股份有限公司 | Digital circuit means for implementing data dithering removal |
| CN101964688B (en) * | 2009-07-21 | 2015-05-20 | 中兴通讯股份有限公司 | Method and system for recovering data clock |
| CN101741500B (en) * | 2009-12-21 | 2013-01-09 | 浙江大学 | Special multiconnection device of border network processor |
| CN102013934A (en) * | 2010-01-21 | 2011-04-13 | 柳州市达迪通信设备有限公司 | Clock generating and smoothing device |
| CN108988849B (en) * | 2018-06-22 | 2019-05-28 | 西安邮电大学 | E1 tributary signal output smoothing phaselocked loop and dividing method in SDH system |
| CN114499728A (en) * | 2020-11-11 | 2022-05-13 | 迈普通信技术股份有限公司 | Associated clock jitter suppression method and device for E1 link and electronic equipment |
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