CN1265604C - Two-phase FSK digital demodulator and its signal demodulation method - Google Patents

Two-phase FSK digital demodulator and its signal demodulation method Download PDF

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CN1265604C
CN1265604C CN 02156457 CN02156457A CN1265604C CN 1265604 C CN1265604 C CN 1265604C CN 02156457 CN02156457 CN 02156457 CN 02156457 A CN02156457 A CN 02156457A CN 1265604 C CN1265604 C CN 1265604C
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negative edge
positive edge
positive
critical value
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CN1509034A (en
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黄振升
张晋嘉
张耀光
许立正
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Zhicheng Electronic Ltd By Share Ltd
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Liyuan Communication Co ltd
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Abstract

The invention discloses a double-phase FSK digital demodulator and a signal demodulation method thereof, wherein the double-phase FSK digital demodulator respectively detects and captures a positive edge signal and a negative edge signal of an intermediate frequency signal by utilizing at least one detection circuit; then, two ripple counters are used for referencing a critical value, and positive and negative edge signals are received as starting signals to reset the critical value to the initial value of the ripple counter so as to start counting comparison, and further a positive edge data bit and a negative edge data bit are output; finally, the positive and negative edge data are located in a hard decision logic circuit for frequency-down decision to transmit a baseband signal. The double-phase FSK demodulator not only can reduce the number of logic gates and shorten the signal edge delay time, but also can increase the demodulation resolution, is a simple and practical double-phase FSK digital demodulator, and accords with the development trend of light, thin and short wireless products.

Description

Quarter-phase FSK digital demodulator and signal demodulating method thereof
Technical field
The present invention relates to a kind of modulating signal technology of digital radio communication receiving/transmission module, more particularly, relate to a kind of wireless intermediate frequency (IF) frequency shift keying (Frequency Shift Keying, FSK) quarter-phase in (Two Phase) FSK digital demodulator (demodulator) and signal demodulating method thereof of being applied in.
Background technology
Along with the popularizing of significantly development, the network of communication product in recent years, the rise of information household electrical appliances and application of radio communication, digital broadcasting and broadband network or the like, prove the arriving of " information age " amply, the transmission that is to say information will be rapider, also with diversification more.And in order to satisfy the increase of people to information requirement, wireless communication technique is also more and more paid attention to, and the demand of wireless product is also increased.
Radio frequency/intermediate frequency module in the radio communication product is formed with three unit of wireless transmission by wireless receiving, signal are synthetic, and wherein the radio receiving unit circuit etc. that is used to eliminate jamming incoherent signal, automatic gain adjustment by radio frequency head end, mixer, intermediate frequency amplifier and demodulator and other is formed.Basically, this radio frequency/intermediate frequency module be the signal that will receive after amplification, filtering and synthetic the processing, utilize demodulator that the intermediate-freuqncy signal demodulation is reduced into fundamental frequency signal originally, handle in order to follow-up fundamental frequency signal; Therefore, demodulator is being played the part of the role who can not be ignored in digital radio communication receiving/transmission module.
When tradition is utilized the underway frequency demodulated signal of the fsk demodulator of frequency modulation technology, be to utilize a mixer (Mixer) to carry out the frequency reducing first time earlier, the signal that is about to the intermediate-freuqncy signal frequency reducing and is high Q value makes the signal complex calculation formula designed through inside calculate afterwards again, this signal down could be demodulated to fundamental frequency signal after as calculated; Utilize this kind mode will cause the time and the shared gate number (logic gate counts) of increase of inhibit signal, in addition, the required chip area of this traditional RTL digital Design circuit that fsk demodulator adopted is bigger, and current drain is also higher relatively.
For this reason, creator among the present invention relies on it to be engaged in the experience and the practice of relevant industries for many years, and through concentrating on studies and developing, create quarter-phase FSK digital demodulator and signal demodulating method thereof among the present invention eventually, carry out demodulation and existing deficiency with the above-mentioned traditional F SK demodulator that utilizes of effective solution.
Summary of the invention
To transfer the main purpose of device and signal demodulating method thereof be not enough in order to solve the resolution (resolution) that existing demodulator separates timing frequently at the centering frequency tone of Chinese characters for quarter-phase FSK numeral among the present invention, and problem such as effect is remarkable inadequately when Low Medium Frequency.
Another order of quarter-phase FsK digital demodulator and signal demodulating method thereof is to solve existing demodulator and signal demodulating method meeting inhibit signal time, increases the gate number and has the problem that relative high current consumes among the present invention.
An order again of quarter-phase FSK digital demodulator and signal demodulating method thereof is bigger in order to solve the existing required chip area of demodulator among the present invention, thereby causes demodulator structure big, does not meet that wireless product is light, thin, the problem of short and small trend.
The another purpose of quarter-phase FSK digital demodulator and signal demodulating method thereof is not have the signal compensation function in order to solve existing digital demodulator among the present invention, thereby has the problem of big frequency error.
For achieving the above object, the quarter-phase FSK digital demodulator among the present invention includes:
At least onely be used for detecting respectively the positive edge signal of acquisition intermediate-freuqncy signal and the testing circuit of negative edge signal;
One first counter, this counter is after selecting relative critical value according to different band codes, receive positive edge signal as enabling signal and the initial value of this first counter is reset to critical value, and the spacing between the adjacent positive edge signal and this critical value begun counting relatively, if the positive edge sitgnal distancel relatively is during greater than this critical value, the positive edge data position of output is 0, if the spacing of this positive edge signal is during less than this critical value, the positive edge data position of output is 1, and then obtains a positive edge data position;
One second counter, this counter receives negative edge signal and as enabling signal the initial value of second counter is reset to critical value, and the spacing between the adjacent negative edge signal and this critical value begun counting relatively, if the negative edge sitgnal distancel relatively is during greater than this critical value, the negative edge data position of output is 0, if spacing that should negative edge signal is during less than this critical value, the negative edge data position of output is 1, and then obtains a negative edge data position; And
One hard decision logical circuit, this hard decision logical circuit are to carry out the frequency reducing judgement according to positive edge data position and negative edge data position, to send out a fundamental frequency signal.
In addition, when if the spacing of positive edge or negative edge signal is too big, can utilize a positive edge or negative edge data position compensating signal to the hard decision logical circuit, to carry out signal compensation, then need not sitgnal distancel counted fully and finish, can obtain main track or negative edge data position.
The signal demodulating method of quarter-phase FSK digital demodulator is to receive after the intermediate-freuqncy signal after amplification, filtering and synthetic the processing at quarter-phase FSK digital demodulator among the present invention, carries out demodulation step, and this signal demodulating method comprises the following steps:
Detect the positive edge signal and the negative edge signal of acquisition intermediate-freuqncy signal;
After the relative critical value of different band code selections, receive positive edge signal and this critical value is reset to initial value as enabling signal, and the spacing between the adjacent positive edge signal and this critical value begun counting relatively, after counting relatively, if positive edge sitgnal distancel is during greater than this critical value, the positive edge data position of output is 0, if the spacing of positive edge signal is during less than this critical value, the positive edge data position of output is 1, and then obtains a positive edge data position;
Receive and as enabling signal this critical value to be reset to initial value by negative edge signal, and the spacing between the adjacent negative edge signal and this critical value begun counting relatively, after counting relatively, if when bearing the edge sitgnal distancel greater than this critical value, the negative edge data position of output is 0, if the spacing of negative edge signal is during less than this critical value, the negative edge data position of output is 1, and then obtains a negative edge data position;
Carry out frequency reducing according to the negative edge data position of this positive edge data position and this and judge, to send out a fundamental frequency signal.
Not only can reduce the gate number behind quarter-phase fsk demodulator in utilizing the present invention and the demodulation method thereof and shorten signal and prolong the limit time, and can increase the demodulation resolution, be a simple and practical quarter-phase FSK digital demodulator in fact, meet light, thin, the short and small development trend of wireless product.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment among the present invention is described in further detail.
Fig. 1 is the structural representation of quarter-phase FSK digital demodulator among the present invention;
Fig. 2 is the waveform signal schematic diagram of quarter-phase FSK digital demodulator when detecting positive and negative edge signal among the present invention.
Embodiment
The present invention utilizes a pair of counter that one intermediate-freuqncy signal (IF) is carried out a quarter-phase (two phase) Signal Processing, positive edge signal and negative edge signal by quarter-phase carry out the demodulation of signal, and reach reduction gate number, shorten signal delay time and increase demodulation resolution (resolution).When particularly the demodulator among the present invention being applied in Low Medium Frequency (low IF), its effect will be more remarkable.
Quarter-phase FSK digital demodulator among the present invention and signal demodulating method thereof can be taken this figure the structure of whole quarter-phase FSK digital demodulator and the whole flow process of carrying out the signal demodulation thereof are described simultaneously with reference to shown in Figure 1.When radio receiving unit receives a radio frequency signal, after handling via the amplification of elements such as radio frequency head end, mixer, intermediate frequency amplifier, filtering and synthetic etc., will transmit in FSK intermediate-freuqncy signal to the quarter-phase FSK digital demodulator.
As shown in Figure 1, after a quarter-phase FSK digital demodulator 10 receives the FSK intermediate-freuqncy signal, utilize at least one testing circuit 12 in the cycle of each FSK intermediate-freuqncy signal, to detect earlier, capture positive edge and align the positive edge signal of edge (positive edge-to-positive edge) and negative edge negative edge signal negative edge (negative edge-to-negative edge), simultaneously as shown in Figure 2, after testing circuit 12 captures positive edge signal, be sent to after utilizing an inverter 14 with positive edge signal inversion earlier in the n bit ripple counter (n-bit ripple counter) 16 as enabling signal, and the initial value of a n bit ripple counter 16 is reset to critical value (threshold value) 22 (use two complement be negative); Simultaneously, testing circuit 12 is after capturing negative edge signal, also utilize an inverter 18 to give this negative edge signal anti-phase, be resent in one the 2nd n bit ripple counter 20 as enabling signal, and the initial value of the 2nd n bit ripple counter 20 is reset to critical value 22 (use two complement be negative).Wherein, this critical value 22 has different respective value according to different band code (channel code).
Before counting comparison, utilize system pulse to go respectively to calculate the distance between the adjacent positive edge signal earlier and obtain a positive edge sitgnal distancel, and calculate the distance between the adjacent negative edge signal simultaneously and obtain a negative edge sitgnal distancel.At this moment, the one n bit ripple counter 16 initial values are reset to after the critical value 22, cooperate positive edge sitgnal distancel to begin to count comparison, to export a positive edge data position (data bit), it is (the MostSignificant Bit of most significant digit unit of the n bit ripple counter of 1 or 0 binary data bit, MSB), if this positive edge sitgnal distancel is during greater than critical value 22, then Shu Chu positive edge data position is 0; Otherwise if this positive edge sitgnal distancel is during less than critical value 22, then Shu Chu positive edge data position is 1.Wherein, when if the spacing between the positive edge signal is too big, utilize in positive edge data position compensation (compensation) signal to hard decision logical circuit (hard decision logic circuit) 24 and carry out signal compensation, then a n bit ripple counter 16 need not the spacing of this positive edge signal counted fully and finishes, and can obtain the data bit of positive edge data.
When a n bit ripple counter 16 is counted, the initial value of the 2nd n bit ripple counter 20 is reset to after the critical value 22, cooperate negative edge sitgnal distancel to begin to count comparison, to export a negative edge data position, this negative edge data position also is the most significant digit unit (MSB) of the n bit ripple counter of 1 or 0 binary data bit, if the spacing that should bear the edge signal is greater than critical value 22, then Shu Chu negative edge data position is 0; If spacing that should negative edge signal is less than critical value 22, then the 2nd n bit ripple counter 20 negative edge data position of being exported is 1.Wherein, when if the spacing of negative edge signal is too big, utilize a negative edge data position compensating signal to carry out signal compensation to this hard decision logical circuit 24, then the 2nd n bit ripple counter 20 need not negative edge sitgnal distancel counted fully and finishes, and can obtain this negative edge data position.
Positive edge data position and negative edge data position that the one n bit ripple counter 16 and the 2nd n bit ripple counter 20 are counted out are sent in the hard decision logical circuit 24 simultaneously, this hard decision logical circuit 24 carries out the frequency reducing judgement according to positive edge data position and negative edge data position, and cooperate positive edge data position compensating signal and negative edge data position compensating signal to carry out the compensation of signal simultaneously, and then send out a fundamental frequency signal.So, can in hard decision logical circuit 24, make judgement simultaneously by positive edge data position compensating signal and negative edge data position compensating signal by nationality,, and then significantly reduce the bit error with the accuracy of fundamental frequency signal after the increase demodulation.
The present invention utilizes aforementioned way can save the logic gate number that tradition needs multidigit unit comparator again; Signal compensation part is then because of the spacing of supposing adjacent positive edge signal or the distance of the spacing of adjacent negative edge signal when oversize, can cause the resolution of hard decision logical circuit 24 to reduce, so utilize a positive edge or negative edge data position compensating signal to hard decision logical circuit 24, to carry out signal compensation, finish and need not sitgnal distancel counted fully, can obtain positive edge data position and negative edge data position.
Therefore, the present invention utilizes quarter-phase should be used for carrying out the demodulation of signal, and can increase the intermediate frequency frequency-shift keying and separate the resolution of timing, and can reduce the gate number simultaneously and shorten signal delay time, and the consumption that effectively reduces electric current.In addition, the invention allows for a kind of simple and practical quarter-phase FSK digital demodulator, it can reduce chip area, makes digital demodulator have the advantage that structure is little, economize area, and wireless product is light to meet, book, short and small trend.
Above-mentionedly only the preferred embodiment among the present invention is described; but can not be as protection scope of the present invention; because of as those skilled in the art it being made corresponding modification and modification is fine; therefore; the equivalence that designs spirit and make of the present invention of every foundation changes or modifies, and all should think to fall into protection scope of the present invention.

Claims (19)

1.一种双相位FSK数字解调器，用于接收经放大、滤波与合成处理后的中频信号，该双相位FSK数字解调器包括有：1. A dual-phase FSK digital demodulator is used to receive the intermediate frequency signal after amplification, filtering and synthesis processing, and this dual-phase FSK digital demodulator includes: 至少一用于分别检测撷取中频信号的正缘信号与负缘信号的检测电路；At least one detection circuit for respectively detecting the positive edge signal and the negative edge signal of the captured intermediate frequency signal; 一第一计数器，该计数器在根据不同的频带码选择相对的临界值后，接收正缘信号作为启动信号而将该第一计数器的初始值重置为临界值，并对相邻正缘信号之间的间距与该临界值开始计数比较，若比较后的正缘信号间距大于该临界值时，输出的正缘资料数据位为0，若该正缘信号的间距小于该临界值时，输出的正缘资料数据位为1，进而得到一正缘资料数据位；A first counter, after the counter selects the relative critical value according to different frequency band codes, receives the positive edge signal as the start signal to reset the initial value of the first counter to the critical value, and the adjacent positive edge signal The distance between them is compared with the critical value to start counting. If the distance between the positive edge signals after comparison is greater than the critical value, the data bit of the positive edge data output is 0. If the distance between the positive edge signals is smaller than the critical value, the output The positive edge data bit is 1, and then a positive edge data bit is obtained; 一第二计数器，该计数器接收负缘信号作为启动信号而将第二计数器的初始值重置为临界值，并对相邻负缘信号之间的间距与该临界值开始计数比较，若比较后的负缘信号间距大于该临界值时，输出的负缘资料数据位为0，若该负缘信号的间距小于该临界值时，输出的负缘资料数据位为1，进而得到一负缘资料数据位；及A second counter, which receives the negative edge signal as a start signal and resets the initial value of the second counter to a critical value, and starts counting and comparing the interval between adjacent negative edge signals with the critical value, if after the comparison When the distance between the negative edge signals is greater than the critical value, the output negative edge data bit is 0, if the negative edge signal spacing is smaller than the critical value, the output negative edge data bit is 1, and then a negative edge data is obtained data bits; and 一硬判定逻辑电路，该硬判定逻辑电路是根据正缘资料数据位与负缘资料数据位进行降频判定，以传送出一基频信号。A hard-decision logic circuit. The hard-decision logic circuit performs down-frequency judgment according to the data bits of the positive edge and the data bits of the negative edge, so as to transmit a base frequency signal. 2.根据权利要求1中所述的双相位FSK数字解调器，其特征在于：在所述检测电路与所述第一计数器之间连接有一可将检测电路撷取到的正缘信号反相后送至第一计数器的反相器。2. According to the dual-phase FSK digital demodulator described in claim 1, it is characterized in that: a positive edge signal that can be captured by the detection circuit is connected between the detection circuit and the first counter. Feed to the inverter of the first counter. 3.根据权利要求1中所述的双相位FSK数字解调器，其特征在于：在所述检测电路与所述第二计数器之间连接有一可将检测电路撷取到的负缘信号反相后送至第二计数器的反相器。3. According to the dual-phase FSK digital demodulator described in claim 1, it is characterized in that: a negative edge signal that can be captured by the detection circuit is connected between the detection circuit and the second counter. It is sent to the inverter of the second counter. 4.根据权利要求1中所述的双相位FSK数字解调器，其特征在于：利用一系统脉冲来计算相邻的所述正缘信号之间的间距与所述负缘信号之间的间距。4. according to the two-phase FSK digital demodulator described in claim 1, it is characterized in that: utilize a system pulse to calculate the spacing between adjacent described positive edge signals and the spacing between the described negative edge signals . 5.根据权利要求1中所述的双相位FSK数字解调器，其特征在于：所述正缘信号的间距太大时，利用一正缘资料数据位补偿信号至所述硬判定逻辑电路中进行信号补偿，则第一计数器无需将该正缘信号间距完全计数完毕，即可得到正缘资料数据位。5. according to the dual-phase FSK digital demodulator described in claim 1, it is characterized in that: when the spacing of described positive edge signal is too large, utilize a positive edge data bit compensation signal to described hard decision logic circuit When the signal compensation is performed, the first counter can obtain the data bits of the positive edge without completely counting the interval of the positive edge signal. 6.根据权利要求1中所述的双相位FSK数字解调器，其特征在于：所述负缘信号的间距太大时，利用一负缘资料数据位补偿信号至所述硬判定逻辑电路中进行信号补偿，则第二计数器无需将该负缘信号间距完全计数完毕，即可得到负缘资料数据位。6. according to the dual-phase FSK digital demodulator described in claim 1, it is characterized in that: when the spacing of described negative edge signal is too large, utilize a negative edge data bit compensation signal to the described hard decision logic circuit When the signal compensation is performed, the second counter can obtain the negative edge data data bits without completely counting the negative edge signal intervals. 7.根据权利要求1中所述的双相位FSK数字解调器，其特征在于：所述正缘资料数据位与负缘资料数据位为1或0的二进制数据位。7. The dual-phase FSK digital demodulator according to claim 1, characterized in that: the positive edge data bit and the negative edge data bit are binary data bits of 1 or 0. 8.根据权利要求1中所述的双相位FSK数字解调器，其特征在于：所述第一计数器与第二计数器为n位元涟波计数器。8. The dual-phase FSK digital demodulator according to claim 1, wherein the first counter and the second counter are n-bit ripple counters. 9.根据权利要求1中所述的双相位FSK数字解调器，其特征在于：所述第一计数器输出的正缘资料数据位与第二计数器输出的负缘资料数据位都为最高有效数元。9. according to the two-phase FSK digital demodulator described in claim 1, it is characterized in that: the positive edge data data bit of the first counter output and the negative edge data data bit of the second counter output are all most significant numbers Yuan. 10.一种双相位FSK数字解调器的信号解调方法，其是在双相位FSK数字解调器接收经放大、滤波与合成处理后的中频信号后，进行解调步骤，该信号解调方法包括下列步骤：10. A signal demodulation method of a bi-phase FSK digital demodulator, which is after the bi-phase FSK digital demodulator receives the intermediate frequency signal after amplification, filtering and synthesis processing, and carries out a demodulation step, and the signal demodulation The method includes the following steps: 检测撷取中频信号的正缘信号与负缘信号；Detect and extract the positive edge signal and negative edge signal of the intermediate frequency signal; 根据不同的频带码选择相对的临界值后，接收正缘信号作为启动信号而将该临界值重置为初始值，并对相邻正缘信号之间的间距与该临界值开始计数比较，经计数比较后，若正缘信号间距大于该临界值时，输出的正缘资料数据位为0，若正缘信号的间距小于该临界值时，输出的正缘资料数据位为1，进而得到一正缘资料数据位；After selecting the relative critical value according to different frequency band codes, receive the positive edge signal as the start signal to reset the critical value to the initial value, and start counting and comparing the interval between adjacent positive edge signals with the critical value, and then After counting and comparing, if the positive edge signal spacing is greater than the critical value, the output positive edge data bit is 0, if the positive edge signal spacing is smaller than the critical value, the output positive edge data bit is 1, and then a Zhengyuan data data bit; 接收该负缘信号作为启动信号而将该临界值重置为初始值，并对相邻负缘信号之间的间距与该临界值开始计数比较，经计数比较后，负缘信号间距大于该临界值时，输出的负缘资料数据位为0，若负缘信号的间距小于该临界值时，输出的负缘资料数据位为1，进而得到一负缘资料数据位；Receiving the negative edge signal as a start signal resets the critical value to the initial value, and starts counting and comparing the interval between adjacent negative edge signals with the critical value. After counting and comparing, the negative edge signal spacing is greater than the critical value value, the output negative edge data bit is 0, if the negative edge signal spacing is less than the critical value, the output negative edge data bit is 1, and then a negative edge data bit is obtained; 根据该正缘资料数据位与该负缘资料数据位进行降频判定，以传送出一基频信号。The down-frequency determination is performed according to the positive edge data bit and the negative edge data bit, so as to transmit a base frequency signal. 11.根据权利要求10中所述的信号解调方法，其特征在于：在所述检测撷取到正缘信号的步骤后，可将该正缘信号进行反相后再进行计数比较。11. The signal demodulation method according to claim 10, characterized in that: after the step of detecting and capturing the positive edge signal, the positive edge signal can be inverted and then counted and compared. 12.根据权利要求10中所述的信号解调方法，其特征在于：在所述检测撷取到负缘信号的步骤后，可将该负缘信号进行反相后再进行计数比较。12. The signal demodulation method according to claim 10, characterized in that: after the step of detecting and extracting the negative edge signal, the negative edge signal can be inverted and then counted and compared. 13.根据权利要求10中所述的信号解调方法，其特征在于：在所述计算正缘信号之间的间距与负缘信号之间的间距步骤中是利用一系统脉冲来计算间距。13. The signal demodulation method according to claim 10, characterized in that: in the step of calculating the spacing between positive edge signals and the spacing between negative edge signals, a system pulse is used to calculate the spacing. 14.根据权利要求10中所述的信号解调方法，其特征在于：在对正、负缘信号间距进行计数时是利用二n位元涟波计数器分别进行的。14. The signal demodulation method according to claim 10, characterized in that: the two n-bit ripple counters are used to count the positive and negative edge signal intervals respectively. 15.根据权利要求10中所述的信号解调方法，其特征在于：所述降频判定的步骤是在一硬判定逻辑电路中进行。15. The signal demodulation method according to claim 10, characterized in that: the step of determining frequency reduction is performed in a hard decision logic circuit. 16.根据权利要求10中所述的信号解调方法，其特征在于：所述正缘信号的间距太大时是利用一正缘资料数据位补偿信号进行信号补偿，则无需将该正缘信号间距完全计数完毕，即可得到正缘资料数据位。16. According to the signal demodulation method described in claim 10, it is characterized in that: when the spacing of the positive edge signal is too large, a positive edge data bit compensation signal is used to perform signal compensation, and there is no need to use the positive edge signal After the spacing is completely counted, the data bits of positive edge data can be obtained. 17.根据权利要求10中所述的信号解调方法，其特征在于：所述负缘信号的间距太大时是利用一负缘资料数据位补偿信号进行信号补偿，则无需将该负缘信号间距完全计数完毕，即可得到负缘资料数据位。17. According to the signal demodulation method described in claim 10, it is characterized in that: when the spacing of the negative edge signal is too large, a negative edge data data bit compensation signal is used to perform signal compensation, and there is no need to use the negative edge signal After the spacing is completely counted, the data bits of the negative edge data can be obtained. 18.根据权利要求10中所述的信号解调方法，其特征在于：所述正缘资料数据位及负缘资料数据位为1或0的二进制数据位。18. The signal demodulation method according to claim 10, characterized in that: the positive edge data bit and the negative edge data bit are binary data bits of 1 or 0. 19.根据权利要求10中所述的信号解调方法，其特征在于：所述正缘资料数据位与负缘资料数据位都为最高有效数元。19. The signal demodulation method according to claim 10, wherein the data bits of the positive edge and the data bits of the negative edge are both most significant digital elements.
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