CN1265604C - Double-phase FSK digital demodulator and signal demodulating method thereof - Google Patents
Double-phase FSK digital demodulator and signal demodulating method thereof Download PDFInfo
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- CN1265604C CN1265604C CN 02156457 CN02156457A CN1265604C CN 1265604 C CN1265604 C CN 1265604C CN 02156457 CN02156457 CN 02156457 CN 02156457 A CN02156457 A CN 02156457A CN 1265604 C CN1265604 C CN 1265604C
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Abstract
The present invention discloses a double-phase FSK digital demodulator and a signal demodulating method thereof. The double-phase FSK digital demodulator uses at least one detecting circuit to respectively detect and acquire a positive edge signal and a negative edge signal of an intermediate frequency signal; then two ripple counters are used to refer a critical value and receive the positive edge signal and the negative edge signal as starting signals, the critical value is reset as an initial value of the ripple counters to carry out counting comparison, and a positive edge data bit and a negative edge data bit are output; finally, the positive edge data bit and the negative edge data bit are positioned in a hard decision logic circuit to carry out frequency reducing decision and send out a fundamental frequency signal. The double-phase FSK digital demodulator of the present invention not only can reduce the number of logic gates and shorten the edge-prolonging time of the signals, but also can increase the resolution degree of the demodulation. The present invention is a simple and practical double-phase FSK digital demodulator which is in accordance with the development trends of light, thin, short and small.
Description
Technical field
The present invention relates to a kind of modulating signal technology of digital radio communication receiving/transmission module, more particularly, relate to a kind of wireless intermediate frequency (IF) frequency shift keying (Frequency Shift Keying, FSK) quarter-phase in (Two Phase) FSK digital demodulator (demodulator) and signal demodulating method thereof of being applied in.
Background technology
Along with the popularizing of significantly development, the network of communication product in recent years, the rise of information household electrical appliances and application of radio communication, digital broadcasting and broadband network or the like, prove the arriving of " information age " amply, the transmission that is to say information will be rapider, also with diversification more.And in order to satisfy the increase of people to information requirement, wireless communication technique is also more and more paid attention to, and the demand of wireless product is also increased.
Radio frequency/intermediate frequency module in the radio communication product is formed with three unit of wireless transmission by wireless receiving, signal are synthetic, and wherein the radio receiving unit circuit etc. that is used to eliminate jamming incoherent signal, automatic gain adjustment by radio frequency head end, mixer, intermediate frequency amplifier and demodulator and other is formed.Basically, this radio frequency/intermediate frequency module be the signal that will receive after amplification, filtering and synthetic the processing, utilize demodulator that the intermediate-freuqncy signal demodulation is reduced into fundamental frequency signal originally, handle in order to follow-up fundamental frequency signal; Therefore, demodulator is being played the part of the role who can not be ignored in digital radio communication receiving/transmission module.
When tradition is utilized the underway frequency demodulated signal of the fsk demodulator of frequency modulation technology, be to utilize a mixer (Mixer) to carry out the frequency reducing first time earlier, the signal that is about to the intermediate-freuqncy signal frequency reducing and is high Q value makes the signal complex calculation formula designed through inside calculate afterwards again, this signal down could be demodulated to fundamental frequency signal after as calculated; Utilize this kind mode will cause the time and the shared gate number (logic gate counts) of increase of inhibit signal, in addition, the required chip area of this traditional RTL digital Design circuit that fsk demodulator adopted is bigger, and current drain is also higher relatively.
For this reason, creator among the present invention relies on it to be engaged in the experience and the practice of relevant industries for many years, and through concentrating on studies and developing, create quarter-phase FSK digital demodulator and signal demodulating method thereof among the present invention eventually, carry out demodulation and existing deficiency with the above-mentioned traditional F SK demodulator that utilizes of effective solution.
Summary of the invention
To transfer the main purpose of device and signal demodulating method thereof be not enough in order to solve the resolution (resolution) that existing demodulator separates timing frequently at the centering frequency tone of Chinese characters for quarter-phase FSK numeral among the present invention, and problem such as effect is remarkable inadequately when Low Medium Frequency.
Another order of quarter-phase FsK digital demodulator and signal demodulating method thereof is to solve existing demodulator and signal demodulating method meeting inhibit signal time, increases the gate number and has the problem that relative high current consumes among the present invention.
An order again of quarter-phase FSK digital demodulator and signal demodulating method thereof is bigger in order to solve the existing required chip area of demodulator among the present invention, thereby causes demodulator structure big, does not meet that wireless product is light, thin, the problem of short and small trend.
The another purpose of quarter-phase FSK digital demodulator and signal demodulating method thereof is not have the signal compensation function in order to solve existing digital demodulator among the present invention, thereby has the problem of big frequency error.
For achieving the above object, the quarter-phase FSK digital demodulator among the present invention includes:
At least onely be used for detecting respectively the positive edge signal of acquisition intermediate-freuqncy signal and the testing circuit of negative edge signal;
One first counter, this counter is after selecting relative critical value according to different band codes, receive positive edge signal as enabling signal and the initial value of this first counter is reset to critical value, and the spacing between the adjacent positive edge signal and this critical value begun counting relatively, if the positive edge sitgnal distancel relatively is during greater than this critical value, the positive edge data position of output is 0, if the spacing of this positive edge signal is during less than this critical value, the positive edge data position of output is 1, and then obtains a positive edge data position;
One second counter, this counter receives negative edge signal and as enabling signal the initial value of second counter is reset to critical value, and the spacing between the adjacent negative edge signal and this critical value begun counting relatively, if the negative edge sitgnal distancel relatively is during greater than this critical value, the negative edge data position of output is 0, if spacing that should negative edge signal is during less than this critical value, the negative edge data position of output is 1, and then obtains a negative edge data position; And
One hard decision logical circuit, this hard decision logical circuit are to carry out the frequency reducing judgement according to positive edge data position and negative edge data position, to send out a fundamental frequency signal.
In addition, when if the spacing of positive edge or negative edge signal is too big, can utilize a positive edge or negative edge data position compensating signal to the hard decision logical circuit, to carry out signal compensation, then need not sitgnal distancel counted fully and finish, can obtain main track or negative edge data position.
The signal demodulating method of quarter-phase FSK digital demodulator is to receive after the intermediate-freuqncy signal after amplification, filtering and synthetic the processing at quarter-phase FSK digital demodulator among the present invention, carries out demodulation step, and this signal demodulating method comprises the following steps:
Detect the positive edge signal and the negative edge signal of acquisition intermediate-freuqncy signal;
After the relative critical value of different band code selections, receive positive edge signal and this critical value is reset to initial value as enabling signal, and the spacing between the adjacent positive edge signal and this critical value begun counting relatively, after counting relatively, if positive edge sitgnal distancel is during greater than this critical value, the positive edge data position of output is 0, if the spacing of positive edge signal is during less than this critical value, the positive edge data position of output is 1, and then obtains a positive edge data position;
Receive and as enabling signal this critical value to be reset to initial value by negative edge signal, and the spacing between the adjacent negative edge signal and this critical value begun counting relatively, after counting relatively, if when bearing the edge sitgnal distancel greater than this critical value, the negative edge data position of output is 0, if the spacing of negative edge signal is during less than this critical value, the negative edge data position of output is 1, and then obtains a negative edge data position;
Carry out frequency reducing according to the negative edge data position of this positive edge data position and this and judge, to send out a fundamental frequency signal.
Not only can reduce the gate number behind quarter-phase fsk demodulator in utilizing the present invention and the demodulation method thereof and shorten signal and prolong the limit time, and can increase the demodulation resolution, be a simple and practical quarter-phase FSK digital demodulator in fact, meet light, thin, the short and small development trend of wireless product.
Description of drawings
Below in conjunction with accompanying drawing the specific embodiment among the present invention is described in further detail.
Fig. 1 is the structural representation of quarter-phase FSK digital demodulator among the present invention;
Fig. 2 is the waveform signal schematic diagram of quarter-phase FSK digital demodulator when detecting positive and negative edge signal among the present invention.
Embodiment
The present invention utilizes a pair of counter that one intermediate-freuqncy signal (IF) is carried out a quarter-phase (two phase) Signal Processing, positive edge signal and negative edge signal by quarter-phase carry out the demodulation of signal, and reach reduction gate number, shorten signal delay time and increase demodulation resolution (resolution).When particularly the demodulator among the present invention being applied in Low Medium Frequency (low IF), its effect will be more remarkable.
Quarter-phase FSK digital demodulator among the present invention and signal demodulating method thereof can be taken this figure the structure of whole quarter-phase FSK digital demodulator and the whole flow process of carrying out the signal demodulation thereof are described simultaneously with reference to shown in Figure 1.When radio receiving unit receives a radio frequency signal, after handling via the amplification of elements such as radio frequency head end, mixer, intermediate frequency amplifier, filtering and synthetic etc., will transmit in FSK intermediate-freuqncy signal to the quarter-phase FSK digital demodulator.
As shown in Figure 1, after a quarter-phase FSK digital demodulator 10 receives the FSK intermediate-freuqncy signal, utilize at least one testing circuit 12 in the cycle of each FSK intermediate-freuqncy signal, to detect earlier, capture positive edge and align the positive edge signal of edge (positive edge-to-positive edge) and negative edge negative edge signal negative edge (negative edge-to-negative edge), simultaneously as shown in Figure 2, after testing circuit 12 captures positive edge signal, be sent to after utilizing an inverter 14 with positive edge signal inversion earlier in the n bit ripple counter (n-bit ripple counter) 16 as enabling signal, and the initial value of a n bit ripple counter 16 is reset to critical value (threshold value) 22 (use two complement be negative); Simultaneously, testing circuit 12 is after capturing negative edge signal, also utilize an inverter 18 to give this negative edge signal anti-phase, be resent in one the 2nd n bit ripple counter 20 as enabling signal, and the initial value of the 2nd n bit ripple counter 20 is reset to critical value 22 (use two complement be negative).Wherein, this critical value 22 has different respective value according to different band code (channel code).
Before counting comparison, utilize system pulse to go respectively to calculate the distance between the adjacent positive edge signal earlier and obtain a positive edge sitgnal distancel, and calculate the distance between the adjacent negative edge signal simultaneously and obtain a negative edge sitgnal distancel.At this moment, the one n bit ripple counter 16 initial values are reset to after the critical value 22, cooperate positive edge sitgnal distancel to begin to count comparison, to export a positive edge data position (data bit), it is (the MostSignificant Bit of most significant digit unit of the n bit ripple counter of 1 or 0 binary data bit, MSB), if this positive edge sitgnal distancel is during greater than critical value 22, then Shu Chu positive edge data position is 0; Otherwise if this positive edge sitgnal distancel is during less than critical value 22, then Shu Chu positive edge data position is 1.Wherein, when if the spacing between the positive edge signal is too big, utilize in positive edge data position compensation (compensation) signal to hard decision logical circuit (hard decision logic circuit) 24 and carry out signal compensation, then a n bit ripple counter 16 need not the spacing of this positive edge signal counted fully and finishes, and can obtain the data bit of positive edge data.
When a n bit ripple counter 16 is counted, the initial value of the 2nd n bit ripple counter 20 is reset to after the critical value 22, cooperate negative edge sitgnal distancel to begin to count comparison, to export a negative edge data position, this negative edge data position also is the most significant digit unit (MSB) of the n bit ripple counter of 1 or 0 binary data bit, if the spacing that should bear the edge signal is greater than critical value 22, then Shu Chu negative edge data position is 0; If spacing that should negative edge signal is less than critical value 22, then the 2nd n bit ripple counter 20 negative edge data position of being exported is 1.Wherein, when if the spacing of negative edge signal is too big, utilize a negative edge data position compensating signal to carry out signal compensation to this hard decision logical circuit 24, then the 2nd n bit ripple counter 20 need not negative edge sitgnal distancel counted fully and finishes, and can obtain this negative edge data position.
Positive edge data position and negative edge data position that the one n bit ripple counter 16 and the 2nd n bit ripple counter 20 are counted out are sent in the hard decision logical circuit 24 simultaneously, this hard decision logical circuit 24 carries out the frequency reducing judgement according to positive edge data position and negative edge data position, and cooperate positive edge data position compensating signal and negative edge data position compensating signal to carry out the compensation of signal simultaneously, and then send out a fundamental frequency signal.So, can in hard decision logical circuit 24, make judgement simultaneously by positive edge data position compensating signal and negative edge data position compensating signal by nationality,, and then significantly reduce the bit error with the accuracy of fundamental frequency signal after the increase demodulation.
The present invention utilizes aforementioned way can save the logic gate number that tradition needs multidigit unit comparator again; Signal compensation part is then because of the spacing of supposing adjacent positive edge signal or the distance of the spacing of adjacent negative edge signal when oversize, can cause the resolution of hard decision logical circuit 24 to reduce, so utilize a positive edge or negative edge data position compensating signal to hard decision logical circuit 24, to carry out signal compensation, finish and need not sitgnal distancel counted fully, can obtain positive edge data position and negative edge data position.
Therefore, the present invention utilizes quarter-phase should be used for carrying out the demodulation of signal, and can increase the intermediate frequency frequency-shift keying and separate the resolution of timing, and can reduce the gate number simultaneously and shorten signal delay time, and the consumption that effectively reduces electric current.In addition, the invention allows for a kind of simple and practical quarter-phase FSK digital demodulator, it can reduce chip area, makes digital demodulator have the advantage that structure is little, economize area, and wireless product is light to meet, book, short and small trend.
Above-mentionedly only the preferred embodiment among the present invention is described; but can not be as protection scope of the present invention; because of as those skilled in the art it being made corresponding modification and modification is fine; therefore; the equivalence that designs spirit and make of the present invention of every foundation changes or modifies, and all should think to fall into protection scope of the present invention.
Claims (19)
1. a quarter-phase FSK digital demodulator is used to receive the intermediate-freuqncy signal after amplification, filtering and synthetic the processing, and this quarter-phase FSK digital demodulator includes:
At least onely be used for detecting respectively the positive edge signal of acquisition intermediate-freuqncy signal and the testing circuit of negative edge signal;
One first counter, this counter is after selecting relative critical value according to different band codes, receive positive edge signal as enabling signal and the initial value of this first counter is reset to critical value, and the spacing between the adjacent positive edge signal and this critical value begun counting relatively, if the positive edge sitgnal distancel relatively is during greater than this critical value, the positive edge data position of output is 0, if the spacing of this positive edge signal is during less than this critical value, the positive edge data position of output is 1, and then obtains a positive edge data position;
One second counter, this counter receives negative edge signal and as enabling signal the initial value of second counter is reset to critical value, and the spacing between the adjacent negative edge signal and this critical value begun counting relatively, if the negative edge sitgnal distancel relatively is during greater than this critical value, the negative edge data position of output is 0, if spacing that should negative edge signal is during less than this critical value, the negative edge data position of output is 1, and then obtains a negative edge data position; And
One hard decision logical circuit, this hard decision logical circuit are to carry out the frequency reducing judgement according to positive edge data position and negative edge data position, to send out a fundamental frequency signal.
2. according to the quarter-phase FSK digital demodulator described in the claim 1, it is characterized in that: the inverter of after being connected with a positive edge signal inversion that testing circuit can be captured between described testing circuit and described first counter, delivering to first counter.
3. according to the quarter-phase FSK digital demodulator described in the claim 1, it is characterized in that: the inverter of after being connected with a negative edge signal inversion that testing circuit can be captured between described testing circuit and described second counter, delivering to second counter.
4. according to the quarter-phase FSK digital demodulator described in the claim 1, it is characterized in that: utilize system pulse to calculate spacing between the adjacent described positive edge signal and the spacing between the described negative edge signal.
5. according to the quarter-phase FSK digital demodulator described in the claim 1, it is characterized in that: when the spacing of described positive edge signal is too big, utilize a positive edge data position compensating signal to described hard decision logical circuit, to carry out signal compensation, then first counter need not this positive edge sitgnal distancel counted fully and finishes, and can obtain positive edge data position.
6. according to the quarter-phase FSK digital demodulator described in the claim 1, it is characterized in that: when the spacing of described negative edge signal is too big, utilize a negative edge data position compensating signal to described hard decision logical circuit, to carry out signal compensation, then second counter need not this negative edge sitgnal distancel counted fully and finishes, and can obtain negative edge data position.
7. according to the quarter-phase FSK digital demodulator described in the claim 1, it is characterized in that: described positive edge data position and negative edge data position are 1 or 0 binary data bit.
8. according to the quarter-phase FSK digital demodulator described in the claim 1, it is characterized in that: described first counter and second counter are n bit ripple counter.
9. according to the quarter-phase FSK digital demodulator described in the claim 1, it is characterized in that: the negative edge data position of the positive edge data position of described first counter output and the output of second counter all is a most significant digit unit.
10. the signal demodulating method of a quarter-phase FSK digital demodulator, it is to receive after the intermediate-freuqncy signal after amplification, filtering and the synthetic processing at quarter-phase FSK digital demodulator, carries out demodulation step, this signal demodulating method comprises the following steps:
Detect the positive edge signal and the negative edge signal of acquisition intermediate-freuqncy signal;
After the relative critical value of different band code selections, receive positive edge signal and this critical value is reset to initial value as enabling signal, and the spacing between the adjacent positive edge signal and this critical value begun counting relatively, after counting relatively, if positive edge sitgnal distancel is during greater than this critical value, the positive edge data position of output is 0, if the spacing of positive edge signal is during less than this critical value, the positive edge data position of output is 1, and then obtains a positive edge data position;
Receive and as enabling signal this critical value to be reset to initial value by negative edge signal, and the spacing between the adjacent negative edge signal and this critical value begun counting relatively, after counting relatively, when bearing the edge sitgnal distancel greater than this critical value, the negative edge data position of output is 0, if the spacing of negative edge signal is during less than this critical value, the negative edge data position of output is 1, and then obtains a negative edge data position;
Carry out frequency reducing according to the negative edge data position of this positive edge data position and this and judge, to send out a fundamental frequency signal.
11. the signal demodulating method according to described in the claim 10 is characterized in that: capture the step of positive edge signal in described detection after, this positive edge signal can be carried out counting comparison again after anti-phase.
12. the signal demodulating method according to described in the claim 10 is characterized in that: capture the step of negative edge signal in described detection after, can count comparison again after anti-phase with should negative edge signal carrying out.
13. the signal demodulating method according to described in the claim 10 is characterized in that: be to utilize system pulse to calculate spacing in spacing between the positive edge signal of described calculating and the spacing step between the negative edge signal.
14. the signal demodulating method according to described in the claim 10 is characterized in that: when positive and negative edge sitgnal distancel is counted, utilize two n bit ripple counters to carry out respectively.
15. the signal demodulating method according to described in the claim 10 is characterized in that: the step that described frequency reducing is judged is to carry out in a hard decision logical circuit.
16. according to the signal demodulating method described in the claim 10, it is characterized in that: the spacing of described positive edge signal is to utilize a positive edge data position compensating signal to carry out signal compensation when too big, then need not this positive edge sitgnal distancel counted fully and finish, can obtain positive edge data position.
17. according to the signal demodulating method described in the claim 10, it is characterized in that: the spacing of described negative edge signal is to utilize a negative edge data position compensating signal to carry out signal compensation when too big, then need not this negative edge sitgnal distancel counted fully and finish, can obtain negative edge data position.
18. the signal demodulating method according to described in the claim 10 is characterized in that: described positive edge data position and negative edge data position are 1 or 0 binary data bit.
19. the signal demodulating method according to described in the claim 10 is characterized in that: described positive edge data position and negative edge data position all are most significant digit unit.
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| CN 02156457 CN1265604C (en) | 2002-12-16 | 2002-12-16 | Double-phase FSK digital demodulator and signal demodulating method thereof |
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| CN 02156457 CN1265604C (en) | 2002-12-16 | 2002-12-16 | Double-phase FSK digital demodulator and signal demodulating method thereof |
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