CN1263145C - Ultraviolet ray programmed P-type mask type ROM and making method thereof - Google Patents
Ultraviolet ray programmed P-type mask type ROM and making method thereof Download PDFInfo
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- CN1263145C CN1263145C CN02106042.8A CN02106042A CN1263145C CN 1263145 C CN1263145 C CN 1263145C CN 02106042 A CN02106042 A CN 02106042A CN 1263145 C CN1263145 C CN 1263145C
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- ultraviolet ray
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- 238000000034 method Methods 0.000 title claims description 34
- 238000004519 manufacturing process Methods 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 23
- 239000002019 doping agent Substances 0.000 claims description 23
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 239000002131 composite material Substances 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 230000000903 blocking effect Effects 0.000 claims 6
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 50
- 239000000463 material Substances 0.000 description 12
- 230000000694 effects Effects 0.000 description 8
- 238000002347 injection Methods 0.000 description 8
- 239000007924 injection Substances 0.000 description 8
- 238000012163 sequencing technique Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005755 formation reaction Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000006396 nitration reaction Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000011241 protective layer Substances 0.000 description 2
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
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Abstract
The present invention relates to an ultraviolet ray programmed P-type mask ROM and a manufacturing method thereof. Firstly, the initial voltages of all memory units are increased, so that all memory units are in a first logic state (0 or 1) which is difficult to be conducted, and thus, current leakage between bit lines is avoided; then, after the bit lines and character lines are formed, a memory unit for storing a second logic value (1 or 0) is radiated by ultraviolet rays, so that electrons are injected into a nitride layer in the memory unit, and programming is carried out.
Description
Technical field
The invention relates to a kind of read-only memory (read only memory, abbreviation ROM) manufacture method, and be particularly to a kind of ultraviolet ray programmed P type mask-type ROM (UV-programmed P-type mask ROM) and manufacture method thereof.
Background technology
Present P type mask-type ROM generally includes the substrate with N type trap, the bit line (Bit Line) that is arranged in N type trap, the character line (Word Line) across also vertical bit line, the silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide between N type trap and character line, be called for short ONO) composite bed, and the oxide layer between bit line and character line.
Yet after design more and more high in the requirement of circuit integration, circuit element also developed toward downsizing, high leakage current (Current Leakage) can take place and make because line-spacing is too small in above-mentioned P type mask-type ROM between the bit line when operation.For addressing the above problem, known technology proposes a kind of manufacture method of P type mask-type ROM again, mainly be after the making of finishing bit line and character line, implement the injection technology (Blanket ErasingImplantation) of comprehensively erasing, to increase the concentration that belongs to the N type well of light doping originally, so as to improving the problem of leakage current.
But the method that known technology was improved but easily because of the control deviation of the implantation dosage (Dosage) of wherein the injection technology of erasing comprehensively, lacks and produce.That is to say, when the implantation dosage of the injection technology of comprehensively erasing is not enough, still have the problem of leakage current; And when implantation dosage is too high, again can be because of impurity (Dopant) horizontal proliferation of injecting N type trap to passage (Channel), and produce short-channel effect (Short Channel Effect).
Summary of the invention
The purpose of this invention is to provide a kind of ultraviolet ray programmed P type mask-type ROM and manufacture method thereof, can avoid producing between the bit line leakage current.
A further object of the present invention provides a kind of P type mask-type ROM and manufacture method thereof of ultraviolet erasing, and it does not have the implantation dosage deficiency of known technology because of the injection technology of erasing comprehensively, and the leakage between bit lines flow problem that still exists.
Another object of the present invention provides a kind of P type mask-type ROM and manufacture method thereof of ultraviolet erasing, and it is too high because of the implantation dosage of the injection technology of erasing comprehensively that it does not have known technology, and the short-channel effect that produces.
According to above-mentioned and other purpose, the present invention proposes a kind of manufacture method of ultraviolet ray programmed P type mask-type ROM, the method improves the starting voltage (Threshold Voltage) of all memory cell (Memory Cell) earlier, first logic state (0 or 1) that all memory cell all is in be difficult to conducting for example forms a dense dopant well (Heavily Doped Well).Then, form a charge immersing layer (Charge Trapping Layer) on substrate, charge immersing layer for example is stacking-type (Stacked) structure of silicon monoxide/nitrogenize silicon/oxidative silicon (ONO) composite bed.Then, form bit line in dense dopant well, form insulating barrier again on bit line, it for example is a thermal oxide layer.Afterwards, on substrate, form one deck conductor layer, this conductor layer of patterning is to form character line again, wherein the etch-stop of character line is in the bottom oxide (Bottom Oxide) of silicon oxide/silicon nitride/silicon oxide (ONO) charge immersing layer, and the substrate between each bit line of character line below is as a plurality of memory cell.Then, but on substrate, form the material layer of shielding of ultraviolet, it for example is to absorb ultraviolet material layer, and this material layer has several openings and is positioned on the character line of memory cell that desire stores second logical value (1 or 0), use the ultraviolet irradiation substrate subsequently, make electronics inject silicon oxide/silicon nitride/silicon oxide (ONO) charge immersing layer under these openings, to carry out sequencing.
The present invention proposes a kind of ultraviolet ray programmed P type mask-type ROM in addition, comprise a dense dopant well substrate, the bit line in dense dopant well, be across character line, the silicon oxide/silicon nitride/silicon oxide between dense dopant well and character line (ONO) charge immersing layer on the bit line, but and the material layer that is positioned at shielding of ultraviolet on the substrate, wherein the substrate between each bit line of character line below is as a plurality of memory cell, but and the material layer of shielding of ultraviolet for example be one can absorb ultraviolet material layer.This material layer has several openings and is positioned on the memory cell partly, and these memory cell are to write with ultraviolet ray.
Because the present invention is formed on all memory cell on the dense dopant well, re-uses the ultraviolet irradiation substrate to carry out sequencing, so significantly reduced the leakage current between the bit line.
In addition, owing to have only silicon nitride layer to have the effect of stored electrons, so when the present invention uses the ultraviolet irradiation substrate, only limit the silicon oxide/silicon nitride/silicon oxide charge immersing layer under the character line of opening below can stored electrons, and the starting voltage of the memory cell under the opening is reduced, and can not produce short-channel effect.
Description of drawings
Figure 1A～Fig. 6 A and Figure 1B～Fig. 6 B is respectively manufacturing process profile and the vertical view according to a kind of ultraviolet ray programmed P type mask-type ROM of preferred embodiment of the present invention.
10: substrate
100: dense dopant well
102: charge immersing layer
104: bottom oxide
106: nitration case
108: the top oxide layer
110: bit line
112: thermal oxide layer
114: character line
116: protective layer
118: anti-reflecting layer
120: inner layer dielectric layer
122: can absorb ultraviolet material layer
124: opening
126: ultraviolet ray
128a: by the ultraviolet zone that writes
128b: the memory cell that is in the state of " 0 "
130: the contact hole connector
Embodiment
For the problem of leakage current takes place between the bit line that prevents P type mask-type ROM (P-type Mask ROM), and impel element to develop towards miniaturization, therefore the invention provides a kind of manufacture method of ultraviolet ray programmed P type mask-type ROM (UV-programmed P-typeMask ROM).
Figure 1A～Fig. 6 A and Figure 1B～Fig. 6 B is respectively manufacturing process profile and the vertical view according to a kind of ultraviolet ray programmed P type mask-type ROM of preferred embodiment of the present invention.
Please refer to Figure 1A and Figure 1B, on substrate 10, form the dense dopant well (Heavily Doped Well) 100 of a N type earlier, to improve the starting voltage (Threshold Voltage) of all memory cell (MemoryCell) that form afterwards, make all memory cell be in the state of " 0 ".Wherein, as being that impurity forms dense dopant well 100 with phosphorus, its condition is the injection energy and 2.5 * 10 of 360KeV
13～5 * 10
13Atom/cm
2Dosage, or the injection energy and 5 * 10 of 60KeV
12～9 * 10
12Atom/cm
2Dosage.Then on substrate 10, form a charge immersing layer (Trapping Layer) 102 again, wherein charge immersing layer 102 is by a bottom oxide (Bottom Oxide) 104, one nitration case 106 and 108 formations of a top oxide layer (Top Oxide), silicon oxide/silicon nitride/silicon oxide (Oxide-Nitride-Oxide, be called for short ONO) layer just.Then, come out in substrate 10 surfaces that utilize Patternized technique to make the part desire form bit line.Subsequently, carry out injection technology in dense dopant well 100, to form bit line 110.The detailed cross sectional view of above technology is shown in Figure 1A, and Figure 1B is the vertical view of its array (Array).
Then, please refer to Fig. 2 A and Fig. 2 B, on bit line 110, form thermal oxide layer 112, with the character line of isolated bit line 110 with follow-up formation.
Then, please refer to Fig. 3 A and Fig. 3 B, form character line 114 on substrate 10, its detailed process for example forms one deck conductor layer earlier on substrate 10, and its material for example is a polysilicon.Then, this conductor layer of patterning, to form character line 114 across also vertical bit line 110, wherein etch-stop is in the bottom oxide 104 of charge immersing layer 102 during patterning character line 114, so 102 of silicon oxide/silicon nitride/silicon oxide (0NO) charge immersing layer are present under the character line 114.The substrate 10 of position this moment between the bit line below the character line 114 110 is as a plurality of memory cell
Then; please refer to Fig. 4 A and Fig. 4 B; on substrate 10, form and to absorb ultraviolet material layer 122; this material layer 122 can with the contact hole process integration of peripheral circuit; and comprise layer protective layer 116, one deck anti-reflecting layer (Anti-Reflection Coating; be called for short ARC) 118 with one deck inner layer dielectric layer (Inter-Layer Dielectrics is called for short ILD) 120, wherein the manufacture method of anti-reflecting layer 118 is a chemical vapour deposition technique for example.In Fig. 4 B shown be the vertical view that can find out character line and bit line position, Fig. 5 B afterwards and Fig. 6 B are too.
Subsequently, please refer to Fig. 5 A and Fig. 5 B, form several openings 124 in the material layer 122 on the memory cell that is selected, and the memory cell that is selected is for desiring the memory cell of stored electrons position " 1 " (e-bit (1)).Then, re-use ultraviolet ray 126 irradiation substrates 10, make electronics inject silicon oxide/silicon nitride/silicon oxide (ONO) charge immersing layer 102 under the opening 124, carrying out sequencing (" 0 " R " 1 "), and form the memory cell 128a that is write by ultraviolet ray.Comparatively speaking, please refer to Fig. 5 B, the memory cell that the top does not form opening is the memory cell 128b of the state that is in " 0 ".Owing to have only silicon nitride layer 106 in the silicon oxide/silicon nitride/silicon oxide charge immersing layer 102 to have the effect of stored electrons, so when the present invention uses ultraviolet ray 126 irradiation substrates 10, only have for 124 times the starting voltage at the position of silicon nitride layer 106 existence to be lowered at opening.
At last, please refer to Fig. 6 A and Fig. 6 B, if with the situation of the contact hole process integration of peripheral circuit under, also be included in and form a contact hole connector 130 in the opening 124.And belong to the dummy pattern (DummyPattern) of P type mask-type ROM in the contact hole connector 130 of this formation, can't influence its operation.
In sum, feature of the present invention comprises:
1. the present invention system is formed on all memory cell on the dense dopant well, re-uses ultraviolet ray and shines Penetrate substrate to carry out sequencing, so significantly reduced the leakage current between the bit line.
2. owing to only have silicon nitride layer to have the effect of stored electrons, use purple so work as the present invention During outside line irradiation substrate, only limit the silicon oxide/silicon nitride/silicon oxide electricity under the character line under the opening The lotus immersed layer can stored electrons, and its starting voltage is lowered, and can not produce jitty Effect.
Claims (20)
1, a kind of ultraviolet ray programmed P type mask-type ROM is characterized in that this read-only memory comprises:
One dense dopant well is arranged in a substrate;
Multiple bit lines is arranged in this dense dopant well;
One insulating barrier is positioned on those bit lines;
Many character line is across on those bit lines, and this substrate between those bit lines of those character line belows is as a plurality of memory cell;
One charge immersing layer is between those character lines and this dense dopant well; And
One ultraviolet blocking layer is positioned on this substrate, and this ultraviolet blocking layer has a plurality of openings and is positioned on those memory cell partly, and those memory cell of this part are to write with ultraviolet ray.
2, ultraviolet ray programmed P type mask-type ROM as claimed in claim 1 is characterized in that an impurity of this dense dopant well is phosphorus.
3, ultraviolet ray programmed P type mask-type ROM as claimed in claim 1 is characterized in that, the cell stores electronic bits " 1 " that those are write by ultraviolet ray.
4, ultraviolet ray programmed P type mask-type ROM as claimed in claim 1 is characterized in that, this charge immersing layer comprises silicon monoxide/nitrogenize silicon/oxidative silicon composite bed.
5, ultraviolet ray programmed P type mask-type ROM as claimed in claim 1 is characterized in that this insulating barrier comprises a thermal oxide layer.
6, ultraviolet ray programmed P type mask-type ROM as claimed in claim 1 is characterized in that this ultraviolet blocking layer comprises a UV-absorbing layer.
7, ultraviolet ray programmed P type mask-type ROM as claimed in claim 6 is characterized in that this UV-absorbing layer comprises an anti-reflecting layer.
8, a kind of manufacture method of ultraviolet ray programmed P type mask-type ROM is characterized in that this method comprises:
In a substrate, form a dense dopant well;
On this substrate, form a charge immersing layer;
In this dense dopant well, form multiple bit lines;
Be positioned at and form an insulating barrier on those bit lines;
On this substrate, form a conductor layer;
This conductor layer of patterning is across on those bit lines to form many character lines, and wherein this substrate between those bit lines of those character line belows is as a plurality of memory cell;
Form a ultraviolet blocking layer on this substrate, this ultraviolet blocking layer has a plurality of openings and is positioned on a plurality of selected memory cell; And
Write those selected memory cell by ultraviolet ray.
9, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 8 is characterized in that, the cell stores electronic bits " 1 " that those are selected.
10, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 8 is characterized in that an impurity of this dense dopant well is phosphorus.
11, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 10 is characterized in that, it is 360KeV that one of this dense dopant well injects energy.
12, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 11 is characterized in that an implantation dosage of this dense dopant well is 2.5 * 10
13～5 * 10
13Atom/cm
2Between.
13, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 10 is characterized in that, it is 60KeV that one of this dense dopant well injects energy.
14, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 13 is characterized in that an implantation dosage of this dense dopant well is 5 * 10
12～9 * 10
12Atom/cm
2Between.
15, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 8 is characterized in that this charge immersing layer comprises silicon monoxide/nitrogenize silicon/oxidative silicon composite bed.
16, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 15 is characterized in that, is that a bottom oxide with this silicon oxide/silicon nitride/silicon oxide composite bed is as an etch stop layer in the step of this conductor layer of patterning.
17, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 8 is characterized in that this insulating barrier comprises a thermal oxide layer.
18, the manufacture method of ultraviolet ray programmed P type mask-type ROM as claimed in claim 8 is characterized in that this ultraviolet blocking layer comprises a UV-absorbing layer.
19, the manufacture method of the P type mask-type ROM of ultraviolet erasing as claimed in claim 18 is characterized in that this UV-absorbing layer comprises an anti-reflecting layer.
20, the manufacture method of the P type mask-type ROM of ultraviolet erasing as claimed in claim 19 is characterized in that the method that forms this anti-reflecting layer comprises chemical vapour deposition technique.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02106042.8A CN1263145C (en) | 2002-04-09 | 2002-04-09 | Ultraviolet ray programmed P-type mask type ROM and making method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN02106042.8A CN1263145C (en) | 2002-04-09 | 2002-04-09 | Ultraviolet ray programmed P-type mask type ROM and making method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1450646A CN1450646A (en) | 2003-10-22 |
| CN1263145C true CN1263145C (en) | 2006-07-05 |
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| CN02106042.8A Expired - Fee Related CN1263145C (en) | 2002-04-09 | 2002-04-09 | Ultraviolet ray programmed P-type mask type ROM and making method thereof |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100423213C (en) * | 2005-08-05 | 2008-10-01 | 旺宏电子股份有限公司 | Non-volatile memory operating method |
| US7544992B2 (en) | 2007-05-16 | 2009-06-09 | United Microelectronics Corp. | Illuminating efficiency-increasable and light-erasable embedded memory structure |
| CN101315934B (en) * | 2007-05-31 | 2012-06-27 | 联华电子股份有限公司 | Embedded optical erasing memory capable of improving illumination efficiency and manufacturing method thereof |
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2002
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| Publication number | Publication date |
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| CN1450646A (en) | 2003-10-22 |
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