CN1262092C - Method and system for synchronizing clock resuming in packet network - Google Patents
Method and system for synchronizing clock resuming in packet network Download PDFInfo
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- CN1262092C CN1262092C CNB031468764A CN03146876A CN1262092C CN 1262092 C CN1262092 C CN 1262092C CN B031468764 A CNB031468764 A CN B031468764A CN 03146876 A CN03146876 A CN 03146876A CN 1262092 C CN1262092 C CN 1262092C
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Abstract
The present invention discloses a method and a system for synchronizing clock restoring in packet networks. Firstly, one synchronous reference clock is restored to replace a public network clock in an ATM system by adding a self-adapting clock adjusting algorithm module and by being matched with a standard time scale processing module and a high precision crystal oscillator, and thereby, a synchronous service clock can be restored by referring to and adopting a synchronous residual time scale method. The present invention transmits TDM real-time services on an IP/Ethernet network and realizes TDMoIP/EloEthernet. The present invention really combines the traditional circuit services and packet services in an access network, causes inexpensive IP networks to bear circuit services, such as voices, hiring wires, video conferences, etc., lowers operating cost, and protects the investment of user's existing equipment. The present invention performs a key function for realizing the TDM+IP combination of access networks and MAN, and can be extensively used for the service integration and upgrade rebuilding of IP access networks.
Description
Technical field:
The present invention relates to a kind of be applied on the connectionless asynchronous random length Packet Based Network in, the synchronised clock restoration methods in the IP network/Ethernet net particularly.
Background technology:
In synchronous, PDH (Pseudo-synchronous Digital Hierarchy) (SDH, PDH), be extensive use of the analog or digital PHASE-LOCKED LOOP PLL TECHNIQUE and carry out the recovery of synchronised clock, so that from transmission code stream, recover business datum like clockwork.Can provide or transmit synchronously/accurate synchronised clock information but its precondition is a far-end, so that receiving end is extracted and recovered clock from code stream.
And such method and system is impracticable at IP/Ethernet on the net, because there is not required synchronous/accurate synchronizing information in the code stream of IP/Ethernet network transmission.Otherwise on IP network, behind the queuing of packet encapsulation, deblocking and the network of the successive bits stream information process IP layer of TDM business, the exchange process, its continuity and periodicity are damaged, produced packet delay shake (PDV, packet delay variable) phenomenon, this can produce large-scale packet delay, drift and shake, and phenomenons such as the error code when causing data to recover therefrom, step-out, slip.
Similar to the IP/Ethernet net, the ATM net also is a kind of asynchronous Packet Based Network, to transmitting the TDM signal on the net at ATM, ITU-T standard I .363 has made regulation to source clock frequency recovery method and has recommended: promptly under the situation that public network clock (for example 155Mb/s of SDH) transmission is arranged, regulation adopts synchronous residual time mark method, i.e. Synchronous residual time stamp method (SRTS); Under the situation of no net clock transmission (when for example between asynchronous difference net, transmitting), recommend to adopt adaptive clock recovery method (Adaptive clock method), but the latter's indignant thought only is provided, do not stipulate concrete grammar.
Because of IP/Ethernet does not have general public network clock, can't the synchronous residual time mark method SRTS of adopting by reference, only may adopt similar adaptive clock recovery method.But different with IP/Ethernet net is, ATM is connection-oriented, regular length, the grouping of note unit; Thereby the relative IP/Ethernet net of packet delay, drift and shake of its cell transmission comes much smaller.Through evidence, the adaptive clock recovery method of directly diverting from one use to another the former ATM of being used for net also is impracticable to the IP/Ethernet net.
At present also do not have a kind of known, disclosed or announced patented technology, can when IP/Ethernet transmits the TDM/E1 signal on the net, be used for recovering synchronizing clock signals.
Summary of the invention:
Purpose of the present invention is exactly in order to overcome the above problems, and provides a kind of and can be applied on the connectionless asynchronous random length Packet Based Network, can adapt to the synchronised clock restoration methods of packet delay, drift and shake on a large scale.
For achieving the above object, the synchronised clock restoration methods of the present invention's proposition comprises the steps: 1) time tag of transmitting terminal generation reference clock and the transmission of packing; 2) transmitting terminal produces synchronous remaining time of the label of professional clock, and packing sends; 3) after receiving end receives above-mentioned two kinds of timescale data bags, unpack the extraction clock information; 4) the reference clock time tag that extracts is carried out self-adaptation clock and adjust computing, and utilize the adjustment signal to recover the synchronous base clock; 5) replace the reference net clock with the synchronous base clock that recovers, utilize professional clock synchronous remaining time of the label that extracts, carry out synchronous residual time mark computing, recover the professional synchronised clock that receives.
The synchronised clock recovery system that the present invention proposes comprises high accuracy crystal oscillator, reference clock markers processing module, the synchronous residual time mark processing module of professional clock, it is characterized in that: also comprise self-adaptation clock adjustment algorithm module and markers packing parse module; Described high accuracy crystal oscillator links to each other with self-adaptation clock adjustment algorithm module with reference clock markers processing module; Reference clock markers processing module links to each other with high accuracy crystal oscillator, the synchronous residual time mark processing module of professional clock, markers packing parse module respectively; Markers packing parse module also links to each other with the synchronous residual time mark processing module of professional clock, self-adaptation clock adjustment algorithm module respectively.
Owing to adopted above scheme, the present invention is by increasing self-adaptation clock adjustment algorithm module, cooperate reference time scale processing module and high accuracy crystal oscillator, recover a synchronous base clock earlier, with the public network clock in this alternative ATM system, thereby just can the synchronous residual time mark method SRTS of adopting by reference, recover the synchronous service clock.The present invention can transmit the TDM real time business on the IP/Ethernet network; can realize TDMoIP/EloEthernet; realize the real fusion of traditional Circuit Service and Packet Service at Access Network; the IP network that makes current cheapness is Circuit Services such as voice-over, leased line, video conferencing simultaneously; reduce operation cost, protected the investment of user's existing equipment.This invention is merged the crucial effect of playing for the TDM+IP that realizes Access Network and metropolitan area network, and it is the core technology of the low-cost TDMoIP of realization, can be widely used in the service integration and the upgrading of IP Access Network.
Description of drawings:
Fig. 1 is a schematic diagram of the present invention.
Fig. 2 is an embodiment of the invention schematic diagram.
Fig. 3 is a packing partial logic block diagram.
Fig. 4 unpacks the partial logic block diagram.
Embodiment:
Also the present invention is described in further detail in conjunction with the accompanying drawings below by specific embodiment.
Synchronised clock restoration methods of the present invention can illustrate that it comprises five modules with the technical scheme of Fig. 1: high accuracy crystal oscillator a, MCU self-adaptation clock adjustment algorithm module b, reference clock markers processing module c, the synchronous residual time mark processing module of professional clock d, markers packetization/depacketization module e.Be respectively described below:
A, be arranged at the high-precision crystal oscillator a on system's terminal device,, and give MCU self-adaptation clock adjustment algorithm module b and reference clock markers processing module c and carry out markers and handle as the reference data clock of local terminal.It handles the reference net clock of back as the synchronous residual time mark method of the synchronous residual time mark processing module of professional clock d through reference clock markers processing module c.
B, MCU self-adaptation clock adjustment algorithm module: by the reference clock markers is filtered and statistical average, extract the frequency error of local high accuracy crystal oscillator and far-end high accuracy crystal oscillator, control signal is adjusted in output, gives the digital phase-locked loop (DPLL) of (c) and adjusts.This module is realized by the software of MCU single-chip microcomputer.Its implementation can have multiple, for example:
Receiving terminal is put into a buffering area with the data of receiving, the speed that data enter this buffering area depends on the clock frequency of transmitting terminal.Receiving terminal reads the data in the buffering area and the full situation of the data that receive in the test constantly buffering area with certain clock frequency.When the data loading illustrates local clock faster than the transmitting terminal tranmitting data register in limited time near the following of buffering area, therefore should reduce the local clock frequency; Prescribe a time limit near going up of buffering area when the data loading, illustrate that local clock is lower than the transmitting terminal tranmitting data register, therefore should increase the local clock frequency.Like this, adjusting the receive clock frequency by the data that keep receiving at the middle capacity of data buffer zone makes it near the tranmitting data register frequency.
C, reference clock markers processing module: core is a narrow-band digital phase-locked loop (DPLL), receive the adjustment pulse of MCU software module output, carry out the meticulous adjustment of reference clock frequency and phase place, obtain a high precision reference clock (frequency error less than 1ppm) synchronous with far-end.Digital phase-locked loop (DPLL) is a kind of device that can export clock frequency according to the digital signal adjustment of being given.
D, the synchronous residual time mark processing module of professional clock: this module is finished the synchronous of local service clock and far-end business clock, basic skills is similar to the synchronous residual time mark method (SRTS) of atm network, and the different this locality/synchronous base clocks that just utilize obtain synchronous residual time mark as reference net clock.
E, markers packetization/depacketization module: the markers of the markers of reference clock and professional clock is packaged into the IP/UDP bag sends and receive.See Fig. 3 and Fig. 4 for details.
The software of native system mainly is in MCU self-adaptation clock adjustment algorithm module b, comprises three modules: 1. markers acquisition filter; 2. statistical computation mean value; 3. generate and adjust signal.Collection is actually the collection markers; Statistical computation mean value is to need a time interval because adjust DPLL, the markers of this section of statistics in the time in this time interval; The adjustment signal is exactly the voltage by the VCXO of adjusting DPLL, controls its clock output frequency then.
Its processing procedure is as follows:
1, the local side time tag that produces reference clock by (c) is given (e) and is carried out the markers packing and send; Simultaneously, produce synchronous remaining time of the label of professional clock, deliver (e) and carry out the markers packing and send, finally all mail to far-end as the IP bag system of delivering that contains clock information by (d).
2, after (e) of far-end receives two kinds of markers IP bags of local side, unpack the extraction clock information.Wherein reference clock receives markers and is sent to (b) and carries out self-adaptation clock and adjust computing, and sends the digital phase-locked loop (DPLL) of adjusting signal controlling (c) back to, to recover the synchronous base clock.
3, (d) utilizes synchronous base clock that (c) recover and the professional clock of (e) sending here to receive markers, carries out synchronous residual time mark computing, and controls its DPLL digital phase-locked loop and recover the professional synchronised clock that receives.
4 and, in order to carry out meticulous two way phase adjustment, obtain stable synchronous receive clock at receiving terminal, the synchronised clock that receiving end recovers produces the receiving end markers again, sends local side back to; Local side carries out markers computing and processing once more, obtains further adjustment information and sends receiving end back to.
Fig. 2 is a kind of full-service Ethernet switch schematic diagram with E1 circuit emulation service interface, and it is the Ethernet switch of a kind of E1 of having circuit switching and transfer function.Just adopted method of the present invention on its 8E1 circuit simulation card.In instance graph 2, self-adaptation clock adjustment algorithm module (b) is made up of a slice 51 series monolithic W78LE58P and peripheral circuit, except the self-adaptation clock adjustment algorithm functions of modules of finishing native system, also need finish other control and the management function of 8E1 circuit simulation card.High accuracy crystal oscillator (a) is one and has temperature-compensating and the high high-precision crystal oscillator of stability in short-term.Reference clock markers processing module (c), the synchronous residual time mark processing module of professional clock (d), markers packetization/depacketization module (e) and (c) two digital phase-locked loops (DPLL) in (d) are all finished with a slice FPGA gate array chip XC2S300E.Certainly it also will finish other artificial circuit function of artificial card.
The equipment of this example is owing to adopted method of the present invention, thereby have in Access Network cheaply with a plurality of E1 real time business and IP Ethernet service unifiedly insert, the ability of exchange, transmission, can in the IP of cheapness Access Network, realize TDMoIP, EloEthernet, realize that the unified of broadband, narrow band service inserts.
In sum, the present invention adopts a kind of dual two-way markers processing, control and phase-locked loop systems: with a kind of self-adaptation clock adjustment algorithm of uniqueness, carry out the reference data clock recovery earlier; Utilize the reference clock and the synchronous residual time mark statistic algorithm that recover again, finish service clock recovery and phase place adjustment; Finally carry out the two way phase adjustment and recover accurate synchronous service clock.
Method of the present invention can be applicable to transmit the clock recovery of TDM business on the IP/Ethernet network, be TDMoIP/TDMoEthernet, comprise: have full-service Ethernet switch, the ether multiplexer (TDMoIP gateway) of EloIP emulation interface, the product of IP-based full-service optical transceiver types such as (full-service light MODEM).The present invention is merged the crucial effect of playing for the TDM+IP that realizes Access Network and metropolitan area network, and it is the core technology of the low-cost TDMoIP of realization, can be widely used in the service integration and the upgrading of IP Access Network.
Claims (6)
1, the synchronised clock restoration methods in a kind of Packet Based Network is characterized in that comprising the steps:
1) transmitting terminal produces the time tag and the packing transmission of reference clock;
2) transmitting terminal produces synchronous remaining time of the label of professional clock, and packing sends;
3) after receiving end receives above-mentioned two kinds of timescale data bags, unpack the extraction clock information;
4) the reference clock time tag that extracts is carried out self-adaptation clock and adjust computing, and utilize the adjustment signal to recover the synchronous base clock;
5) replace the reference net clock with the synchronous base clock that recovers, utilize professional clock synchronous remaining time of the label that extracts, carry out synchronous residual time mark computing, recover the professional synchronised clock that receives.
2, the synchronised clock restoration methods in the Packet Based Network as claimed in claim 1, it is characterized in that: wherein the method for utilizing the adjustment signal to recover the synchronous base clock in the step 4) is that the adjustment signal is delivered to digital phase-locked loop (DPLL), and digital phase-locked loop (DPLL) is controlled to recover the synchronous base clock; Wherein recovering the professional method that receives synchronised clock in the step 5) is that the signal after the computing is delivered to digital phase-locked loop (DPLL), utilizes digital phase-locked loop (DPLL) to recover the professional synchronised clock that receives.
3, the synchronised clock restoration methods in the Packet Based Network as claimed in claim 1 or 2, it is characterized in that: wherein self-adaptation clock adjustment computing comprises the steps: by the reference clock markers of extracting is filtered and statistical average in the step 4), extract the frequency error of local high accuracy crystal oscillator and far-end high accuracy crystal oscillator, control signal is adjusted in output.
4, the synchronised clock restoration methods in the Packet Based Network as claimed in claim 1 or 2, it is characterized in that: wherein self-adaptation clock is adjusted computing and is comprised the steps: that receiving terminal puts into a buffering area with the data of receiving in the step 4), and the speed that data enter this buffering area depends on the clock frequency of transmitting terminal; Receiving terminal reads the data in the buffering area and the full situation of the data that receive in the test constantly buffering area with certain clock frequency; When the data loading illustrates local clock faster than the transmitting terminal tranmitting data register in limited time near the following of buffering area, therefore should reduce the local clock frequency; Prescribe a time limit near going up of buffering area when the data loading, illustrate that local clock is lower than the transmitting terminal tranmitting data register, therefore should increase the local clock frequency; Like this, adjusting the receive clock frequency by the data that keep receiving at the middle capacity of data buffer zone makes it near the tranmitting data register frequency.
5, the synchronised clock restoration methods in the Packet Based Network as claimed in claim 1 or 2 is characterized in that also comprising the steps:
6) synchronised clock that recovers of receiving end produces the receiving end markers again, sends original sender back to; Original sender carries out markers computing and processing once more, obtains further adjustment information and sends receiving end back to; Thereby can carry out meticulous two way phase adjustment at receiving terminal, obtain stable synchronous receive clock.
6, the synchronised clock restoration methods in the Packet Based Network as claimed in claim 1 or 2 is characterized in that: step 1), 2 wherein) in the packet that sends of packing be the IP/UDP bag.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CNB031468764A CN1262092C (en) | 2003-09-16 | 2003-09-16 | Method and system for synchronizing clock resuming in packet network |
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| Application Number | Priority Date | Filing Date | Title |
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| CNB031468764A CN1262092C (en) | 2003-09-16 | 2003-09-16 | Method and system for synchronizing clock resuming in packet network |
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| CN1525704A CN1525704A (en) | 2004-09-01 |
| CN1262092C true CN1262092C (en) | 2006-06-28 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100542083C (en) * | 2005-08-24 | 2009-09-16 | 华为技术有限公司 | Realize the method and system of Network Synchronization by packet network |
| ES2425237T3 (en) * | 2007-09-21 | 2013-10-14 | Telefonaktiebolaget Lm Ericsson (Publ) | Reverse timestamp method and network node for clock recovery |
| CN101453316B (en) * | 2007-11-30 | 2011-04-13 | 华为技术有限公司 | Time information synchronization system, method and related apparatus |
| CN101174912B (en) * | 2007-12-05 | 2012-07-25 | 武汉烽火网络有限责任公司 | Self-adapting clock method based on time stamp facing Ethernet circuit simulation service |
| GB0908884D0 (en) * | 2009-05-22 | 2009-07-01 | Zarlink Semiconductor Inc | Time recovery over packet networks |
| CN101626346B (en) * | 2009-08-03 | 2011-12-07 | 中兴通讯股份有限公司 | Method and device for restoring self-adaptive clock |
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