CN1258966A - Frame synchronizing virtual channel shunt with adaptive characteristics - Google Patents
Frame synchronizing virtual channel shunt with adaptive characteristics Download PDFInfo
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- CN1258966A CN1258966A CN 98111798 CN98111798A CN1258966A CN 1258966 A CN1258966 A CN 1258966A CN 98111798 CN98111798 CN 98111798 CN 98111798 A CN98111798 A CN 98111798A CN 1258966 A CN1258966 A CN 1258966A
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Abstract
Frame synchronizing virtual channel shunt for shunting the high-speed remote measurement base band signal of space flyer includes frame synchronizing fault-tolerant control circuit, phase lock controller, frame protector circuit, descrambling circuit, frame shunt circuit, synchronous protecting window controller an error correcting circuit. It can shunt the down stream data flow comprising data from different information sources of space flyer and complying with relevant international standard into high-speed, middle-speed and low-speed data. The present invention can realize time-dividing transmission of several kinds of data.
Description
The present invention relates to a kind of satellite communication signal receiving device, particularly relate to a kind of synchronous in real time the frame synchronizing virtual channel shunt along separate routes of spacecraft HRT high-rate telemetry baseband signal (through the digital signal of HF receiver receiving demodulation recovery) with adaptive characteristic.It can will be made of various information source on the spacecraft, the downstream data flow that meets the Aerospace Data Systems standard recommendation book CCSDS701.0-b-2 of international space data system Advisory Board (CCSDS) " senior to rail system, network and data link " standard in real time along separate routes be the data respectively a tunnel of high speed, middling speed, low speed.Time division multiplexing transmits several data on the same physical channel thereby be implemented in, as image, voice, scientific exploration and scientific experiment data, flight engineering parameter etc.
In digital communication by satellite, in order to enlarge transmission capacity, improve efficiency of transmission, usually adopt the digital signal of several physics information sources is inserted frame synchronizing signal by certain standard, become one road high-speed digital signal by the multiplexer multiple connection, will be decomposed into original branch road digital signal to the digital signal of making a start with coupler in receiving end.For the frame state that the makes coupler frame state unanimity with respect to multiplexer, coupler must be caught the frame synchronization state of multiplexer, and maintenance and locking phase relation.The enforcement tap that coupler could be correct under the condition of phase locking.Because frame swynchronization code is not subjected to the protection of error correction coding, therefore when the channel signal to noise ratio is low, frame synchronization will be the bottleneck of whole communication system.Therefore in satellite digital communication, the identification of frame synchronization and judgement are most important parts in the synchronous drop set.In realizing engineering design, the problem that it relates to is more, and is also bigger to whole drop set performance impact.
Because satellite communication is subjected to the influence of the attitude of satellite, orbital position, noise and interference; the signal to noise ratio of received signal may change at any time; adopt the coupler of prior art when catching the frame synchronization state of multiplexer, only to have fixing frame forward protect and rearward protect time; when poor signal quality, be easy to generate the frame synchronization step-out, cause losing of one piece of data.Do not adopt frame synchronization window protection false (coincidence of data and synchronous code) synchronously may occur or make the data dislocation cause the frame synchronization step-out because the bit synchronization clock is subjected to disturb.
As the technology that the present digital communication frame synchronization of " microwave and satellite communication " refined " implementation of frame synchronization in the digital communication network " introduction of writing of interim Lv Zhi in 1977 the 3rd, adopts.
Purpose of the present invention is exactly the deficiency that overcomes prior art, designs a kind of frame synchronizing channel coupler that input signal is had adaptation function.It can be fault-tolerant in synchronous code, aspect frame the place ahead and rear synchronous protection, the protection of frame synchronization window, look the power of input signal and adjust tolerance limit within the specific limits automatically.False synchronia can be do not occurred, loss of data can be do not made yet.Very wide adaptability is arranged on receiving velocity.
The object of the present invention is achieved like this:
This frame synchronizing virtual channel shunt comprises the fault-tolerant control circuit 1 of frame synchronization, phase-locked controller 2, frame protective circuit 3, scrambling code decoding circuit 4, frame shunt circuit 5, synchronous protection window controller 6 and error correction circuit 7.Wherein:
Behind signal incoming frame synchronous fault-tolerant control circuit 1, the fault-tolerant control circuit 1 of this frame synchronization is sought synchronous mark, and synchronous mark is inputed to phase-locked controller 2, adjusts pll phase.The output of phase-locked controller 2 is respectively frame protective circuit 3, scrambling code decoding circuit 4, frame shunt circuit 5 and synchronous protection window controller 6 control timing is provided as the timing sequencer of the fault-tolerant control circuit 1 of frame synchronization.The synchronous mark of fault-tolerant control circuit 1 output of frame synchronization is recorded in the frame protective circuit 3, opens control gate when satisfying frame synchronization condition time frame protective circuit 3, and signal inputs to scrambling code decoding circuit 4.This signal generates high speed, middling speed and low speed data successively after scrambling code decoding circuit 4, error correction circuit 7, frame shunt circuit 5.Synchronous protection window controller 6 output protection scopes are to the fault-tolerant control circuit 1 of frame synchronization, control frame synchronous fault-tolerant working range after frame synchronization.
The setting of fault-tolerant when this frame synchronizing virtual channel shunt also has one parameter interface 8 is set is used for the non-self-adapting mode state, guard time and synchronous window width.When not needing the adaptive model state,, parameter interface 8 to the fault-tolerant control circuit 1 of frame synchronization, frame protective circuit 3, synchronous protection window controller 6 the fault-tolerant figure place of frame synchronization, frame guard time and frame synchronization protection window width parameter are set respectively by being set.
The present invention not only has sign indicating number and is derived from adaptation synchronous fault-tolerant technology, and has the frame synchronization window protection of frame forward protect, rearward protect adaptive control and variable range.Therefore the present invention can adjust tolerance limit automatically according to the quality of received signal, false synchronia can not occur, also can not make loss of data.Very wide adaptability is arranged on receiving velocity, can finish according to the CCSDS standard the descending various high-speed datas of spacecraft are carried out the equipment that real-time tap is handled.And owing to adopted scale programmable logic device FPGA to realize real time implementation with smaller volume.
Accompanying drawing 1 is a structured flowchart of the present invention;
Accompanying drawing 2 is message processing flow figure of the present invention;
Accompanying drawing 3 is the forward protect and the rearward protect schematic diagram of frame;
Accompanying drawing 4 is the schematic diagram of frame synchronization protection window protection.
Below in conjunction with accompanying drawing embodiments of the invention are described.
When device runs on the non-self-adapting control model, by parameter interface 8 is set the fault-tolerant figure place of frame synchronization is set, arbitrary value in fault-tolerant 0 to 3 can be set.Frame guard time 2 to 5 frames can be set.Be provided with frame synchronization protection window width ± 3bits or ± 7bits.
Accompanying drawing 2 is message processing flow figure of the present invention, now each step is described further.1, frame synchronization
The telemetered signal that aerospace craft is descending generates through the receiver receiving demodulation and to meet the CCSDS standard, has synchronous accompanying clock, and serial is non-returns " 0 " digital baseband signal.This clock and serial data are as the input signal of this frame synchronizing virtual channel shunt.The rising edge of its clock is the variation edge of data.Serial code speed 0-15MHz.
Frame synchronization is to utilize the autocorrelation of synchronous code (1ACFFC1D) to determine the sync bit of frame.In the initial moment of Data Receiving, frame synchronization is sought frame swynchronization code in data flow.After finding first group of synchronous code, skip a frame length and reaffirm frame swynchronization code.Set up synchronous regime (by capturing synchronous foundation first) through after the continuous n frame acknowledgment synchronous code the rearward protect time.M LOF synchronous code then enters desynchronizing state continuously in synchronous regime, cries the forward protect time during this period of time, as shown in Figure 3.Consider the difference of quality of the data flow transmission of reception, therefore protect frame number to be designed to have adaptivity.When being consecutively detected frame swynchronization code, will gradually reduce the place ahead and rearward protect time by FEEDBACK CONTROL, when reducing to 2 frames, will keep, no longer reduce guard time.Surpass fault-tolerant scope in case certain frame swynchronization code mistake figure place occurs in reception process, this moment, system did not enter desynchronizing state because the protection of forward protect time is arranged.The threshold value of guard time will increase under the effect of feedback.So possibility that has reduced to enter desynchronizing state.Have only continuous 5 frames of working as not detect frame swynchronization code system step-out.Need be consecutively detected 5 frame swynchronization codes synchronously once more.If do not wish to use adaptive guard control then can the parameter interface is provided with the forward protect time and the rearward protect time is 2 frames, 3 frames, 4 frames or 5 frames by being provided with.
After frame synchronization is set up, slide and come into force in anti-position.Sync bit ± t bits at each frame offers confirmation of synchronization slip protection window with interior, in case occur false (coincidence of data and synchronous code) synchronously in the stop signal or disturb the dislocation that causes data flow owing to the bit synchronization clock exists.
The size of seeking the district in design synchronously is subjected to the relevant control of adaptive frame protection.Confirmation of synchronization slip protection window was ± 7 bits when sign indicating number source signal to noise ratio was low, as shown in Figure 4.Confirmation of synchronization slip protection window was ± 3 bits when sign indicating number source signal to noise ratio was high.Also can not be subjected to FEEDBACK CONTROL, by circuit interface be provided with selection ± 3 bits or ± 7 bits.
The fault-tolerant figure place of 36 frame swynchronization codes can change from the 0-3 position, depends on yard height of source signal to noise ratio, and fault-tolerant position was many when sign indicating number source signal to noise ratio was low, and fault-tolerant position was few when sign indicating number source signal to noise ratio was high.Also can not be subjected to FEEDBACK CONTROL, be provided with by circuit interface and determine to select.The fault-tolerant position of 0-3bits.When signal quality is relatively good fault-tolerant can obtain a little bit smaller, otherwise fault-tolerant can obtaining more greatly.2, descrambling code
In order to prevent to occur a plurality of continuously " 1 " or a plurality of " 0 " in the data, cause continuous high level of nonreturn to zero code or low level, cause difficulty for the bit synchronization Clock Extraction.So adopt pseudo noise code to the data scrambling at the information source end.Therefore need to obtain original data stream by descrambling code.Circuit design is made of pseudo-noise code generator and XOR descrambling circuit, and pseudo-noise code generator is synchronoused working with source end scrambling pseudo-noise code generator under the effect of frame synchronization and bit clock.To guarantee accurate descrambling.
Scrambling code decoding circuit is started working after signal Synchronization.252 bytes except that synchronous code 4 bytes in 256 bytes of every frame (2048bits) are removed scrambler, are parallel data with these 252 bytes of serial data conversions, to satisfy the input interface requirement of R-S decoding circuit again.Each frame start position scrambling code decoding circuit resets once, to guarantee the synchronism of descrambling and scrambling.3, R-S error correction
In communication process, may be subjected to the data that various interference cause receiving and have error code, therefore in channel, adopt the R-S error correction coding to correct owing to disturb the error code that causes.Selected special-purpose R-S codec chip in the design for use.This chip can be decoded about the suggestion of the Reed-Solomon coding in the telemeter channel coding by CCSDS to initial data.Can correct any 16 mistakes in per 255 bytes.This chip is RS (255,233) encoding and decoding.Virtual filling capacity is 1 or 3 byte, and data are 8 parallel-by-bit modes.Control signal comprises: data input, data output, byte clock, code block are synchronously, data enable, bypass mode select, virtually be filled with, input error is overflowed, the number indication or the like of correcting a mistake.3. frame along separate routes
The present invention can realize 4 pseudo channels are carried out shunt.Comprise high-speed video channel, middling speed channel, low speed science data channel and fill channel.Pseudo channel is with the data after descrambling and error correction along separate routes, and by the leading position of transmission frame that frame synchronization is determined, interpretation virtual channel identifier is wherein pressed identifier to pseudo channel along separate routes.
Wherein the high-speed video channel data is 32 bit synchronization sign indicating numbers with the front among the communication transmission frame 2048bits, the leading head of 48 virtual channel data unit units (VCDU) is removed, RS EDC error detect correction sign indicating number with 32 * 8=256bits of frame back removes again, and splicing reverts to original bit stream video data stream.Employing has the serial data stream output of accompanying clock, for the Video processing computer vision signal is done further processing.
Padding data is because of not comprising useful information, and whole transmission frame is discarded, not to any interface output.
It also is with synchronous code that low speed science data channel transmits frame, leading and the removal of RS EDC error detect correction sign indicating number of virtual channel data unit unit (VCDU), and splicing reverts to original low speed source packet data streams, inputs to Data Buffer Memory through string and conversion generation 8 parallel-by-bit data.For easily data being imported computer, designed PC computer XT bus inserted card.The output of Data Buffer Memory is imported computer by the XT bus with data.Because the data buffer zone of 8K byte is arranged, computer and the asynchronous system of splitter employing synchronously swap data have alleviated requirement and the pressure of data acquisition to computer real-time.4, low speed data computer real-time decomposition, Data Post
Low speed data signal information transmitted comprises four kinds of science data source bags: (1) intelligence is far put science data source, unit bag: (2) high-speed multiplexer engineering parameter source bag; (3) bus control unit engineering parameter source bag; (4) by simply far putting the science data bag that the unit generates.Enter the low speed data of computer, will differentiate 4 kinds of data source bags according to the sign of the bag in the packet header, be stored in respectively in 4 files, simultaneously bag or the wrong bag data that can not differentiate are stored in the 5th file by computer software filtered source bag packet header.On the display of computer, can not show following active bag data simultaneously, therefore show different science data source bag data (showing in real time) respectively with drop-down menu, pop-up window mode.For analog quantity with time-voltage coordinate curve or histogram mode show.For the low-speed digital amount then receiving terminal will show its numerical value in the fixed position of display with forms mode, each of form all has the Chinese note name and the unit of display.The high-speed figure amount also adopts scrolling windows to show.For switching value then adopt variable color light/dark mode shows.
The frame input of low speed data along separate routes is the also line buffer memory of PC-XT bus by a 8K byte, enters computer through bus slot.The half-full signal of buffer will interrupt computer as interrupt source.The resident interrupt service routine that assembler language is arranged of the bottom of computer is had no progeny in each response and is taken about 4K data the buffer away from the parallel port, writes the 200K buffer circle in the calculator memory.This buffer circle is opened up in program initialization.What the reading of buffer circle referred to clock system and data reads as C language function.The demonstration deposit on upper strata and source bag identification, shunt program are write as by the C language.Can guarantee that through soft two-stage asynchronous buffer really up to the mark the data acquisition of computer do not lose data.
The also engineering parameter of Acquisition Circuit and decoding of computer in receiving course, state such as synchronous.An accepting state subitem will be set under the main menu of computer, and display synchronization, losing lock, Various types of data bag receive counter value, wrong frame ratio, R-S error correction result, error correction is overflowed and the front and back protection frame number during current circuit working, sliding window size, fault-tolerant figure place or the like.5. the realization of system
The equipment that the present invention has realized comprises that frame synchronizing virtual channel shunt main frame and PC bus advance the machine card, and it and computer have constituted spacecraft telemetry intelligence (TELINT) treatment system jointly.Owing to adopted scale programmable logic device FPGA to realize intellectuality and real time implementation, had the advantages that volume is little, function is strong.The speed of input serial data stream can reach 15Mbps.Ratio adopts the superiority of software synchronization to be can synchronous in real time and shunt under high bit rate.Because all circuit are by the accompanying clock control of input.Therefore serial received rate-compatible can work between 0-15Mbps on any speed.
The PC bus is advanced the machine card and is mainly formed its core circuit by the FPGA of 3000 of a slices.It goes back the accepting state of monitoring channel coupler except satisfying computer interface function.The engineering parameter that it exports computer to comprises: high speed, middling speed, low speed, the infilled frame that receives counted respectively.The number of times of record step-out.Number of times is overflowed in the error correction of record R-S error correction coding.Provide step-out to report to the police and error correcting code error correction overflow alarm.
The output of apparatus of the present invention comprises high speed, medium speed data and the clock of serial.The clock and the data of output all have long line driving force.Low speed data and parameter are output as PC XT bus.In addition the lock-out state of outbalance and error correcting code error correction are overflowed on device and be provided with indicator light.
The FPGA internal circuit has all adopted the synchronous logic design, to improve operating rate.For preventing the competition of taking a risk, taked safeguard measure in the design.But because the device that the circuit more complicated is used is a lot, many indoor design modules have been passed through tens of grades of doors from being input to output, hundreds of logical blocks have been used, therefore the output of module lags behind input signal, may occur competition between the situation lower module of the public clock of each module.Therefore the output of all modules has all designed the phase alignment circuit with common clock, to guarantee the operate as normal of circuit.
Claims (4)
1, a kind of frame synchronizing virtual channel shunt; it is characterized in that: this frame synchronizing virtual channel shunt comprises the fault-tolerant control circuit of frame synchronization (1), phase-locked controller (2), frame protective circuit (3), scrambling code decoding circuit (4), frame shunt circuit (5), synchronous protection window controller (6) and error correction circuit (7), wherein:
Behind signal incoming frame synchronous fault-tolerant control circuit (1); the fault-tolerant control circuit of this frame synchronization (1) is sought synchronous mark; synchronous mark is inputed to phase-locked controller (2); adjust pll phase; the output of phase-locked controller (2) is as the timing sequencer of the fault-tolerant control circuit of frame synchronization (1); be respectively frame protective circuit (3); scrambling code decoding circuit (4); frame shunt circuit (5) and synchronous protection window controller (6) provide control timing; the synchronous mark of the fault-tolerant control circuit of frame synchronization (1) output is recorded in the frame protective circuit (3); open control gate when satisfying frame synchronization condition time frame protective circuit (3); signal inputs to scrambling code decoding circuit (4), and this signal is successively through scrambling code decoding circuit (4); error correction circuit (7); frame shunt circuit (5) back generates at a high speed; middling speed and low speed data.Synchronous protection window controller (6) output protection scope is to the fault-tolerant control circuit of frame synchronization (1) after frame synchronization, control frame synchronous fault-tolerant working range.
2, a kind of frame synchronizing virtual channel shunt as claimed in claim 1; it is characterized in that: when not needing the adaptive model state, to the fault-tolerant control circuit of frame synchronization (1), frame protective circuit (3), synchronous protection window controller (6) the fault-tolerant figure place of frame synchronization, frame guard time and frame synchronization protection window width parameter are set respectively by parameter interface (8) is set.
3, a kind of frame synchronizing virtual channel shunt as claimed in claim 1 is characterized in that: it comprises that also one connects the low speed data signal and this signal carried out the engineering parameter low speed data interface (9) of the computer real-time subpackage treatment system of demonstration in real time.
4, a kind of frame synchronizing virtual channel shunt as claimed in claim 1 is characterized in that:.The fault-tolerant control circuit of the frame synchronization that this coupler comprises (1), phase-locked controller (2), frame protective circuit (3), scrambling code decoding circuit (4), frame shunt circuit (5), synchronous protection window controller (6) utilize a slice scale programmable logic device FPGA to realize.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 98111798 CN1096761C (en) | 1998-12-29 | 1998-12-29 | Frame synchronizing virtual channel shunt with adaptive characteristics |
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| CN 98111798 CN1096761C (en) | 1998-12-29 | 1998-12-29 | Frame synchronizing virtual channel shunt with adaptive characteristics |
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| CN1096761C CN1096761C (en) | 2002-12-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461960A (en) * | 2014-11-18 | 2015-03-25 | 中国电子科技集团公司第十研究所 | Telemetry frame data path selection processing method for matrix type telemetry frame |
| CN105245313A (en) * | 2015-10-18 | 2016-01-13 | 中国电子科技集团公司第十研究所 | Multi-load data dynamic multiplexing method of unmanned aerial vehicle |
-
1998
- 1998-12-29 CN CN 98111798 patent/CN1096761C/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104461960A (en) * | 2014-11-18 | 2015-03-25 | 中国电子科技集团公司第十研究所 | Telemetry frame data path selection processing method for matrix type telemetry frame |
| CN104461960B (en) * | 2014-11-18 | 2017-04-05 | 中国电子科技集团公司第十研究所 | Matrix type telemetry frame chooses the processing method of road remote measurement frame data |
| CN105245313A (en) * | 2015-10-18 | 2016-01-13 | 中国电子科技集团公司第十研究所 | Multi-load data dynamic multiplexing method of unmanned aerial vehicle |
| CN105245313B (en) * | 2015-10-18 | 2018-05-04 | 中国电子科技集团公司第十研究所 | Unmanned plane multi-load data dynamic multiplexing method |
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| CN1096761C (en) | 2002-12-18 |
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