CN1256768C - Method for manufacturing silicon nitride ROM - Google Patents
Method for manufacturing silicon nitride ROM Download PDFInfo
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- CN1256768C CN1256768C CN 02140799 CN02140799A CN1256768C CN 1256768 C CN1256768 C CN 1256768C CN 02140799 CN02140799 CN 02140799 CN 02140799 A CN02140799 A CN 02140799A CN 1256768 C CN1256768 C CN 1256768C
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Abstract
The present invention discloses a method for manufacturing a silicon nitride ROM, which comprises the following steps: an adulterating compound crystal silicon layer is formed on a substrate, and then, a patterned cover curtain layer is formed on the adulterating compound crystal silicon layer; the adulterating compound crystal silicon layer is defined by the patterned cover curtain layer to become a compound crystal silicon line layer, and part of the substrate is exposed; subsequently, heat processing is implemented in order to expose an oxide layer formed on the exposed substrate and the side wall of the compound crystal silicon line layer, wherein dopant in the compound crystal silicon line layer can be diffused into the substrate to form a source/leakage pole and form a position line with the compound crystal silicon line layer; next, the patterned cover curtain layer is removed in order to expose the top of the position line, and then, a process of automatically aligning silicified metal is carried out in order to form an automatically-aligning silicified metal layer; afterwards, the oxide layer is removed, and a plurality of character lines are formed on a silicon nitride stacking layer.
Description
Technical field
The present invention relates to a kind of read-only memory manufacture method of (read only memory is called for short ROM), and be particularly related to the manufacture method of a kind of silicon nitride ROM (nitride ROM).
Background technology
The practice of non-volatile ROM is to form one earlier to catch layer (trappinglayer) in substrate, the material of catching layer is by silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide, abbreviation ONO) nesting structural embedded control (stacked structure) that composite bed constituted is called silicon nitride ROM with this kind material as the read-only memory of catching layer.Then, on this silicon oxide/silicon nitride/silicon oxide (ONO) layer, form the compound crystal silicon grid again, promptly as character line (word line), at last in silicon oxide/silicon nitride/silicon oxide (ONO) layer substrate on two sides formation source/drain electrode (source/drain) as embedded type bit line (buried bit line).
Yet, when memory element constantly develops down towards miniaturization, the length of grid also can be reduced thereupon, and utilize the formed embedded type bit line of ion implantation technology usually, make admixture (dopant) diffusion wherein easily because of heat treatment, cause the reduction of element efficient channel, and short channel effect (short channel effect) takes place.When element after miniaturization development, the problems referred to above will be more serious.Therefore, present way is to utilize pocket to implant the growth requirement that (pocket implant) and shallow joint (shallowjunction) or the technology of super shallow joint (ultra shallow junction) cooperate miniaturization.Yet, these shallow joints or the resistance of the embedded type bit line of super shallow joint is often quite high, and cause memory element in operational difficulty.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of silicon nitride ROM, significantly to reduce the resistance of bit line.
A further object of the present invention provides a kind of manufacture method of silicon nitride ROM, can increase the conductivity (conductivity) of bit line.
Another object of the present invention provides a kind of manufacture method of silicon nitride ROM, can prevent that the admixture of embedded type bit line from spreading the short channel effect that is caused because of heat treatment.
According to above-mentioned and other purpose, the present invention proposes a kind of manufacture method of silicon nitride ROM, be included in and form the doping compound crystal silicon layer (doped polysilicon layer) that contains admixture in the substrate, on the doping compound crystal silicon layer, form a patterning cover curtain layer (mask layer) again, and utilize the patterning cover curtain layer to define the doping compound crystal silicon layer, forming several doping compound crystal silicon line layers, and expose the part substrate.Subsequently, implement a heat treatment, to form layer of oxide layer on substrate that exposes and doping compound crystal silicon line layer sidewall, the admixture in the compound crystal silicon line layer that wherein mixes can be diffused into substrate and become a source/drain electrode, comprises the bit line of compound crystal silicon line layer and source/drain electrode so as to formation.Then, remove the patterning cover curtain layer,, carry out one again and aim at metal silicide process (self-aligned silicide process) voluntarily, aim at metal silicide layer voluntarily to form at the bit line top to expose the top of bit line.Remove oxide layer then, and in substrate, form a silicon nitride stack layer and several character lines.
The present invention proposes a kind of manufacture method of silicon nitride ROM, also comprises: a substrate is provided, forms a plurality of conductor lines layers that contain an admixture in this substrate, wherein those conductor lines layer tops are formed with a cover curtain layer.Implement a heat treatment, on this substrate that exposes and those conductor lines layer sidewalls, forming an oxide layer, and make this dopant diffusion in those conductor lines layers in this substrate and form a source/drain electrode.Remove this cover curtain layer,, carry out one and aim at the metal silicide process voluntarily, aim at metal silicide layer voluntarily to form one at those conductor lines layer tops to expose the top of those conductor lines layers.Remove this oxide layer, formation one silicon nitride stack layer covers those conductor lines layers and aims at metal silicide layer voluntarily with this in this substrate, forms plurality of word lines in this substrate.
The present invention is by forming doping compound crystal silicon line layer and being formed at source/drain electrode under the compound crystal silicon line layer by heat treatment as the bit line of memory element, so can significantly reduce the resistance of bit line.And, owing to the source/drain electrode that diffuses to substrate from doping compound crystal silicon line layer belongs to super shallow joint, therefore can avoid the admixture of known embedded type bit line to spread the short channel effect that is caused because of heat treatment.In addition, the present invention not only has the bit line that comprises compound crystal silicon line layer and source/drain electrode, also forms one deck again at this bit line top and aims at metal silicide layer voluntarily, so can increase the conductivity of bit line.
Description of drawings
For purpose of the present invention, feature and advantage can be become apparent, conjunction with figs. hereinafter elaborates:
Figure 1A to Fig. 1 F is the manufacturing process profile of the silicon nitride ROM of a preferred embodiment of the present invention.
Figure acceptance of the bid note is respectively:
100: substrate
102,102a: doping compound crystal silicon layer
104: cover curtain layer
106: oxide layer
108: source/drain electrode
110: bit line
112: metal level
114: metal silicide layer
116: the silicon nitride stack layer
118: character line
Embodiment
In order to prevent silicon nitride ROM (nitride read only memory, be called for short NROM) because of the too high problem of shallow joint (shallow junction) resistance that miniaturization of components caused, the invention provides a kind of manufacture method of silicon nitride ROM.
Figure 1A to Fig. 1 F is the manufacturing process profile of the silicon nitride ROM of a preferred embodiment of the present invention.
Please refer to Figure 1A, in substrate 100, form the doping compound crystal silicon layer (doped polysilicon layer) 102 that contains admixture (dopant), form a patterning cover curtain layer (mask layer) 104 again on doping compound crystal silicon layer 102, wherein patterning cover curtain layer 104 for example is a silicon nitride layer.
Then, please refer to Figure 1B, utilize patterning cover curtain layer 104 definition doping compound crystal silicon layers 102, forming several doping compound crystal silicon line layers 102a, and expose part substrate 100.
Then, please refer to Fig. 1 C, implement heat treatment such as thermal oxidation process (thermal oxidationprocess), on substrate 100 that exposes and doping compound crystal silicon line layer 102a sidewall, to form layer of oxide layer 106, the admixture that wherein mixes among the compound crystal silicon line layer 102a can be diffused into substrate 100 and become a source/drain electrode 108, comprises the bit line 110 of compound crystal silicon line layer 102a and source/drain electrode 108 so as to formation.
Then, please refer to Fig. 1 D, remove patterning cover curtain layer 104, to expose the top of bit line 110.Subsequently, form layer of metal layer 112 and cover bit line 110 in substrate 100, wherein metal level 112 for example is cobalt/titanium (Co/Ti) layer or tungsten (W) layer.
Afterwards, please refer to Fig. 1 E, carry out one and aim at metal silicide process (self-alignedsilicide process) voluntarily, aim at metal silicide layer 114 voluntarily to form at bit line 110 tops, wherein aiming at the metal silicide process voluntarily mainly is to comprise carrying out a drawing process, so that doping compound crystal silicon line layer 102a and metal level 112 reactions remove the unreacted metal layer again, and the step of removal unreacted metal layer comprise wet etch process.
At last, please refer to Fig. 1 F, remove oxide layer 106, and in substrate 100, form a silicon nitride stack layer (stacked layer) 116, wherein the nesting structural embedded control that constituted of silicon nitride stack layer 116 can be silicon oxide/silicon nitride/silicon oxide, silica/silicon nitride/silicon nitride or silicon nitride/silicon nitride/silicon nitride.Then, on silicon nitride stack layer 116, form character line (word line) 118 again, the step that wherein forms character line 118 for example is to form a conductor layer earlier to cover bit line 110 in substrate 100, define conductor layer again with formation character line 118, and conductor layer can be a compound crystal silicon layer.
Therefore, feature of the present invention comprises:
1. the present invention is by forming doping compound crystal silicon line layer, and the source/drain electrode that utilizes heat treatment to form to be positioned under the compound crystal silicon line layer is as the bit line of memory element, so can significantly reduce the resistance of bit line.
2. the present invention is owing to dopant diffusion to the formed source of the substrate/drain electrode from doping compound crystal silicon line layer is to belong to a kind of super shallow joint (ultra shallow junction), therefore can avoid the admixture of known embedded type bit line (buried bit line) to spread the short channel effect that is caused (shortchannel effect) because of heat treatment.
3. the present invention not only has the bit line that comprises compound crystal silicon line layer and source/drain electrode, also forms one deck again at the bit line top and aims at metal silicide layer voluntarily, so can increase the conductivity (conductivity) of bit line.
Though the present invention is with preferred embodiment openly as above, so it is not in order to qualification the present invention, any personnel that are familiar with this technology, and without departing from the spirit and scope of the present invention, various changes and the retouching done all belong to protection scope of the present invention.
Claims (18)
1. the manufacture method of a silicon nitride ROM is characterized in that: comprising:
In a substrate, form a doping compound crystal silicon layer, wherein should have an admixture by the doping compound crystal silicon;
On this doping compound crystal silicon layer, form a patterning cover curtain layer;
Utilize this patterning cover curtain layer to define this doping compound crystal silicon layer, forming a plurality of doping compound crystal silicon line layers, and expose this substrate of part;
Implement a heat treatment, on the sidewall of this substrate that exposes and those doping compound crystal silicon line layers, to form an oxide layer, and make this dopant diffusion in this substrate, become a source/drain electrode, comprise a plurality of bit lines of this doping compound crystal silicon line layer and this source/drain electrode so as to formation;
Remove the cover curtain layer of this patterning, to expose the top of those bit lines;
Carry out one and aim at the metal silicide process voluntarily, aim at metal silicide layer voluntarily to form one at those bit line tops;
Remove this oxide layer;
In this substrate, form a silicon nitride stack layer;
In this substrate, form plurality of word lines.
2. the manufacture method of silicon nitride ROM according to claim 1 is characterized in that: carry out this step of aiming at the metal silicide process voluntarily and comprise:
In this substrate, form a metal level and cover those bit lines;
Carry out a drawing process, so that those doping compound crystal silicon line layers and the reaction of this metal level are aimed at metal silicide layer voluntarily and form this at those bit line tops;
Remove unreacted this metal level.
3. the manufacture method of silicon nitride ROM according to claim 2, it is characterized in that: this metal level comprises cobalt/titanium layer.
4. the manufacture method of silicon nitride ROM according to claim 2 is characterized in that: the step of removing unreacted this metal level comprises wet etch process.
5. the manufacture method of silicon nitride ROM according to claim 1, it is characterized in that: this heat treatment comprises thermal oxidation.
6. the manufacture method of silicon nitride ROM according to claim 1, it is characterized in that: this patterning cover curtain layer comprises silicon nitride layer.
7. the manufacture method of silicon nitride ROM according to claim 1, it is characterized in that: those character lines comprise compound crystal silicon layer.
8. the manufacture method of silicon nitride ROM according to claim 1 is characterized in that: the nesting structural embedded control that is constituted at this silicon nitride stack layer comprise silicon oxide/silicon nitride/silicon oxide, silica/silicon nitride/silicon nitride and silicon nitride/silicon nitride/silicon nitride one of them.
9. the manufacture method of a silicon nitride ROM is characterized in that: comprising:
One substrate is provided;
Form a plurality of conductor lines layers that contain an admixture in this substrate, wherein those conductor lines layer tops are formed with a cover curtain layer;
Implement a heat treatment, on this substrate that exposes and those conductor lines layer sidewalls, forming an oxide layer, and make this dopant diffusion in those conductor lines layers in this substrate and form a source/drain electrode;
Remove this cover curtain layer, to expose the top of those conductor lines layers;
Carry out one and aim at the metal silicide process voluntarily, aim at metal silicide layer voluntarily to form one at those conductor lines layer tops;
Remove this oxide layer;
Formation one silicon nitride stack layer covers those conductor lines layers and aims at metal silicide layer voluntarily with this in this substrate;
In this substrate, form plurality of word lines.
10. the manufacture method of silicon nitride ROM according to claim 9 is characterized in that: carry out this step of aiming at the metal silicide process voluntarily and comprise:
In this substrate, form a metal level and cover those conductor lines layers;
Carry out a drawing process, so that those conductor lines layers and the reaction of this metal level are aimed at metal silicide layer voluntarily and form this at those conductor lines layer tops;
Remove unreacted this metal level.
11. the manufacture method of silicon nitride ROM according to claim 10 is characterized in that: this metal level comprises cobalt/titanium layer.
12. the manufacture method of silicon nitride ROM according to claim 10 is characterized in that: the step of removing unreacted this metal level comprises wet etch process.
13. the manufacture method of silicon nitride ROM according to claim 9 is characterized in that: those conductor lines layers comprise doping compound crystal silicon line layer.
14. the manufacture method of silicon nitride ROM according to claim 9 is characterized in that: this heat treatment comprises thermal oxidation.
15. the manufacture method of silicon nitride ROM according to claim 9 is characterized in that: this cover curtain layer comprises silicon nitride layer.
16. the manufacture method of silicon nitride ROM according to claim 9 is characterized in that: the nesting structural embedded control that this silicon nitride stack layer is constituted comprise silicon oxide/silicon nitride/silicon oxide, silica/silicon nitride/silicon nitride and silicon nitride/silicon nitride/silicon nitride one of them.
17. the manufacture method of silicon nitride ROM according to claim 9 is characterized in that: the step that forms those character lines in this substrate comprises:
In this substrate, form a conductor layer and cover this silicon nitride stack layer;
Define this conductor layer, to form those character lines.
18. the manufacture method of silicon nitride ROM according to claim 17 is characterized in that: this conductor layer comprises compound crystal silicon layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02140799 CN1256768C (en) | 2002-07-25 | 2002-07-25 | Method for manufacturing silicon nitride ROM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02140799 CN1256768C (en) | 2002-07-25 | 2002-07-25 | Method for manufacturing silicon nitride ROM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1471154A CN1471154A (en) | 2004-01-28 |
| CN1256768C true CN1256768C (en) | 2006-05-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02140799 Expired - Fee Related CN1256768C (en) | 2002-07-25 | 2002-07-25 | Method for manufacturing silicon nitride ROM |
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| Country | Link |
|---|---|
| CN (1) | CN1256768C (en) |
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2002
- 2002-07-25 CN CN 02140799 patent/CN1256768C/en not_active Expired - Fee Related
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| CN1471154A (en) | 2004-01-28 |
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