CN1194407C - Method for preventing leakage current of embedded non-volatile memory - Google Patents
Method for preventing leakage current of embedded non-volatile memory Download PDFInfo
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- CN1194407C CN1194407C CNB011429879A CN01142987A CN1194407C CN 1194407 C CN1194407 C CN 1194407C CN B011429879 A CNB011429879 A CN B011429879A CN 01142987 A CN01142987 A CN 01142987A CN 1194407 C CN1194407 C CN 1194407C
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- 230000015654 memory Effects 0.000 title claims abstract description 105
- 238000000034 method Methods 0.000 title claims abstract description 43
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 49
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 15
- 238000006396 nitration reaction Methods 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 8
- 150000004706 metal oxides Chemical class 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- 150000004767 nitrides Chemical class 0.000 abstract description 4
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000002955 isolation Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 230000008672 reprogramming Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000012940 design transfer Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
The prevent invention relates to a method for preventing a leakage current of an embedded non-volatile memory. The embedded non-volatile memory comprises a memory array region and a logic element region on a substrate, wherein an oxide layer/nitride layer/oxide layer (ONO layer) is formed in the memory array region; a gate oxide layer is formed in the logic element region. In the method of the present invention, the conditions of two micro-image manufacturing processes are respectively used, so that transistors in the memory array region and in the logic element region can be respectively formed. In the memory array region, space widths between gates are equal, and gap walls have a large width; in the logic element region, spaces between the gates are unequal, wherein the width of the gap walls is optimal. According to the present invention, a leakage current path between bit lines during a self-aligned silicide step can be avoided through the separate type gap wall widths in the memory array region and the logic element region.
Description
Technical field
The relevant a kind of method that forms embedded non-volatile memory of the present invention, the particularly relevant separate type clearance wall that forms in embedded non-volatile memory is in case the method for leak-stopping electric current.
Background technology
Typical semiconductor memory is volatile storage (volatilememory) in the operating process of microprocessor.If the power interruptions of being supplied with, the data that then are stored in the semiconductor memory all can run off fully.And the method for head it off provides the memory backup of separate style, for example battery (battery power) or condenser storage (capacitor storage).Another kind of can technology alternatively then be to make a nonvolatile memory (non-volatile memory).The method of this selection has quite high satisfaction for the storage and the follow-up processing of data in the memory, this is because non-volatile semiconductor memory not only can not run off data when power supply supply with to interrupt, and data can be stored fully or change and need not any power supply and supply with.
Because non-volatility memorizer can not lose storage because of power interruptions, therefore compared to random access memory (random access memory, RAM), no matter be dynamic-form (dynamic) or static form (static), non-volatility memorizer has its importance that can not be ignored.Random access memory makes data to be stored in the memory or from memory by the operation of microprocessor and reads.The most general pattern is read-only memory (read-only memory in the non-volatility memorizer, ROM), and in various read-only memorys, use that (erasable programmable ROM, EPROM) flash memory (flash memory) of comparing technology is a kind of quite novel read-only memory element with wiping programmable read only memory.
In addition, as other common programmable read only memory wiped, the content of flash memory can be many times able to programme again, no matter be whole flash memory of reprogramming or reprogramming flash memory partly only.Except existing with the form of memory separately, flash memory also can be embedded in the process chip further, Here it is so-called embedded flash memory (embedded flash memory).Other flash memory of the efficiency ratio of embedded flash memory is not bad, and its reason is can improve effectively between bandwidth problem of memory and logical circuit (bandwidth problem) and the disappearance that interface peripheral circuit (interface circuit) and housed joint (package head) wait other flash memory often to have.In addition, the reaction speed of embedded flash memory is also very fast.
With reference to Figure 1A, a ground 100 is divided into memory array region (memory array) 100a and logic element district (logic device area) 100b.In traditional method, utilize thermal oxidation method (thermal oxidation) that the first dielectric layer 102a is formed on the ground 100.Yet the dielectric constant of the first dielectric layer 102a and the second dielectric layer 102c that deposited afterwards is greatly between 3.8 to 3.9, and thermal oxidation method is to be the high temperature process method.Then, will be deposited on the first dielectric layer 102a as the silicon nitride (siliconnitride) of electric charge storage layer (charge storage layer) 102b mode by traditional chemical vapour deposition (CVD).Then, the second dielectric layer 102c utilizes the method for traditional chemical deposition to be deposited on the electric charge storage layer 102b.Wherein, the material of a 102a and the second dielectric layer 102c is silica.(hotelectron injection phenomenon, HEI), some electronics can be through at the first dielectric layer 102a of bottom, and when the first dielectric layer 102a approached especially, electronics can be stored in the electric charge storage layer 102b to inject phenomenon according to hot electron.
With reference to Figure 1B and Fig. 1 C, photoresist layer is formed on the second dielectric layer 102c.Then, utilize etching step to remove at the second dielectric layer 102c, electric charge storage layer 102b and the first dielectric layer 102a of logic element district 100b.Then, after removing photoresist layer, lock oxide layer (gate oxide layer) 104 is formed on logic element district 100b, and then polysilicon layer 106 is deposited on memory array region 100a and logic element district 100b at Fig. 1 C.Then, limit a character line (word line) and another photoresist layer is formed on the polysilicon layer 106 at memory array region 100a.Then, make and on memory array region 100a and logic element district 100b, can form polycrystalline silicon gate pole (poly gateelectrode) 106 simultaneously carrying out an etching step on the polysilicon layer 106.
Then, with reference to figure 1D, cvd silicon oxide is to fill up the spacing between the polycrystalline silicon gate pole 106.On silica, carry out the etch-back step then, make on the sidewall of polycrystalline silicon gate pole 106, to form clearance wall 110.Then, on polycrystalline silicon gate pole 106, form automatic aligned metal layer (self-aligned salicide).
Fig. 1 E is the vertical view of a memory component.Memory cell in horizontal line and the line (memory cell) is joined, and is called character line (word lines) 112a, 112b, 112c, and 112d.And up and down the lead of stringer because of relevant, so be called bit line (bit lines) 114a, 114b, 114c, and 114d with the transmission of data (data).Dotted line 116 among the figure then is to be transverse to character line 112a, 112b, 112c, and 112d.Because the thickness of the second dielectric layer 102C is too thin, make in the follow-up step of aiming at metal silicide voluntarily, metal silicide can be because oxide layer/nitration case/oxide layer (ONO, oxide/nitride/oxide layer) thickness of 102C is too thin and pass nitration case/oxide layer/nitration case 102 and arrive ground 100, makes whole semiconductor element to operate.
The method of traditional formation in-line memory has two main shortcomings, and one is that cost is higher, and another then is that method exists the usefulness of restriction and memory to reduce.Because memory array region and logic element district form with identical step, can't reach optimization simultaneously.That is to say not to be that the transistorized usefulness in logic element district reduces, is exactly that the transistorized reliability of memory array region reduces.
Summary of the invention
The purpose of this invention is to provide a kind of method that prevents leakage current of embedded non-volatile memory, this method provide separate type clearance wall width avoid to form effective oxidated layer thickness form conductor layer between the bit line, carrying out voluntarily to prevent between the bit line, to form drain current path on time, adjust by separate type that little shadow stripe spare obtains the optimum process space in memory array region and logic element district in case stop bit unit line to the leakage current of bit line and little shadow space of improving character line and CMOS (Complementary Metal Oxide Semiconductor) polycrystalline silicon gate pole.
For achieving the above object, the method that prevents leakage current of embedded non-volatile memory according to an aspect of the present invention is characterized in comprising at least: a ground with a memory array region and a logic element district is provided; Form one oxide layer/nitration case/oxide layer (ONO) at described memory array region; Deposit a dielectric layer in described logic element district; Form a polysilicon layer in described memory array region and described logic element district; The described polysilicon layer of etching is to form several character lines at described memory array region; Forming a clearance wall between described several character lines to be filled in spacing between described several character lines; And in described logic element district, form the metal-oxide semiconductor transistor.
The method of formation embedded non-volatile memory according to a further aspect of the invention is characterized in comprising at least: a ground with a memory array region and a logic element district is provided; Form one oxide layer/nitration case/oxide layer (ONO) at described memory array region; Form a lock oxide layer in described logic element district; Deposit a polysilicon layer in described memory array region and described logic element district; The described polysilicon layer of etching is to form several character lines at described memory array region; Forming one first clearance wall between described several character lines to be filled in the spacing between described several character lines; In described logic element district, form the metal-oxide semiconductor transistor; And in described memory array region and described logic element district, carry out one and aim at the metal silicide step voluntarily.
Method according to the formation embedded non-volatile memory of another aspect of the invention is characterized in comprising at least: a ground with a memory array region and a logic element district is provided; Deposit one first dielectric layer in regular turn on described ground, an electric charge storage layer on described first dielectric layer and one second dielectric layer on described electric charge storage layer; Remove described first dielectric layer, described electric charge storage layer and described second dielectric layer in described logic element district; Form one the 3rd dielectric layer in described logic element district; Deposit a polysilicon layer in described memory array region and described logic element district; The described polysilicon layer of etching is to form several character lines at described memory array region; Forming one first clearance wall between described several character lines to be filled in the spacing between described several character lines; The described polysilicon layer of etching and in described logic element district, form polycrystalline silicon gate pole; In described logic element district, form the light dope drain area; Between the described polycrystalline silicon gate pole in the described logic element district, form one second clearance wall; Form one source pole/drain area and be adjacent to described light dope drain area; And in described memory array region and described logic element district, carry out one and aim at the metal silicide step voluntarily.
For clearer understanding purpose of the present invention, characteristics and advantage, preferred embodiment of the present invention is elaborated below in conjunction with accompanying drawing.
Description of drawings
Figure 1A is the structural representation that forms gate dielectric layer according to conventional art on ground;
Figure 1B is the structural representation that forms lock oxide layer and polysilicon layer according to conventional art on ground;
Fig. 1 C is the structural representation that forms polycrystalline silicon gate pole according to conventional art in memory array region and logic element district simultaneously;
Fig. 1 D is the structural representation that forms memory component according to conventional art on ground;
Fig. 1 E is the vertical view for memory component;
Fig. 2 A is according to each step structural representation when forming memory array on chip of the present invention;
Fig. 2 B be according to the present invention in the structure of Fig. 2 A, on memory array region, form the polycrystalline silicon gate pole structural representation;
Fig. 2 C is the structural representation that forms polycrystalline silicon gate pole according to the present invention on the structure of Fig. 2 B; And
Fig. 2 D be according to the present invention in the structure of Fig. 2 C, in memory array region and logic element district, form transistorized structural representation.
Embodiment
Some embodiments of the present invention are described in detail as follows.Yet except describing in detail, the present invention can also be widely implements at other embodiment, and scope of the present invention do not limit by it, but is as the criterion with the claim of claims.
Isolated component (isolation device) is arranged in ground 10.This isolated component be the shallow trench isolation element (shallow trench isolation, STI).This isolation structure is used to isolate the transistor in memory array region on the ground and logic element district.At this, ground 10 is divided into two zones at least, one is the logic element district 10b that has the memory array region 10a of memory function and have logical circuit function (logic circuit function), and logic element district 10b is adjacent to memory array region 10a.For forming the shallow trench isolation element, silicon nitride layer (silicon nitride) and photoresist layer are deposited on the ground 10 in regular turn, then utilize existing method for photolithography with the design transfer of shallow trench to photoresist layer.Then with photoresist layer as cover curtain etches both silicon nitride layer and the ground that partly exposes, and in ground, form the shallow trench structure.Then, after photoresist layer removes, insert silicon oxide layer in the shallow trench again or utilize thermal oxidation method in shallow trench, to form oxide layer with as the shallow trench isolation element.
With reference to figure 2A, the pattern of a word line architecture is limited on the memory array region 10a of ground 10.Oxide layer/nitration case/oxide layer (its thickness is approximately 200 dusts for oxide/nitride/oxide, ONO) 12 structure, be deposited on the ground 10 with form silicon nitride ROM (nitride read-only memory, NROM).Oxide layer/nitration case/oxide layer 12 structures are: the silica 1 2a at bottom (can be described as tunnel oxide again, tunneling oxide) be first dielectric layer, silicon nitride layer 12b forms on ground 10 respectively in regular turn as electric charge storage layer (charge storagelayer) and at the silicon dioxide layer 12c as second dielectric layer on the electric charge storage layer.And the first dielectric layer 12a utilizes thermal oxidation method to form on ground 10, electric charge storage layer 12b utilizes traditional chemical vapour deposition technique (chemical vapor deposition, CVD) on the first dielectric layer 12a, form, for programmable storage, electric charge storage layer 12b provides the function that a kind of electric charge keeps, and then with second dielectric layer 12c deposition or utilize thermal oxidation method to grow (oxidized silicon nitride layer) on electric charge storage layer 12b.Then, the pattern of bit line (bit line) structure is limited on the ground 10, and forms the bit line.Then, oxide layer/nitration case/12 of the oxide layers on logic element district (logic device area) 10b are that (Reactive Ion Etching, method RIE) removes by reactive ion etching.Then, will utilize thermal oxidation method to form as the 3rd dielectric layer of lock oxide layer 14 at logic element district 10b.Then, polysilicon layer 16 is formed on memory array region (memory array) 10a and logic element district 10b.
Then, on the polysilicon layer 16 of memory array region 10a, carry out little shadow, and photoresist layer also covers on the logic element district 10b simultaneously with reference to figure 2B.Then, on polysilicon layer 16, carry out etching step, make and on memory array region 10a, form polycrystalline silicon gate pole (poly gate electrodes) 16a, wherein between between the polycrystalline silicon gate pole 16a, equate apart from width, and be effective clearance wall width, make oxide layer spacing can be filled up.Then, after polycrystalline silicon gate pole 16a forms, again the photoresist layer on logic element district 10b and the memory array region 10a is removed.
Then, on memory array region 10a, on the sidewall of polycrystalline silicon gate pole 16a, form first clearance wall 18.The formation of clearance wall 18 then is that deposited oxide layer is to be filled in the upward spacing between the polycrystalline silicon gate pole 16a of memory array region 10a.And then utilize the mode etching oxide layer of etch-back (etching back) and on the sidewall of polycrystalline silicon gate pole 16a, form clearance wall 18.Adjust the thickness of deposited oxide layer, make etch-back after, fill up apart from being able to oxidized layer between the polycrystalline silicon gate pole 16a.
With reference to figure 2C and Fig. 2 D, then, on the polysilicon layer 16 of logic element district 10b, carry out little shadow step.Then, etching polysilicon layer 16, and on logic element district 10b, form polycrystalline silicon gate pole 16b, wherein, spacing width between the polycrystalline silicon gate pole 16b is unequal, and has suitable clearance wall width and the oxide layer in the subsequent step can be inserted in the spacing fully.Then, below the lock oxide layer 14 of logic element district 10b, form light dope drain area (lightly doped drain region, LDD region).Then, oxide deposition is filled in spacing between the polycrystalline silicon gate pole 16b, and utilizes the mode etching oxide layer of etch-back, make on the sidewall of polycrystalline silicon gate pole 16b, to form second clearance wall 20.Then, the mode of utilizing conventional ion to implant forms source/drain (source/drain) in ground 10.At last, utilize the step aim at metal silicide (self-aligned salicide) voluntarily will aim at voluntarily on the polycrystalline silicon gate pole 16b that metal silicide (salicide) 24 is deposited on the polycrystalline silicon gate pole 16a of memory array region 10a and logic element district 10b.
Can know that according to above description in the present invention advantage is that transistor on memory array region 10a and logic element district 10b is to utilize twice little shadow step to form respectively.Utilize the little shadow stripe spare that separates twice can adjust the depth of focus (DOF of character line array and complementary metal oxide semiconductor gate respectively, depth of focus) and exposure latitude (EL, exposure latitude), and improve the method in the micro-photographing process space of character line and complementary metal oxide polycrystalline silicon semiconductor gate simultaneously, can reach and prevent that the bit line is to the leakage current between the bit line.In addition, the separate type clearance wall width on memory array region 10a and logic element district 10b can also can be avoided forming drain current path between the bit line in aiming at the metal silicide processing procedure voluntarily.
The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence finished under the disclosed spirit and changes or modify, and all should be included in the claim that claims limit.
Claims (9)
1. method that prevents leakage current of embedded non-volatile memory is characterized in that comprising at least:
Ground with memory array region and logic element district is provided;
Form oxide layer/nitration case/oxide layer at described memory array region;
Dielectric layer is in described logic element district;
Form polysilicon layer in described memory array region and described logic element district;
The described polysilicon layer of etching is to form several character lines at described memory array region;
Forming clearance wall between described several character lines to be filled in spacing between described several character lines; And
In described logic element district, form the metal-oxide semiconductor transistor.
2. the method for claim 1 is characterized in that, also is included in to form the bit line after described oxide layer/nitration case/oxide layer forms step.
3. method that forms embedded non-volatile memory is characterized in that comprising at least:
Ground with memory array region and logic element district is provided;
Form oxide layer/nitration case/oxide layer at described memory array region;
Form the lock oxide layer in described logic element district;
The deposit spathic silicon floor is in described memory array region and described logic element district;
The described polysilicon layer of etching is to form several character lines at described memory array region;
Forming first clearance wall between described several character lines to be filled in the spacing between described several character lines;
In described logic element district, form the metal-oxide semiconductor transistor; And
In described memory array region and described logic element district, aim at the metal silicide step voluntarily.
4. method as claimed in claim 3 is characterized in that, also is included in to form on the described memory array region to form the bit line after nitration case/oxide layer/nitration case step.
5. method as claimed in claim 3 is characterized in that, described metal oxide semiconductor transistor comprises that at least polycrystalline silicon gate pole is on the described lock oxide layer and on the sidewall of second clearance wall in described polycrystalline silicon gate pole.
6. method that forms embedded non-volatile memory is characterized in that comprising at least:
Ground with memory array region and logic element district is provided;
Deposit first dielectric layer in regular turn on described ground, electric charge storage layer on described first dielectric layer and second dielectric layer on described electric charge storage layer;
Remove described first dielectric layer, described electric charge storage layer and described second dielectric layer in described logic element district;
Form the 3rd dielectric layer in described logic element district;
The deposit spathic silicon floor is in described memory array region and described logic element district;
The described polysilicon layer of etching is to form several character lines at described memory array region;
Forming first clearance wall between described several character lines to be filled in the spacing between described several character lines;
The described polysilicon layer of etching and in described logic element district, form polycrystalline silicon gate pole;
In described logic element district, form the light dope drain area;
Between the described polycrystalline silicon gate pole in the described logic element district, form second clearance wall;
Form source/drain and be adjacent to described light dope drain area; And
In described memory array region and described logic element district, aim at the metal silicide step voluntarily.
7. method as claimed in claim 6 is characterized in that, the material of described first dielectric layer, described second dielectric layer and described the 3rd dielectric layer comprises silica at least.
8. method as claimed in claim 7 is characterized in that the material of described electric charge storage layer comprises silicon nitride at least.
9. method as claimed in claim 6 is characterized in that, also is included in described deposition step in regular turn and forms afterwards a bit line.
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| CNB011429879A CN1194407C (en) | 2001-12-04 | 2001-12-04 | Method for preventing leakage current of embedded non-volatile memory |
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| CNB011429879A CN1194407C (en) | 2001-12-04 | 2001-12-04 | Method for preventing leakage current of embedded non-volatile memory |
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| TWI424502B (en) | 2008-04-09 | 2014-01-21 | Nanya Technology Corp | Semiconductor structure and method of making the same |
| CN101577243B (en) * | 2008-05-09 | 2013-09-18 | 南亚科技股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN102237366B (en) * | 2010-04-29 | 2016-06-15 | 旺宏电子股份有限公司 | There is continuous electric charge and store the non-volatile storage array of dielectric stack |
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