CN101577243B - Semiconductor structure and manufacturing method thereof - Google Patents
Semiconductor structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN101577243B CN101577243B CN200810095288.XA CN200810095288A CN101577243B CN 101577243 B CN101577243 B CN 101577243B CN 200810095288 A CN200810095288 A CN 200810095288A CN 101577243 B CN101577243 B CN 101577243B
- Authority
- CN
- China
- Prior art keywords
- layer
- semiconductor structure
- anticreep
- silicon
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 56
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 56
- 239000010703 silicon Substances 0.000 claims abstract description 56
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 46
- 239000000758 substrate Substances 0.000 claims description 27
- 239000000377 silicon dioxide Substances 0.000 claims description 23
- 230000004888 barrier function Effects 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 18
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 12
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 7
- 239000005368 silicate glass Substances 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 33
- 229910052760 oxygen Inorganic materials 0.000 abstract description 33
- 239000001301 oxygen Substances 0.000 abstract description 33
- 238000005530 etching Methods 0.000 abstract description 9
- 239000010410 layer Substances 0.000 description 138
- 239000011229 interlayer Substances 0.000 description 20
- 239000000463 material Substances 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 9
- 230000000903 blocking effect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Images
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses an uvioresistant and anti-leaky semiconductor structure and a manufacturing method thereof, which are characterized in that amorphous silicon is used for replacing an oxygen-rich silicon layer or an oxygen-superrich silicon layer used in the prior art, thereby the problem of etching control is improved. The invention is additionally characterized in that a silicon nitride clearance wall is used in a contact hole so that the problem of electric leakage is solved.
Description
Technical field
The present invention relates to a kind of semiconductor structure and preparation method thereof, refer to a kind of effectively shielding of ultraviolet especially and prevent semiconductor structure that leaks electricity and preparation method thereof.
Background technology
Non-volatility memorizer has the characteristic of the read-write that can repeat to erase, add transmission fast, low power consumption, so be widely used in the various portable products, and become necessary element in many information, communication and the consumption electronic products.
What Fig. 1 illustrated is known non-volatile memory structure.As shown in Figure 1, in the memory array region and periphery circuit region of substrate 10, be respectively equipped with transistor 12a and transistor 12b, wherein transistor 12a comprises grid 14a, gate dielectric 16a, source drain doped region 18a is located in the grid 14a substrate on two sides 10.Transistor 12b comprises grid 14b, gate dielectric 16b, source drain doped region 18b is located in the grid 14b substrate on two sides 10.Isolate with insulating barrier 20 between each transistor 12a, 12b.
Be formed with interlayer dielectric layer 24,30 and 32 on grid 14a, the 14b, contact plunger 22, metallic circuit 26 and interlayer connector 28 then are formed in the interlayer dielectric layer 24,30 and 32, are used for being electrically connected different elements and the lead of each interlayer.
Wherein, interlayer dielectric layer 24 can be boron phosphorus silicate glass, non-doped silicon glass layer or other insulating material, interlayer dielectric layer 30 is by super oxygen enrichment silicon (super silicon rich oxide, SSRO) or oxygen enrichment silicon (silicon rich oxide, SRO) constitute, interlayer dielectric layer 32 can be tetraethoxysilane (TEOS) silica layer or other insulating material.Because ultraviolet ray meeting shadow causes grid start voltage instability to the start voltage of grid, for fear of the influence that ultraviolet ray causes, in traditional non-volatility memorizer, interlayer dielectric layer 30 uses super oxygen enrichment silicon or oxygen enrichment silicon as ultraviolet blocking layer.
Yet super oxygen enrichment silicon and oxygen enrichment silicon contain the silicon of high concentration, and its rate of etch is low, when forming interlayer connector 28, may cause over etching or the undercut of fairlead, cause not good and technology allowance (process window) decline of process stabilizing degree.Moreover, when the super oxygen enrichment silicon of etching or oxygen enrichment silicon, because rate of etch is not good, make super oxygen enrichment silicon or oxygen enrichment silicon ablation fully easily, remain in the dead angle, cause the phenomenon of conducting easily.In addition, known non-volatility memorizer has the electric leakage problem.Electric leakage normally occurs between the top surface and grid 14a, 14b and substrate 10 of grid 14a, 14b.
Therefore, how to improve the electric leakage problem of problem that above-mentioned super oxygen enrichment silicon and oxygen enrichment silicon causes and known non-volatility memorizer, still need the important topic of research for industry badly.
Summary of the invention
Main purpose of the present invention is to provide a kind of semiconductor structure and technology, and it utilizes anticreep layer and anticreep clearance wall to prevent known semiconductor electric leakage problem.In addition, this semiconductor structure and technology, other comprises a kind of ultraviolet blocking layer of novelty, to improve the problem that aforementioned super oxygen-rich silicon layer and oxygen enrichment silicon are caused.
According to claim of the present invention, the manufacture method of semiconductor structure is that substrate is provided earlier, and this substrate comprises conductive layer, then, on this conductive layer, form dielectric layer, wherein this dielectric layer includes amorphous silicon layer at least, then, forms the contact hole in this dielectric layer, to expose the conductive layer of part, sidewall in this contact hole forms anticreep clearance wall again, and is last, forms contact plunger in this contact hole.
According to claim of the present invention, other discloses a kind of semiconductor structure and comprises: substrate comprises conductive layer; Dielectric layer is located on this conductive layer, and wherein this dielectric layer includes amorphous silicon layer at least; And contact plunger, be located in this dielectric layer, wherein be provided with anticreep clearance wall between this contact plunger and this dielectric layer.
Because the present invention uses amorphous silicon layer to replace the employed super oxygen enrichment silicon of known technology or oxygen enrichment silicon as ultraviolet blocking layer, therefore when making fairlead, just can remove the super oxygen enrichment silicon of etching or oxygen enrichment silicon from and cause the not good problem of process stabilizing degree.In addition, the present invention is located at anticreep material in the sidewall and dielectric layer in contact hole, thus, because the sidewall in contact hole is coated fully by anticreep material, makes semiconductor structure of the present invention that preferable anticreep effect can be provided.
Description of drawings
What Fig. 1 illustrated is known non-volatile memory structure.
Fig. 2 to Fig. 7 is the schematic diagram of the semiconductor structure manufacture method that illustrates according to first preferred embodiment of the invention.
Fig. 8 to Figure 13 is the schematic diagram of the semiconductor structure manufacture method that illustrates according to second preferred embodiment of the invention.
Description of reference numerals
10 substrate 12a, 12b transistor
14a, 14b conductive grid 16a, 14b gate dielectric
18a, 18b source drain doped region 20 insulating barriers
22 contact plungers, 24 inner layer dielectric layers
26 contact mats, 28 interlayer connectors
30,32 interlayer dielectric layers, 50 substrates
51,52 conductive layers, 54 doped polysilicon layers
56 metal silicide layers, 58 dielectric layers
60 first silica layers, 62 amorphous silicon layers
64 second silica layers, 66 anticreep layers
68 insulating barriers, 70 contact holes
72 look edge layers, 74 anticreep clearance wall
76 contact plungers, 78 interlayer dielectric layers
80 semiconductor structures
Embodiment
Please refer to Fig. 2 to Fig. 7, it is the schematic diagram of the semiconductor structure manufacture method that illustrates according to first preferred embodiment of the invention.As shown in Figure 2, at first provide substrate 50, comprise conductive layer 52.Conductive layer 52 is located at the surface of substrate 50, and conductive layer 52 can be the grid structure that is made of doped polysilicon layer 54 and metal silicide layer 56.Certainly, the material that forms grid structure is not limited only to aforesaid doped polycrystalline silicon and metal silicide, and any material of suitable conductive effect that can provide all can use.
Then, on conductive layer 52, cover dielectric layer 58.The step that forms dielectric layer 58 comprises: deposit first silica layer 60, amorphous silicon layer 62, second silica layer 64, anticreep layer 66 and insulating barrier 68 in regular turn.Then, utilize chemico-mechanical polishing with insulating barrier 68 planarizations.Wherein above-mentioned first silica layer and second silica layer can be non-doped silicon glass layer, and insulating barrier 68 can be the boron phosphorus silicate glass layer, in addition, anticreep layer 66 can use silicon nitride, carborundum or silicon oxynitride as material, and according to a preferred embodiment of the invention, the preferred material of anticreep layer 66 is silicon nitride.
As shown in Figure 4, form contact hole 70 in dielectric layer 58, wherein the surface of conductive layer 52 exposes to the open air out via contact hole 70, forms insulating barrier 72 on the surface of contact hole 70 and dielectric layer 58 then.
As shown in Figure 5, through anisotropic etching insulating barrier 72, on the sidewall in contact hole 70, form anticreep clearance wall 74, the sidewall in contact hole 70 is coated fully, wherein anticreep clearance wall 74 can use silicon nitride, carborundum or silicon oxynitride as material, and according to a preferred embodiment of the invention, the preferred material of anticreep clearance wall 74 is silicon nitride.
As shown in Figure 6, form contact plunger 76 in contact hole 70, wherein contact plunger 76 comprises tungsten, titanium nitride and titanium.Thus, namely finishing tool of the present invention can be anticreep and the semiconductor structure 80 of anti-ultraviolet function.
As shown in Figure 7, on dielectric layer 58, form interlayer dielectric layer 78, come shielding of ultraviolet because using amorphous silicon layer 62, at this moment, can not need to use super oxygen enrichment silicon or oxygen enrichment silicon in the interlayer dielectric layer 78.Certainly, according to different product demands, also can use super oxygen enrichment silicon or oxygen enrichment silicon and amorphous silicon layer as the barrier layer simultaneously, make that the effect of shielding of ultraviolet is better.
Can produce as shown in Figure 7 semiconductor structure according to first embodiment of semiconductor structure manufacture method of the present invention, a kind of semiconductor structure 80 as shown in Figure 7, comprise substrate 50, wherein substrate 50 comprises conductive layer 52, wherein conductive layer 52 is located at the surface of substrate 50, and conductive layer 52 can be the grid structure that is made of doped polysilicon layer 54 and metal silicide layer 56.
In addition, this semiconductor structure comprises dielectric layer 58 in addition, be located on the conductive layer 52, wherein dielectric layer 58 comprises first silica layer 60, amorphous silicon layer 62, second silica layer 64, anticreep layer 66 and insulating barrier 68 in regular turn by lower floor to upper strata, in addition, contact plunger 76 is located in the dielectric layer 58, wherein is provided with anticreep clearance wall 74 between contact plunger 76 and the dielectric layer 58.
The first above-mentioned silica layer and second silica layer can be non-doped silicon glass layer, and insulating barrier 68 can be the boron phosphorus silicate glass layer, in addition, anticreep layer 66 can use silicon nitride, carborundum or silicon oxynitride as material, and according to a preferred embodiment of the invention, the preferred material of anticreep layer 66 is silicon nitride, in addition, anticreep clearance wall 74 can use silicon nitride, carborundum or silicon oxynitride as material, and according to a preferred embodiment of the invention, the preferred material of anticreep clearance wall 74 is silicon nitride.In addition, on dielectric layer 58, can form interlayer dielectric layer 78 in addition.
Aforesaid first embodiment, its contact plunger directly is electrically connected the grid structure that is positioned at substrate surface, yet semiconductor technology of the present invention not only can be applicable to the contact plunger of direct electric connection grid electrode structure, also can use at the semiconductor structure that directly is electrically connected the contact plunger of substrate.The second following embodiment will introduce the technology that the present invention is applied to directly to be electrically connected the contact plunger of substrate.The element that wherein has identical function will prolong with the component symbol among first embodiment.
Please refer to Fig. 8 to Figure 13, it is the schematic diagram of the semiconductor structure manufacture method that illustrates according to second preferred embodiment of the invention.
As shown in Figure 8, at first provide substrate 50, comprise conductive layer 51, wherein conductive layer 51 is located within the substrate 50, and conductive layer 51 can be doped region.
Then, as shown in Figure 9, cover dielectric layer 58 on the surface of substrate 50, the step that forms dielectric layer 58 comprises: deposit first silica layer 60, amorphous silicon layer 62, second silica layer 64, anticreep layer 66 and insulating barrier 68 in regular turn, then utilize chemico-mechanical polishing with insulating barrier 68 planarizations.Wherein above-mentioned first silica layer and second silica layer can be non-doped silicon glass layer, and insulating barrier 68 can be the boron phosphorus silicate glass layer, in addition, anticreep layer 66 can use silicon nitride, carborundum or silicon oxynitride as material, and according to a preferred embodiment of the invention, the preferred material of anticreep layer 66 is silicon nitride.
As shown in figure 10, form contact hole 70 in dielectric layer 58, wherein conductive layer 51 exposes to the open air out via contact hole 70, forms insulating barrier 72 on the surface of contact hole 70 and dielectric layer 58 then.
As shown in figure 11, through anisotropic etching insulating barrier 72, the sidewall that the anticreep clearance wall 74 of formation will contact hole 70 on the sidewall in contact hole 70 coats fully, wherein anticreep clearance wall 74 can use silicon nitride, carborundum or silicon oxynitride as material, and according to a preferred embodiment of the invention, the preferred material of anticreep clearance wall 74 is silicon nitride.
As shown in figure 12, form contact plunger 76 in contact hole 70, wherein contact plunger 76 comprises tungsten, titanium nitride or titanium.Thus, namely finishing tool of the present invention can be anticreep and the semiconductor structure 80 of anti-ultraviolet function.
As shown in figure 13, on dielectric layer 58, form interlayer dielectric layer 78, because the present invention uses amorphous silicon layer 62 to come shielding of ultraviolet, optionally use super oxygen enrichment silicon or oxygen enrichment silicon in the interlayer dielectric layer 78.
What Figure 13 illustrated is the produced semiconductor structure of second embodiment of semiconductor structure, in accordance with the present invention manufacture method.As shown in figure 13, a kind of semiconductor structure 80 comprises substrate 50, and wherein substrate 50 comprises conductive layer 51, and wherein conductive layer 51 is located in the substrate 50, and conductive layer 51 can be doped region.In addition, this semiconductor structure comprises dielectric layer 58 in addition, be located in the substrate 50, wherein dielectric layer 58 comprises first silica layer 60, amorphous silicon layer 62, second silica layer 64, anticreep layer 66 and insulating barrier 68 in regular turn by lower floor to upper strata, in addition, one contact plunger 76 is located in the dielectric layer 58, wherein is provided with anticreep clearance wall 74 between contact plunger 76 and the dielectric layer 58.
The first above-mentioned silica layer and second silica layer can be non-doped silicon glass layer, and insulating barrier 68 can be the boron phosphorus silicate glass layer, in addition, anticreep layer 66 can use silicon nitride, carborundum or silicon oxynitride as material, and according to a preferred embodiment of the invention, the preferred material of anticreep layer 66 is silicon nitride, in addition, anticreep clearance wall 74 can use silicon nitride, carborundum or silicon oxynitride as material, and according to a preferred embodiment of the invention, the preferred material of anticreep clearance wall 74 is silicon nitride.In addition, on dielectric layer 58, can form interlayer dielectric layer 78 in addition.
Because semiconductor structure of the present invention has an amorphous silicon layer as ultraviolet blocking layer, can be used to replace in the known technology oxygen enrichment silicon or the super oxygen enrichment silicon in the interlayer dielectric layer of being located at, therefore, just not necessarily to use oxygen enrichment silicon or super oxygen enrichment silicon in the interlayer dielectric layer, thus, when the etching fairlead, just can avoid because the rate of etch of oxygen enrichment silicon and super oxygen enrichment silicon is not good, excessive or the problem of undercut of the fairlead etching that causes, in addition, also can solve oxygen enrichment silicon and super oxygen enrichment silicon in etching the residual problem at the dead angle later, and therefore the technology allowance also improves.In addition, the present invention uses silicon nitride will contact the hole and coats fully, and silicon nitride is arranged in the dielectric layer, so, conductor structure of the present invention has the advantage that prevents conductive layer electric leakage, for example: can prevent from leaking electricity at the upper surface of grid or grid and substrate joint.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (16)
1. the manufacture method of a semiconductor structure is characterized in that, includes at least:
Substrate is provided, comprises conductive layer;
Form dielectric layer on this conductive layer, wherein this dielectric layer includes silica layer, amorphous silicon layer, insulating barrier and anticreep layer at least, this amorphous silicon layer be arranged under the superiors of this dielectric layer and should anticreep layer under;
In this dielectric layer, form the contact hole, to expose this conductive layer of part;
On the sidewall in this contact hole, form anticreep clearance wall; And
In this contact hole, form contact plunger.
2. the manufacture method of semiconductor structure as claimed in claim 1 is characterized in that, this anticreep clearance wall comprises silicon nitride, carborundum and silicon oxynitride.
3. the manufacture method of semiconductor structure as claimed in claim 1 is characterized in that, this anticreep layer comprises silicon nitride, carborundum and silicon oxynitride.
4. the manufacture method of semiconductor structure as claimed in claim 1 is characterized in that, this silica layer is non-doped silicon glass layer.
5. the manufacture method of semiconductor structure as claimed in claim 1 is characterized in that, this insulating barrier is the boron phosphorus silicate glass layer.
6. the manufacture method of semiconductor structure as claimed in claim 1 is characterized in that, this conductive layer comprises grid.
7. the manufacture method of semiconductor structure as claimed in claim 1 is characterized in that, this conductive layer comprises doped region.
8. the manufacture method of semiconductor structure as claimed in claim 1 is characterized in that, this contact plunger comprises tungsten, titanium nitride and titanium.
9. a semiconductor structure is characterized in that, comprises at least:
Substrate comprises conductive layer;
Dielectric layer is located on this conductive layer, wherein comprises silica layer, amorphous silicon layer, insulating barrier and anticreep layer in this dielectric layer at least, this amorphous silicon layer be arranged under the superiors of this dielectric layer and should anticreep layer under;
Contact plunger is located in this dielectric layer and is through to this conductive layer; And
Anticreep clearance wall is located on the sidewall of this contact plunger.
10. semiconductor structure as claimed in claim 9 is characterized in that, this anticreep layer comprises silicon nitride, carborundum and silicon oxynitride.
11. semiconductor structure as claimed in claim 9 is characterized in that, this anticreep clearance wall comprises silicon nitride, carborundum and silicon oxynitride.
12. semiconductor structure as claimed in claim 9 is characterized in that, this silica layer is non-doped silicon glass layer.
13. semiconductor structure as claimed in claim 9 is characterized in that, this insulating barrier is the boron phosphorus silicate glass layer.
14. semiconductor structure as claimed in claim 9 is characterized in that, this conductive layer comprises grid.
15. semiconductor structure as claimed in claim 9 is characterized in that, this conductive layer comprises doped region.
16. semiconductor structure as claimed in claim 9 is characterized in that, this contact plunger comprises tungsten, titanium nitride and titanium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810095288.XA CN101577243B (en) | 2008-05-09 | 2008-05-09 | Semiconductor structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810095288.XA CN101577243B (en) | 2008-05-09 | 2008-05-09 | Semiconductor structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101577243A CN101577243A (en) | 2009-11-11 |
| CN101577243B true CN101577243B (en) | 2013-09-18 |
Family
ID=41272126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200810095288.XA Active CN101577243B (en) | 2008-05-09 | 2008-05-09 | Semiconductor structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101577243B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110120368B (en) * | 2018-02-05 | 2021-05-11 | 联华电子股份有限公司 | Method for forming dynamic random access memory |
| KR102502165B1 (en) * | 2018-10-19 | 2023-02-21 | 삼성전자주식회사 | Semiconductor devices |
| CN113851427A (en) * | 2020-06-28 | 2021-12-28 | 无锡华润上华科技有限公司 | Semiconductor device with a plurality of transistors |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1423323A (en) * | 2001-12-04 | 2003-06-11 | 旺宏电子股份有限公司 | Method for preventing leakage current of embedded non-volatile memory |
| US6693002B2 (en) * | 2000-04-06 | 2004-02-17 | Fujitsu Limited Kabushiki Kaisha Toshiba | Semiconductor device and its manufacture |
| TW584923B (en) * | 2003-04-10 | 2004-04-21 | Nanya Technology Corp | Bit line contact and method for forming the same |
| US6797565B1 (en) * | 2002-09-16 | 2004-09-28 | Advanced Micro Devices, Inc. | Methods for fabricating and planarizing dual poly scalable SONOS flash memory |
| CN1567569A (en) * | 2003-06-10 | 2005-01-19 | 南亚科技股份有限公司 | Method for controlling top size of trench |
| US20050277258A1 (en) * | 2004-06-01 | 2005-12-15 | Tse-Yao Huang | Method for forming self-aligned contact in semiconductor device |
-
2008
- 2008-05-09 CN CN200810095288.XA patent/CN101577243B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6693002B2 (en) * | 2000-04-06 | 2004-02-17 | Fujitsu Limited Kabushiki Kaisha Toshiba | Semiconductor device and its manufacture |
| CN1423323A (en) * | 2001-12-04 | 2003-06-11 | 旺宏电子股份有限公司 | Method for preventing leakage current of embedded non-volatile memory |
| US6797565B1 (en) * | 2002-09-16 | 2004-09-28 | Advanced Micro Devices, Inc. | Methods for fabricating and planarizing dual poly scalable SONOS flash memory |
| TW584923B (en) * | 2003-04-10 | 2004-04-21 | Nanya Technology Corp | Bit line contact and method for forming the same |
| CN1567569A (en) * | 2003-06-10 | 2005-01-19 | 南亚科技股份有限公司 | Method for controlling top size of trench |
| US20050277258A1 (en) * | 2004-06-01 | 2005-12-15 | Tse-Yao Huang | Method for forming self-aligned contact in semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101577243A (en) | 2009-11-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104241357A (en) | Transistor, integrated circuit and method for manufacturing integrated circuit | |
| CN104681630A (en) | Thin film transistor and manufacturing method thereof as well as array substrate and display panel | |
| CN101577243B (en) | Semiconductor structure and manufacturing method thereof | |
| CN101246886B (en) | Power transistor with MOS structure and production method thereof | |
| TW201306180A (en) | Manufacturing method of memory structure | |
| CN1396646A (en) | Technology manufacturing contact plug of embedded memory | |
| CN105702684A (en) | Array substrate and array substrate making method | |
| KR100861837B1 (en) | Method of forming a metal line in semiconductor device | |
| CN102810505A (en) | Semiconductor process | |
| CN103021999B (en) | Semiconductor structure and manufacture method thereof | |
| TWI424502B (en) | Semiconductor structure and method of making the same | |
| KR20090036879A (en) | Method of manufacturing semiconductor device | |
| CN1988181A (en) | Capacitor in the semiconductor device and method of fabricating the same | |
| CN101211759A (en) | Capacitor, random memory cell and method for forming same | |
| CN104810371A (en) | Semiconductor memory device and manufacturing method thereof | |
| CN102931091A (en) | Driving matrix type flat panel display device, thin film transistor and manufacturing method of driving matrix type flat panel display device and thin film transistor | |
| KR20080092557A (en) | Method for fabricating interconnection in semicondutor device | |
| CN101834157B (en) | Mask plate and method for manufacturing isolation structure of shallow trench by applying same | |
| KR101985937B1 (en) | Semiconductor devices and method of manufacturing the same | |
| KR20010017499A (en) | method for fabricating semiconductor device | |
| CN101383381A (en) | Semiconductor device and method of fabricating the same | |
| CN100487886C (en) | Method of manufacturing bit-line in a semiconductor device | |
| CN101188213A (en) | Making method for ditch capacitor structure | |
| CN105529335A (en) | Array substrate and fabrication method thereof and display panel | |
| CN203588976U (en) | Semiconductor element with borderless contact window |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |