CN105529335A - Array substrate and fabrication method thereof and display panel - Google Patents
Array substrate and fabrication method thereof and display panel Download PDFInfo
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- CN105529335A CN105529335A CN201510957805.XA CN201510957805A CN105529335A CN 105529335 A CN105529335 A CN 105529335A CN 201510957805 A CN201510957805 A CN 201510957805A CN 105529335 A CN105529335 A CN 105529335A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Abstract
The invention discloses an array substrate and a fabrication method thereof and a display panel. The array substrate comprises a substrate, a polysilicon channel layer, a gate insulating layer, a gate, a first interlayer insulation layer, a second interlayer insulation layer, a source and a drain, wherein the polysilicon channel layer, the gate insulating layer, the gate, the first interlayer insulation layer, the second interlayer insulation layer, the source and the drain are sequentially stacked on the substrate; the source and the drain are arranged on the second interlayer insulation layer; and one side, far away from the substrate, of the first interlayer insulation layer and one side, far away from the substrate, of the gate are located on the same plane, so that one side, far away from the substrate, of the second interlayer insulation layer is a plane; one side far away from the substrate, of the source is the plane; and one side, far away from the substrate, of the drain is also the plane. In the manner, parasitic capacitance can be reduced; and the stability of electric signal transmission is ensured.
Description
Technical field
The application relates to Display Technique field, particularly relates to a kind of array base palte and preparation method thereof, display floater.
Background technology
At present, with low-temperature polysilicon silicon technology, (English: LowTemperaturePoly-silicon is called for short: LTPS) type is main flow display panels.As shown in Figure 1, LTPS display panels to need on substrate stacked polysilicon (English: poly) channel layer 11, grid 12, for by grid 12 and source electrode 13 and drain 14 insulate between insulating barrier 15, then source electrode 13 is set on an insulating barrier 15 and drains 14.
Because polysilicon channel layer 11 and grid 12 have certain thickness, the face residing for an insulating barrier is caused to be uneven, and the masking of existing insulating barrier adopts chemical vapour deposition (CVD) (English: ChemicalVaporDeposition usually, be called for short: CVD) obtained certain thickness film, therefore cause an insulating barrier top layer to be also out-of-flatness, and then the source electrode be arranged on an insulating barrier is caused to be all uneven with drain electrode.And this out-of-flatness structure of source electrode and drain electrode can affect it electrically, produce more parasitic capacitance, cause affecting electric signal transmission unstable, affect device performance.
Summary of the invention
The application provides a kind of array base palte and preparation method thereof, display floater, can reduce parasitic capacitance, ensures the stability of electric signal transmission.
The application's first aspect provides a kind of array base palte, comprise substrate and be sequentially stacked in polysilicon channel layer on described substrate, gate insulation layer, grid, first insulating barrier, second insulating barrier, and the source electrode be arranged on described second insulating barrier and drain electrode; Described gate insulation layer is by described polysilicon channel layer and gate insulator, and described source electrode and described drain electrode are all connected with described polysilicon channel layer by described second insulating barrier, first insulating barrier, gate insulation layer, and then are formed thin-film transistor with described grid; Wherein, described first insulating barrier is in same plane away from substrate side and described grid away from substrate side, make described second insulating barrier be a plane away from substrate side, described source electrode is a plane away from substrate side, and described drain electrode is also a plane away from substrate side.
Wherein, between described first insulation sides and described second, one of them of insulating barrier is insulating layer of silicon oxide, and another is silicon nitride dielectric layer.
Wherein, described substrate is also stacked with light shield layer, the first insulating barrier and the second insulating barrier, described first insulating barrier and the second insulating barrier are all between described light shield layer and described polysilicon channel layer.
Wherein, all relatively described light shield layer of described grid, polysilicon channel layer is arranged.
Wherein, described grid is formed by molybdenum layer; Described source electrode and drain electrode by molybdenum layer, aluminium lamination, the stacked formation of molybdenum layer, or described source electrode and drain electrode by molybdenum layer, the first layers of copper, the second layers of copper, the stacked formation of molybdenum layer.
Wherein, described source electrode and drain electrode upper also stacked flatness layer, the first ITO layer, passivation layer and the second ITO layer, wherein, described second ITO layer and described source electrode or drain is electrically connected.
The application's second aspect provides a kind of display floater, comprises above-described array base palte.
The application's third aspect provides a kind of manufacture method of array base palte, comprising: sequentially stacked polysilicon channel layer, gate insulation layer, grid on substrate, and wherein, described gate insulation layer is by described polysilicon channel layer and gate insulator; Described grid arranges first insulating barrier, and wherein, described first insulating barrier is in same plane away from substrate side and described grid away from substrate side; Described first insulating barrier arranges second insulating barrier, and wherein, described second insulating barrier is a plane away from substrate side; Described second insulating barrier arranges source electrode and drain electrode, wherein, described source electrode is a plane away from substrate side, and described drain electrode is also a plane away from substrate side, described source electrode and described drain electrode are all connected with described polysilicon channel layer by described second insulating barrier, first insulating barrier, gate insulation layer, and then are formed thin-film transistor with described grid.
Wherein, described first insulating barrier is set on described grid, wherein, described first insulating barrier is in conplane step away from substrate side and described grid away from substrate side and comprises: insulating barrier between forming first by chemical vapour deposition (CVD) on described grid, and makes described first insulating barrier be in same plane away from substrate side and described grid away from substrate side by exposure, development, etching.
Wherein, before the step of described sequentially stacked polysilicon channel layer, gate insulation layer, grid on substrate, described method also comprises: sequentially stacked light shield layer, the first insulating barrier and the second insulating barrier on substrate, wherein, described first insulating barrier and the second insulating barrier are all between described light shield layer and described polysilicon channel layer; Before described second insulating barrier arranges the step of source electrode and drain electrode, described method also comprises: stacked flatness layer, the first ITO layer, passivation layer and the second ITO layer on described grid and drain electrode, wherein, described second ITO layer and described source electrode or drain is electrically connected.
In such scheme, array base palte is arranged on grid and source electrode, between between drain electrode, insulating barrier comprises two-layer, and first insulating barrier is in same plane away from substrate side and described grid away from substrate side, described second insulating barrier is made to be a plane away from substrate side, and then source electrode and drain electrode are formed in the plane, therefore described source electrode is a plane away from substrate side, and described drain electrode is also a plane away from substrate side, due to this array base palte source electrode and drain electrode are all flat configuration, therefore can parasitic capacitance be reduced, and avoid air spots to make electric signal transmission unstable, thus ensure that the stability of electric signal transmission.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing display floater;
Fig. 2 is the structural representation of the application's array base palte one execution mode;
Fig. 3 is the flow chart of method for making one execution mode of the application's array base palte;
Fig. 4 a is to structural representation during first insulating barrier exposure in another embodiment of method for making of the application's array base palte;
Fig. 4 b is structural representation when developing to first insulating barrier in another embodiment of method for making of the application's array base palte;
Fig. 4 c is structural representation when etching first insulating barrier in another embodiment of method for making of the application's array base palte.
Embodiment
In below describing, in order to illustrate instead of in order to limit, propose the detail of such as particular system structure, interface, technology and so on, thoroughly to understand the application.But, it will be clear to one skilled in the art that and also can realize the application in other execution mode not having these details.In other situation, omit the detailed description to well-known device, circuit and method, in order to avoid unnecessary details hinders the description of the application.
Refer to Fig. 2, Fig. 2 is the structural representation of the application's array base palte one execution mode.In present embodiment, array base palte comprises substrate 201 and is sequentially stacked in polysilicon channel layer 202, gate insulation layer 203, grid 204, first insulating barrier 205, second insulating barrier 206 on described substrate 201, and is arranged on source electrode on described second insulating barrier 206 207 and drain electrode 208.
Wherein, first insulating barrier 205 is in same plane away from substrate side a and grid 204 away from substrate side b, described second insulating barrier 206 is made to be a plane away from substrate side c, described source electrode 207 is a plane away from substrate side d, and described drain electrode 208 is also a plane away from substrate side e.Particularly, between this first insulating barrier 205 and second, one of them of insulating barrier 206 can be silica (chemical formula: SiOx) insulating barrier, and another can be silicon nitride (chemical formula: SiNx) insulating barrier.Such as, first insulating barrier 205 is formed by silica, and second insulating barrier 206 is formed by silicon nitride; Or first insulating barrier 205 is formed by silicon nitride, second insulating barrier 206 is formed by silica.
In the present embodiment, polysilicon channel layer 202 and grid 204 insulate by gate insulation layer 203.Source electrode 207 is all connected (namely forming conductive structure) with described polysilicon channel layer 202 by second insulating barrier, 206, first insulating barrier 205, gate insulation layer 203 with drain electrode 208, and then (English: Thin-filmtransistor is called for short: TFT) to form thin-film transistor with grid 204.When grid 204 acquisition is more than or equal to the voltage of cut-in voltage, polysilicon channel layer 202 induces electronics, makes source electrode 207 and drain electrode 208 conductings.Wherein, this gate insulation layer 203 can be aluminium nitride (chemical formula: AlN) film.Substrate 201 can be the transparency carrier that glass substrate or other insulating material are formed.Described grid 204 can be formed by molybdenum (Mo) layer.Described source electrode 207 and drain electrode 208 can by molybdenum layer, aluminium lamination, the stacked formation of molybdenum layer.
In another embodiment, described source electrode 207 and drain electrode 208 are by molybdenum layer, the first layers of copper, the second layers of copper, the stacked formation of molybdenum layer.This first layers of copper obtains with the first power deposition, namely by depositing device to deposit this first layers of copper during the first power operation.Described second layers of copper obtains with the second power deposition, namely by depositing device to deposit this second layers of copper during the second power operation.And described first power is higher than described second power.What the first layers of copper due to high power deposition can improve layers of copper makes speed, and then improve the production efficiency of array base palte, but the first layers of copper can cause the waviness of local, layers of copper surface comparatively large when film forming, therefore continues to deposit on the first layers of copper to make the second lower layers of copper of power.Low power deposition effectively can improve the profile pattern of the second layers of copper, so the molybdenum layer in the second layers of copper is covered more all even complete, can prevent photoresistance from coming off.
Alternatively, substrate 201 in the present embodiment array base palte is also stacked with shading (English: LightShielding, be called for short: LS) layer 209, first insulating barrier 210 and the second insulating barrier 211, described first insulating barrier 210 and the second insulating barrier 211 all between described light shield layer 209 and described polysilicon channel layer 202, so that described light shield layer 209 is insulated.Wherein, one of them of the first insulating barrier 210 and the second insulating barrier 211 can be insulating layer of silicon oxide, and another can be silicon nitride dielectric layer.Described grid 204, polysilicon channel layer 202 can be arranged by all relatively described light shield layer 209.Such as, grid 204 and polysilicon channel layer 202 just to setting, and all arrange the upper area of light shield layer 209, and the part correspondence of source electrode 207 and drain electrode 208 is arranged on the top of grid 204.
Alternatively, also stacked flatness layer (English abbreviation: PLN) the 212, the one ITO (Chinese: tin indium oxide) layer 213, passivation layer (English abbreviation: PV) 214 and the second ITO layer 215 in described source electrode 207 and drain electrode 208.Wherein, described second ITO layer 215 is electrically connected with source electrode 207, or described second ITO layer 215 is electrically connected with drain electrode 208.
The application also provides a kind of embodiment of display floater, and specifically, this display floater comprises the array base palte in embodiment above, and and therefore not to repeat here.In a particular application, this display floater can be LTPS display panels.
Refer to Fig. 3, Fig. 3 is the flow chart of method for making one execution mode of the application's array base palte.This array base palte is the array base palte in above-described embodiment, and described method comprises:
S31: sequentially stacked polysilicon channel layer, gate insulation layer, grid on substrate, wherein, described gate insulation layer is by described polysilicon channel layer and gate insulator.
S32: arrange first insulating barrier on described grid, wherein, described first insulating barrier is in same plane away from substrate side and described grid away from substrate side.
S33: arrange second insulating barrier on described first insulating barrier, wherein, described second insulating barrier is a plane away from substrate side.
Wherein, this S33 specifically can comprise: on described grid, form first insulating barrier by chemical vapour deposition (CVD), and makes described first insulating barrier be in same plane away from substrate side and described grid away from substrate side by exposure, development, etching.As shown in fig. 4 a, first on grid 204, form thickness first insulating barrier 205 equal with grid, and apply negativity photoresistance 216 on first insulating barrier 205, and the part except grid region is exposed; As shown in Figure 4 b, what to proceed on developing away first insulating barrier 205 just to photoresistance 216, first insulating barrier 205 of grid 204 is just exposed to grid part; As illustrated in fig. 4 c, proceed etching, because etching is not to photoresistance effect, therefore only have just grid part being etched of first insulating barrier 205, finally obtain first insulating barrier 205 contour with grid 204.
S34: source electrode and drain electrode are set on described second insulating barrier, wherein, described source electrode is a plane away from substrate side, and described drain electrode is also a plane away from substrate side, described source electrode and described drain electrode are all connected with described polysilicon channel layer by described second insulating barrier, first insulating barrier, gate insulation layer, and then are formed thin-film transistor with described grid.
Wherein, one of them of this first insulating barrier between insulating barrier and second can be insulating layer of silicon oxide, and another can be silicon nitride dielectric layer.
Described source electrode and drain electrode can by molybdenum layer, aluminium lamination, the stacked formation of molybdenum layer.Or described source electrode and drain electrode are by molybdenum layer, the first layers of copper, the second layers of copper, the stacked formation of molybdenum layer.This first layers of copper obtains with the first power deposition, namely by depositing device to deposit this first layers of copper during the first power operation.Described second layers of copper obtains with the second power deposition, namely by depositing device to deposit this second layers of copper during the second power operation.And described first power is higher than described second power.
Alternatively, before above-mentioned S31, described method for making also can comprise: sequentially stacked light shield layer, the first insulating barrier and the second insulating barrier on substrate, and wherein, described first insulating barrier and the second insulating barrier are all between described light shield layer and described polysilicon channel layer;
Alternatively, after above-mentioned S34 step, described method for making also comprises: stacked flatness layer, the first ITO layer, passivation layer and the second ITO layer on described grid and drain electrode, and wherein, described second ITO layer and described source electrode or drain is electrically connected.
The above array base palte can be made up of LTPS technology.
In one embodiment, the method for making of array base palte can sequentially comprise: form substrate-> formation light shield layer-> and form the first insulating barrier, second insulating barrier and the doping of polysilicon channel layer-> passage (English: ChannelDoping)->N type doping (English: NDoping)-> formed gate insulation layer and the doping of grid->P type (English: PDoping)-> form first between insulating barrier (CVD, exposure, development, etching) and second insulating barrier (CVD)-> form source electrode and drain electrode-> and form flatness layer-> and form the first ITO layer-> and form passivation layer-> and form the second ITO layer.
In such scheme, array base palte is arranged on grid and source electrode, between between drain electrode, insulating barrier comprises two-layer, and first insulating barrier is in same plane away from substrate side and described grid away from substrate side, described second insulating barrier is made to be a plane away from substrate side, and then source electrode and drain electrode are formed in the plane, therefore described source electrode is a plane away from substrate side, and described drain electrode is also a plane away from substrate side, due to this array base palte source electrode and drain electrode are all flat configuration, therefore can parasitic capacitance be reduced, and avoid air spots to make electric signal transmission unstable, improve device performance.
The foregoing is only embodiments of the present invention; not thereby the scope of the claims of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.
Claims (10)
1. an array base palte, it is characterized in that, comprise substrate and be sequentially stacked in polysilicon channel layer on described substrate, gate insulation layer, grid, first insulating barrier, second insulating barrier, and the source electrode be arranged on described second insulating barrier and drain electrode;
Described gate insulation layer is by described polysilicon channel layer and gate insulator, and described source electrode and described drain electrode are all connected with described polysilicon channel layer by described second insulating barrier, first insulating barrier, gate insulation layer, and then are formed thin-film transistor with described grid;
Wherein, described first insulating barrier is in same plane away from substrate side and described grid away from substrate side, make described second insulating barrier be a plane away from substrate side, described source electrode is a plane away from substrate side, and described drain electrode is also a plane away from substrate side.
2. array base palte according to claim 1, is characterized in that, between described first insulation sides and described second, one of them of insulating barrier is insulating layer of silicon oxide, and another is silicon nitride dielectric layer.
3. array base palte according to claim 1, is characterized in that, described substrate is also stacked with light shield layer, the first insulating barrier and the second insulating barrier, and described first insulating barrier and the second insulating barrier are all between described light shield layer and described polysilicon channel layer.
4. array base palte according to claim 3, is characterized in that, all relatively described light shield layer of described grid, polysilicon channel layer is arranged.
5. array base palte according to claim 1, is characterized in that, described grid is formed by molybdenum layer;
Described source electrode and drain electrode by molybdenum layer, aluminium lamination, the stacked formation of molybdenum layer, or described source electrode and drain electrode by molybdenum layer, the first layers of copper, the second layers of copper, the stacked formation of molybdenum layer.
6. array base palte according to claim 1, is characterized in that, described source electrode and drain electrode upper also stacked flatness layer, the first ITO layer, passivation layer and the second ITO layer, and wherein, described second ITO layer and described source electrode or drain is electrically connected.
7. a display floater, is characterized in that, comprises the array base palte described in any one of claim 1 to 6.
8. a manufacture method for array base palte, is characterized in that, comprising:
Sequentially stacked polysilicon channel layer, gate insulation layer, grid on substrate, wherein, described gate insulation layer is by described polysilicon channel layer and gate insulator;
Described grid arranges first insulating barrier, and wherein, described first insulating barrier is in same plane away from substrate side and described grid away from substrate side;
Described first insulating barrier arranges second insulating barrier, and wherein, described second insulating barrier is a plane away from substrate side;
Described second insulating barrier arranges source electrode and drain electrode, wherein, described source electrode is a plane away from substrate side, and described drain electrode is also a plane away from substrate side, described source electrode and described drain electrode are all connected with described polysilicon channel layer by described second insulating barrier, first insulating barrier, gate insulation layer, and then are formed thin-film transistor with described grid.
9. manufacture method according to claim 8, is characterized in that, describedly on described grid, arranges first insulating barrier, and wherein, described first insulating barrier is in conplane step away from substrate side and described grid away from substrate side and comprises:
On described grid, form first insulating barrier by chemical vapour deposition (CVD), and make described first insulating barrier be in same plane away from substrate side and described grid away from substrate side by exposure, development, etching.
10. manufacture method according to claim 8 or claim 9, is characterized in that, before the step of described sequentially stacked polysilicon channel layer, gate insulation layer, grid on substrate, described method also comprises:
Sequentially stacked light shield layer, the first insulating barrier and the second insulating barrier on substrate, wherein, described first insulating barrier and the second insulating barrier are all between described light shield layer and described polysilicon channel layer;
After described second insulating barrier arranges the step of source electrode and drain electrode, described method also comprises:
Stacked flatness layer, the first ITO layer, passivation layer and the second ITO layer on described grid and drain electrode, wherein, described second ITO layer and described source electrode or drain is electrically connected.
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Application publication date: 20160427 |