CN1255872C - Semiconductor module possessing drain electrode with light adulteration and forming method - Google Patents
Semiconductor module possessing drain electrode with light adulteration and forming method Download PDFInfo
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- CN1255872C CN1255872C CN 02149953 CN02149953A CN1255872C CN 1255872 C CN1255872 C CN 1255872C CN 02149953 CN02149953 CN 02149953 CN 02149953 A CN02149953 A CN 02149953A CN 1255872 C CN1255872 C CN 1255872C
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Abstract
The present invention provides a semiconductor module provided with a lightly doped drain and a forming method thereof. The method of the present invention comprises the steps: a semiconductor substrate is provided and has a first region and a second region; secondly, a gate dielectric layer and a conductor layer are orderly formed on the semiconductor substrate; thirdly, part of the conductor layer is selectively removed so as to form a first gate on the gate dielectric layer corresponding to the first region, and the residual part of the conductor layer is substantially positioned above the second region; the first region is doped with a first conducting type first dopant; fourthly, a gap wall is formed on the side wall of the first gate; the first region is doped with a first conducting type second dopant so as to form a first type thin film transistor; fifthly, a patterned photoresistive layer is formed on the semiconductor substrate, and the conductor layer corresponding to the second gate on the second region is defined; the patterned photoresistive layer is used as a mask to remove part of the conductor layer corresponding to the second region so as to form a second gate on the gate dielectric layer corresponding to the second region; the second region is doped with a second conducting type dopant so as to form a second type thin film transistor.
Description
Technical field
The invention relates to a kind of semiconductor subassembly and forming method thereof, particularly relevant for thin-film transistor of a kind of tool lightly doped drain and forming method thereof.
Background technology
General semiconductor device has the effect that various circuit is controlled semiconductor device usually, and thin-film transistor is one of assembly indispensable in the middle of the circuit.With the LCD is example, and thin-film transistor is commonly used to the switch as the effect of control pixel, also is applied in the design of drive circuit simultaneously.
Yet along with thin-film transistor because of after channel length shortens, can produce a kind of phenomenon of thermoelectronic effect, seriously influenced the operation of thin-film transistor.For example, be positioned at the contiguous highfield in drain region of thin-film transistor, can cause the situation of high leakage current usually.In order to suppress the size of these electric fields, prior art has proposed grid structure (offset gate structure) and the multi grid (multi-gate structure) of lightly doped drain (lightly doped drain) structure, biasing.Lightly doped drain technology wherein, for the semiconductor industry generally in order to the application of the leakage current of the opening (on-state) that reduces thin-film transistor.
The existing semiconductor subassembly that adds the design of lightly doped drain zone, needing usually increases the shielding of making thin-film transistor, has increased the complexity and the cost of technology.And if the shielding misalignment (misalignment) that the lightly doped drain ion injects is when situation exists, the length in the lightly doped drain zone of thin film transistor channel (channel) both sides is difference to some extent.Therefore, in thin-film transistor-LCD technology, what Continual Improvement photoetching (photolithography) was aimed at accurately shields number with minimizing, is very important problem.
Existing technology is normally at the grid of etching n type thin-film transistor, when carrying out mixing the first time, utilizes same photoresistance to carry out the etching step of grid undercut, in order to simplify the number of light shield, as U.S. Patent number 6,306, shown in 693.Yet the etch process parameters of grid undercut is wayward, can't effectively control the etched consistency of undercutting.Therefore, in follow-up implantation step, make the length in lightly doped drain zone also can't control effectively.In view of this, be necessary to provide a kind of method that forms semiconductor subassembly, in order to improving the controllability of lightly doped drain zone length, and can simplify processing step simultaneously.
Summary of the invention
An aspect of of the present present invention is to provide a kind of semiconductor subassembly of tool lightly doped drain, and its grid has a clearance wall, and the different situation of lightly doped drain length is avoided in the shielding when can be used as lightly doped drain formation.
Another aspect of the present invention is to provide a kind of method that forms semiconductor subassembly, the different situation of lightly doped drain length that the shielding misalignment when it can avoid photoetching is caused.
Another aspect of the present invention is to provide a kind of method that forms the thin-film transistor of tool lightly doped drain, and it utilizes clearance wall to produce the shielding of aiming at voluntarily, can avoid shielding the situation of misalignment.
Another aspect of the present invention is to provide a kind of method that forms the driving/control circuit of liquid crystal indicator, it utilizes the grid definition process and the clearance wall of different conductivity type thin-film transistor, forms the drive circuit and the pixel control circuit of tool lightly doped drain with the processing step of simplifying.
The inventive method comprises provides the semiconductor ground, has a first area and a second area, respectively in order to form one first type and one second type thin-film transistor.Form a gate dielectric on semiconductor substrate, and form a conductor layer on gate dielectric.Optionally remove the conductor layer of a part, in order to forming a first grid on the gate dielectric of first area correspondence, and the remaining part of conductor layer is positioned at the second area top in fact.Then, mix one first doping of one first conductivity type in the first area.Form the sidewall of a clearance wall at first grid.Afterwards, one second doping of first conductivity type that mixes is in the first area, in order to form the first type thin-film transistor.Form a patterning photoresist layer above semiconductor substrate, it defines the conductor layer of a second grid in the second area correspondence.Utilize the patterning photoresist layer to be mask, remove the some of the conductor layer of second area correspondence, in order to form second grid on the gate dielectric of second area correspondence.Then, mix one second conductivity type doping in second area, in order to form the second type thin-film transistor.
The present invention provides a kind of semiconductor subassembly of tool lightly doped drain simultaneously, and it comprises the semiconductor ground and has a first area and a second area, one first transistor npn npn is to be formed at the first area, and one second transistor npn npn is to be formed at second area.First transistor npn npn and second transistor npn npn are to comprise regions and source respectively to be formed in the semiconductor substrate, and regions and source is separated by a channel region.One gate dielectric is to be positioned on the semiconductor substrate, and covers channel region.Grid is to should first channel region, is positioned on the gate dielectric.In addition, first transistor npn npn comprises a clearance wall and lightly doped region.Clearance wall is the sidewall that is formed at grid, and is positioned on the gate dielectric.Lightly doped region is corresponding clearance wall, is positioned at the some of regions and source.
Description of drawings
Fig. 1 is the profile that embodiments of the invention form conductor layer;
Fig. 2 is the profile that embodiments of the invention form the photoresist layer of definition first grid;
Fig. 3 is the profile that embodiments of the invention form first grid;
Fig. 4 is the profile that embodiments of the invention inject a n type ion;
Fig. 5 is the profile that embodiments of the invention form conformal dielectric layer;
Fig. 6 is the profile that embodiments of the invention inject the 2nd n type ion;
Fig. 7 is the profile that embodiments of the invention form the photoresist layer of a fixed second grid;
Fig. 8 is the profile that embodiments of the invention inject p type ion;
Fig. 9 is the profile that embodiments of the invention form the semiconductor subassembly of tool n type and p type thin-film transistor.
Embodiment
The present invention discloses semiconductor subassembly of a kind of tool lightly doped drain and forming method thereof, in order to improve the different phenomenon of drain electrode length and to simplify processing step.In order to make narration of the present invention more detailed and complete, can be with reference to the icon of following description and cooperation Fig. 1 to Fig. 9.
Shown in a specific embodiment, the inventive method is in order to form semiconductor assembly, for example driving of LCD/pixel control circuit.With reference to figure 1, the inventive method comprises provides semiconductor ground 100, silicon base material for example, or as be formed at silicon layer on the insulating substrate or any semiconductor material layer.Semiconductor substrate 100 is to comprise a first area 110 and a second area 120 at least, respectively in order to form one first type and one second type thin-film transistor, as n type thin-film transistor and p type thin-film transistor.Semiconductor substrate 100 is that a silicon layer 102 is formed on the insulating barrier 104 as illustrated in Figure 1, and insulating barrier 104 is to comprise an oxide layer, is formed on a quartz substrate or the glass baseplate (106).First area 110 is drive area (driver area) 200 and the pixel regions (pixel area) 300 that are illustrated in semiconductor subassembly.Second area 120 is the drive areas 200 that are illustrated in semiconductor subassembly.
Then, form a gate dielectric (gate dielectric layer) 112 on semiconductor substrate 100.This gate dielectric 112 can be a silicon nitride layer, one silica layer or its mixed layer, and it can utilize thermal oxidation method or deposition technique to be formed on the semiconductor substrate 100.Afterwards, form a conductor layer 114 on gate dielectric 112.This conductor layer 114 can be the material layer of polysilicon layer or other tool electric action, and its formation method comprises depositional mode.Then, optionally remove the conductor layer 114 of a part, in order to forming a first grid 118 on this gate dielectric 112 of first area 110 correspondences, and conductor layer 114 remaining parts are positioned at second area 120 tops in fact, as shown in Figure 3.
With reference to figure 2, the conductor layer 114 of optionally removing part comprises formation one photoresist layer 116 on conductor layer 114 in order to the step that forms this first grid.Patterning photoresist layer 116 makes photoresist layer define the conductor layer 114 of first grid 118 in the first area correspondence.The method that forms photoresist layer 116 and patterning photoresist layer 116 can be utilized traditional photoetching technique, utilizes coating, exposure and step of developing to finish.Then, be mask with photoresist layer 116, etched conductors layer 114 forms the conductor layer 114 of a design transfer in order to expose gate dielectric 112.Make one first of conductor layer 114 partly form first grid 118, and one second part of conductor layer 114 is positioned at second area 120 tops in fact.Then, remove photoresist layer, as shown in Figure 3.
With reference to figure 4, be mask with the conductor layer 114 of design transfer, one first doping of one first conductivity type that mixes is in first area 110.For example, with first grid 118 that is positioned at first area 110 and the residue conductor layer 114 that is positioned at second area 120 is mask, ion injects the doping of a n type in the silicon layer 102 of the semiconductor substrate 100 of first area 110, in order to form at least one lightly doped region 122.The doping of the one n type is as phosphorus, arsenic or similar material.
Afterwards, form a conformal dielectric layer 124 in semiconductor substrate 100 tops, as shown in Figure 5.The anisotropic etching conformal dielectric layer 124 then, in order to form a clearance wall 126 in the sidewall of first grid 118, as shown in Figure 6.Then, mix one second doping of first conductivity type in first area 110.Be mask with first grid 118 and clearance wall 126 for example, ion injects one the 2nd n type doping in the silicon layer 102 of the semiconductor substrate 100 of first area 110, in order to form at least one heavily doped region 128.And heavily doped region 128 is overlapping with lightly doped region 122 parts.Thus, because the shielding of the symmetry of clearance wall 126 makes the n type thin-film transistor that forms have the lightly doped drain 122 with length, as shown in Figure 6.The doping of the 2nd n type is as phosphorus, arsenic or similar material.It is noted that at this first doping of first conductivity type and second doping of first conductivity type can be different dopings or same doping.For example, the doping of first and second n type can be all phosphorus or be respectively phosphorus and arsenic.
With reference to figure 7, form a patterning photoresist layer 130 in semiconductor substrate 100 tops, it defines the conductor layer 114 of a second grid 132 in second area 120 correspondences.Utilize patterning photoresist layer 130 to be mask then, remove the some of the conductor layer 114 of second area 120 correspondences, in order to form second grid 132 on the gate dielectric 112 of second area 120 correspondences, as shown in Figure 8.Afterwards, mix one second conductivity type doping in second area 120.For example the patterning photoresist layer 130 with second grid 132 and definition second grid is a mask, ion injects the doping of p type in the silicon layer 102 of the semiconductor substrate 100 of second area 120, in order to form at least one doped region 134, finish p type thin-film transistor.Remove patterning photoresist layer 130 then, as shown in Figure 9.
In addition, the inventive method more comprises technologies (not icon) such as forming electric capacity, contact, online circuit and pixel contact, with driving/pixel control circuit of finishing LCD.In addition, though the driving/pixel control circuit explanation of the embodiment of the invention to form LCD, the inventive method can be applicable to form the semiconductor subassembly of other tool lightly doped drain, does not exceed with the illustrated assembly of embodiment.
Refer again to Fig. 9, the present invention provides a kind of semiconductor subassembly 400 of tool lightly doped drain simultaneously, its comprise semiconductor substrate 100 be have first area 110 and second area 120, first transistor npn npn 410 is to be formed at first area 110, and second transistor npn npn 420 is to be formed at second area 120.As previously mentioned, semiconductor substrate 100 can be the silicon layer of individual layer, or comprises the base material of silicon layer 102, insulating barrier 104 and quartz or glass baseplate (106) composition.First transistor npn npn 410 and second transistor npn npn 420 are respectively n type and p type thin-film transistor, can be distributed in the drive area 200 or the pixel region 300 of semiconductor substrate 100 according to the demand of circuit design.
It is to be formed in the semiconductor substrate 100 that first transistor npn npn 410 comprises first regions and source 412, and first regions and source 412 is separated by first channel region 414.First grid dielectric layer 112 is positioned on the semiconductor substrate 100 and covers first channel region 414.First grid 118, corresponding first channel region 414 is positioned on the first grid dielectric layer 112.Clearance wall 126 is formed at the sidewall of first grid 118, and is positioned on the first grid dielectric layer 112.Lightly doped region 122 corresponding clearance walls 126 are positioned at the some of first regions and source 414.Also promptly first regions and source 412 comprises heavily doped region 128 and lightly doped region 122.
Second transistor npn npn 420 comprises second regions and source 134 and is formed in the semiconductor substrate 100, and second regions and source 134 is separated by second channel region 422.Second grid dielectric layer 112 is positioned on the semiconductor substrate 100, and covers second channel region 422.Second grid 132 corresponding second channel regions 422 are positioned on the second grid dielectric layer 112.As shown in Figure 9, in an embodiment, first grid dielectric layer and second grid dielectric layer are the gate dielectrics 112 that forms simultaneously.Second regions and source is a doped region 134.
The above is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the claim scope of the present invention.
Description of reference numerals
100 semiconductor substrate, 102 silicon layers
104 insulating barriers, 106 quartz substrate or glass baseplate
112 gate dielectrics (or first/second grid dielectric layer)
114 conductor layers
116 photoresist layers, 118 first grids
122 lightly doped regions, 124 conformal dielectric layer
126 clearance walls, 128 heavily doped regions
130 patterning photoresist layers, 132 second grids
134 doped regions or second regions and source/drain
110 first areas, 120 second areas
200 drive areas, 300 pixel regions
400 semiconductor subassemblies, 410 first transistor npn npns
412 first regions and source, 414 first channel regions
420 second transistor npn npns, 422 second channel regions
Claims (10)
1. method that forms semiconductor subassembly, described semiconductor subassembly comprises one first type thin-film transistor and one second type thin-film transistor, it is characterized in that, said method comprising the steps of:
The semiconductor ground is provided, and is to have a first area and a second area;
Form a gate dielectric on described semiconductor substrate;
Form a conductor layer on described gate dielectric;
Optionally remove the described conductor layer of a part, in order to forming a first grid on the described gate dielectric of described first area correspondence, and the remaining part of described conductor layer is positioned at described second area top;
Mix one first doping of one first conductivity type in described first area;
Form the sidewall of a clearance wall at described first grid;
Mix one second doping of described first conductivity type in described first area, in order to form the described first type thin-film transistor;
Form a patterning photoresist layer above described semiconductor substrate, described patterning photoresist layer defines the described conductor layer of a second grid in described second area correspondence;
Utilize described patterning photoresist layer to be mask, remove the some of the described conductor layer of described second area correspondence, in order to form described second grid on the gate dielectric of described second area correspondence; And
Mix one second conductivity type doping in described second area, in order to form the described second type thin-film transistor.
2. the method for claim 1, it is further characterized in that the described conductor layer of optionally removing described part comprises in order to the step that forms described first grid:
Form a photoresist layer on described conductor layer;
The described photoresist layer of patterning makes described photoresist layer define the described conductor layer of described first grid in described first area correspondence; And
With described photoresist layer is mask, and the described conductor layer of etching make that one first of described conductor layer partly forms described first grid, and one second part of described conductor layer is positioned at described second area top in order to expose described gate dielectric.
3. the method for claim 1, it is further characterized in that, the first doping step of described first conductivity type of mixing comprises: with described first grid is mask, and ion injects one the one n type doping in described first area, in order to form at least one lightly doped region.
4. method as claimed in claim 3, it is further characterized in that, the second doping step of described first conductivity type of mixing comprises: with described first grid and described clearance wall is mask, ion injects one the 2nd n type doping in described first area, in order to forming at least one heavily doped region, and described heavily doped region and a described lightly doped region part are overlapping.
5. the method for claim 1, it is further characterized in that first doping of described first conductivity type and second doping of described first conductivity type are two kinds of dopings.
6. the method for claim 1, it is further characterized in that first doping of described first conductivity type and second doping of described first conductivity type are with a kind of doping.
7. method as claimed in claim 6, it is further characterized in that the described second conductivity type doping is a p type doping.
8. method as claimed in claim 6, it is further characterized in that, the doping step of described second conductivity type of mixing comprises: with described second grid and described patterning photoresist layer is mask, and ion injects the doping of p type in described second area, in order to form at least one doped region.
9. the method for claim 1, it is further characterized in that the step that forms described clearance wall comprises: form a conformal dielectric layer above described semiconductor substrate; And
The described conformal dielectric layer of anisotropic etching is in order to form the sidewall of described clearance wall at described first grid.
10. the method for claim 1, it is further characterized in that described gate dielectric is selected by a silicon nitride layer, one silica layer and mixed layer thereof.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02149953 CN1255872C (en) | 2002-11-08 | 2002-11-08 | Semiconductor module possessing drain electrode with light adulteration and forming method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02149953 CN1255872C (en) | 2002-11-08 | 2002-11-08 | Semiconductor module possessing drain electrode with light adulteration and forming method |
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| CN1499610A CN1499610A (en) | 2004-05-26 |
| CN1255872C true CN1255872C (en) | 2006-05-10 |
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| CN104465702B (en) * | 2014-11-03 | 2019-12-10 | 深圳市华星光电技术有限公司 | Manufacturing method of AMOLED (active matrix/organic light emitting diode) backboard |
| CN106531044B (en) * | 2015-09-11 | 2019-09-03 | 南京瀚宇彩欣科技有限责任公司 | Display panel and its gate drive circuit |
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