CN1251304C - Manufacturing process of integrated aligning mark and channel component element - Google Patents
Manufacturing process of integrated aligning mark and channel component element Download PDFInfo
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- CN1251304C CN1251304C CN 03121243 CN03121243A CN1251304C CN 1251304 C CN1251304 C CN 1251304C CN 03121243 CN03121243 CN 03121243 CN 03121243 A CN03121243 A CN 03121243A CN 1251304 C CN1251304 C CN 1251304C
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- groove
- alignment mark
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Abstract
The present invention discloses a process for manufacturing an integrated aligning mark and a channel component. Firstly, a substrate with a first groove and a substrate with a second groove are arranged, wherein the second groove is used as the aligning mark and the width of the second groove is larger than that of the first groove. Then, a groove component is respectively formed on the lower half part of the first groove and the lower half part of the second groove. A first conducting layer is formed on a groove capacitor in the groove. Subsequently, a second conducting layer is formed on the substrate and is filled in the first groove. The second conducting layer is simultaneously formed on an inner surface of the second groove by compliance. Finally, the second conducting layer is reetched to completely remove the second conducting layer of the second groove and the partial first conducting layer. Simultaneously, partial second conducting layer is kept in the first groove.
Description
Technical field
The invention relates to a kind of manufacture of semiconductor, particularly relevant for a kind of processing procedure of integrating alignment mark and groove assembly, to simplify processing procedure and to reduce manufacturing cost.
Background technology
In semiconductor integrated circuit was made, lithographic process was a critical processes.Lithographic process be in order to design transfer to film, or before carrying out ion disposing process, form required mask layer.
Generally speaking, in the semiconductor integrated circuit manufacture process, need carry out lithographic process repeatedly, yet in the lithographic process step, the aligning of pattern (alignment) is a key step.When making the pattern of different layers on wafer, wafer must be accurately in alignment with previous pattern.Traditionally, (alignment mark AM) is to use aligning operation before implementing exposure program to alignment mark.
Alignment mark when the substrate in patterned assembly district or suprabasil film, is formed at outside the assembly district, for example the Cutting Road of wafer (scribe line) usually simultaneously.Below cooperate Fig. 1 a that the processing procedure of known integration alignment mark and groove assembly is described to Fig. 1 d.At first, please refer to Fig. 1 a, provide a substrate 100, for example a Silicon Wafer.This substrate 100 has an assembly district 10 and an alignment mark district 20, and wherein alignment mark regions 20 is the Cutting Roads that are positioned at wafer.
Then, form the mask layer 105 of a patterning on substrate 100 surfaces, it is made up of a pad silicon oxide layer 102 and a silicon nitride layer 104.Afterwards, by the mask layer 105 of patterning as etching mask, with etching substrate 200 respectively in assembly district 10 and alignment mark regions 420 form plural deep trench.For simplicity of illustration, herein only in assembly district 10 and alignment mark regions 20 respectively illustrate a deep trench 110a and a 110b.Wherein, the width of deep trench 110b is greater than deep trench 110a.
Next, form channel capacitor 118a and 118b at deep trench 110a and 110b Lower Half respectively, it comprises top electrode 116a and 116b, capacitance dielectric layer 114a and 114b and bottom electrode 112a and 112b.Then, deep trench 110a above channel capacitor 118a and 118b and 110b sidewall form a neck ring insulating barrier 117a and a 117b respectively.Afterwards, in deep trench 110a and 110b, form conductive layer 120a and 120b, for example polysilicon layer respectively.The height of conductive layer 120a and 120b is identical with neck ring insulating barrier 117a and 117b substantially.
Next, on mask layer 105, form another conductive layer 122, polysilicon layer for example, and insert deep trench 110a and 120b.
Next, please refer to Fig. 1 b, (chemical mechanic polishing CMP), and stays conductive layer 122a and 122b partly at deep trench 110a and 110b respectively as the grinding stop layer conductive layer 122 to be implemented cmp processing with mask layer 105.
Next, please refer to Fig. 1 c, etch-back conductive layer 122a and 122b are to stay conductive layer 124a and 124b partly at deep trench 110a and 110b respectively.Conductive layer 120a among the deep trench 110a and 124a are the conductor layers as channel capacitor 118a.Deep trench 110b and channel capacitor 118b wherein and conductive layer 120b and 124b are as alignment mark.
Owing to be formed with channel capacitor 118b and conductive layer 120b and 124b among the deep trench 110b, reduce alignment mark regions 10 substrate 100 height fall and reduce the image contrast (contrast) of alignment mark.Therefore, please refer to Fig. 1 d, on mask layer 105, form a photoresist pattern layer (not illustrating) by lithographic process and only expose deep trench 110b to cover deep trench 110a fully.Afterwards, utilize the neck ring insulating barrier 117b of photoresist pattern layer removes conductive layer 124b and part fully with etching as mask conductive layer 120b and part and stay the conductive layer 120c of part and the neck ring insulating barrier 117c of part, so as to the height fall of the substrate 100 that increases alignment mark regions 10.
Yet above-mentioned processing procedure is too complicated, thereby increases manufacturing cost and time and reduce production capacity.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of processing procedure of integrating alignment mark and groove assembly, so as to simplifying fabrication steps, and then reduce cost of manufacture and the time increases production capacity simultaneously.
According to above-mentioned purpose, the invention provides a kind of processing procedure of integrating alignment mark and groove assembly.At first, provide substrate with one first groove and one second groove.Wherein, second groove is greater than first groove as alignment mark and its width.Then, respectively form a groove assembly, form one first conductive layer again on the channel capacitor in groove in first and second lower half part of groove.Afterwards, in substrate, form one second conductive layer and insert first groove and form this second conductive layer in the second grooved inner surface compliance simultaneously.At last, etch-back second conductive layer with second conductive layer and the first a part of conductive layer of removing second groove fully, and stays second conductive layer partly simultaneously in first groove.Wherein, said method more is included in the preceding enforcement one cmp treatment step of etch-back second conductive layer, to remove this suprabasil this second conductive layer.
Moreover first conductive layer can be a polysilicon layer and its thickness scope at 2000 to 4000 dusts.Second conductive layer can be a polysilicon layer and its thickness scope at 2000 to 4000 dusts.
Description of drawings
Fig. 1 a is the generalized section that shows the processing procedure of known integration alignment mark and groove assembly to Fig. 1 d.
Fig. 2 a is the generalized section that shows according to the processing procedure of the integration alignment mark of the embodiment of the invention and groove assembly to Fig. 2 f.
The figure number explanation:
10-assembly district; The 20-alignment mark regions;
The 100-substrate; 102-pad silicon oxide layer;
The 104-silicon nitride layer; The 105-mask layer;
110a, 110b-groove; 112a, 112b-bottom electrode;
114a, 114b-capacitance dielectric layer; 116a, 116b-top electrode;
117a, 117b, 117c-neck ring insulating barrier; 118a, 118b-channel capacitor;
120a, 120b, 120c, 122,122a, 122b, 124a, 124b-conductive layer;
30-assembly district; The 40-alignment mark regions;
The 200-substrate; 202-pad silicon oxide layer;
The 204-silicon nitride layer; The 205-mask layer;
The 206-photoresist layer; 208a, 208b-opening;
210a, 210b-groove; 212a, 212b-bottom electrode;
214a, 214b-capacitance dielectric layer; 216a, 216b-top electrode;
217a, 217b, 217c-neck ring insulating barrier; 218a, 218b-channel capacitor;
220a, 220b, 220c, 222,222a, 222b, 222c-conductive layer.
Embodiment
Below cooperate Fig. 2 a to the integration alignment mark of Fig. 2 f explanation embodiment of the invention and the processing procedure of groove assembly.At first, please refer to Fig. 2 a, provide a substrate 200, for example a Silicon Wafer.This substrate 200 has an assembly district 30 and an alignment mark district 40, and wherein alignment mark regions 30 is the Cutting Roads (scribe line) that are positioned at wafer.
Then, form a mask layer 205 on substrate 200 surfaces, it can be the stack architecture of single layer structure or several layers.As shown in FIG., mask layer 205 is preferably by the thicker silicon nitride layer 204 of one deck pad silicon oxide layer 202 and one deck and is formed.Wherein, about about 100 dusts of thickness () of pad silicon oxide layer 202, and its formation method can be thermal oxidation method or (low pressure chemical vapordeposition, LPCVD) deposition forms with known normal pressure (atmospheric) or Low Pressure Chemical Vapor Deposition.In the scope of the thickness that fills up the silicon nitride layer 204 on the silicon oxide layer 202, and can utilize Low Pressure Chemical Vapor Deposition, with dichlorosilane (SiCl about 1000 to 2000 dusts
2H
2) and ammonia (NH
3) form for reaction raw materials deposits.
Then, on mask layer 205 surfaces, form one deck photoresist layer 206.Afterwards, form plural opening 208a and 208b in 206 by the conventional photolithographic processing procedure in photoresist layer.Wherein, opening 208a is positioned at 30 tops, assembly district and opening 208b is positioned at alignment mark regions 40 tops, and the width of opening 208b is greater than opening 208a.Come mask layer 205 is carried out the anisotropic etching processing procedure as mask with photoresist layer 206, for example (reactive ion etching RIE) is transferred to opening 208a and 208b in the mask layer 205 and substrate 200 surfaces of exposed portions serve reactive ion etching.
Next, please refer to Fig. 2 b, remove after the photoresist layer 206 with suitable etching solution or ashing treatment, by mask layer 205 as etching mask, carry out the anisotropic etching processing procedure, reactive ion etching for example, with the substrate 200 with the opening below of mask layer 205 be etched to a desired depth and respectively in assembly district 30 and alignment mark regions 40 form plural deep trench.For simplicity of illustration, herein only in assembly district 30 and alignment mark regions 40 respectively illustrate a deep trench 210a and a 210b.Similarly, the width of deep trench 210b is greater than deep trench 210a.
Next, please refer to Fig. 2 c, utilize known method to form groove assembly 218a and 218b at deep trench 210a and 210b Lower Half respectively.In the present embodiment, groove assembly 218a and 218b are as example with channel capacitor.Channel capacitor 218a and 218b comprise top electrode 216a and 216b, capacitance dielectric layer 214a and 214b and bottom electrode 212a and 212b.Bottom electrode 212a and 212b are surrounded in the substrate 200 of Lower Half deep trench 210a and 210b. Top electrode 216a and 216b are arranged among the deep trench 210a and 210b of Lower Half, and it can be made of polysilicon.Capacitance dielectric layer 214a and 214b are arranged between bottom electrode 212a and 212b and top electrode 216a and the 216b.
Then, deep trench 210a above channel capacitor 218a and 218b and 210b sidewall form neck ring insulating barrier 217a and the 217b by silica constituted.Afterwards, by conventional deposition technique, chemical vapor deposition (CVD) for example forms a conductive layer (not illustrating) on mask layer 205, polysilicon layer for example, and insert among deep trench 210a and the 210b.The above-mentioned conductive layer of etch-back is to stay the conductive layer 220a and the 220b of part respectively in deep trench 210a and 210b.The height of conductive layer 220a and 220b is identical with neck ring insulating barrier 217a and 217b substantially, and its thickness is in the scope of 2000 to 4000 dusts.
Next, please refer to Fig. 2 d, carry out committed step of the present invention to Fig. 2 f.In Fig. 2 d, by conventional deposition technique, CVD for example forms another conductive layer 222 on the mask layer 205 in assembly district 30, polysilicon layer for example, and insert deep trench 210a.Simultaneously, conductive layer 222 mask layer 205 and the compliance that also are formed at alignment mark regions 40 is formed at deep trench 210b inner surface.In the present embodiment, conductive layer 222 thickness are in the scope of 2000 to 4000 dusts.
Next, please refer to Fig. 2 e, conductive layer 222 is implemented a milled processed, for example cmp is handled (CMP), and stays conductive layer 222a and 222b partly at deep trench 210a and 210b with mask layer 205 respectively as grinding stop layer.
At last, please refer to Fig. 2 f, come etch-back conductive layer 222a and 222b by isotropic etching.In this step, removed the conductive layer 222b of alignment mark regions 40 fully and removed the conductive layer 220b of part and the neck ring insulating barrier 217b of part and stay the conductive layer 220c of part and neck ring insulating barrier 217c and finish the making of alignment mark.Herein, the purpose of removing conductive layer 222b fully is to make substrate 200 height falls of alignment mark regions 40 and increases the image contrast (contrast) of alignment mark in lithographic process.Simultaneously, in this step, can remove in the assembly district 30 the conductive layer 222a of part equally and stay the conductive layer 222c of part.Herein, conductive layer 222c and conductive layer 220a are the conductor layers as channel capacitor 218a.
In addition, be noted that, owing to conductive layer 222 be compliance to be formed at its inner surface be not to fill up deep trench 210b fully, therefore can directly carry out above-mentioned isotropic etching and need not before etching, to carry out above-mentioned milled processed, so as to further simplification fabrication steps.
The method according to this invention, the conductive layer 222 that is positioned at alignment mark regions can be removed fully via isotropic etching.Use etch process and a lithographic process of at least twice in the known techniques, can simplify fabrication steps effectively and reduce cost of manufacture and manufacturing time, increase production capacity simultaneously.
Claims (17)
1. a processing procedure of integrating alignment mark and groove assembly comprises the following steps:
One substrate is provided, and it has an assembly district and an alignment mark district;
Form at least one first groove in this assembly district and form at least one second groove in this alignment mark regions simultaneously, wherein the width of this second groove is greater than this first groove;
Respectively form a channel capacitor in this first and second lower half part of groove;
Form one first polysilicon layer on this channel capacitor in these grooves;
In the substrate in this assembly district, form one second polysilicon layer and insert this first groove and form this second polysilicon layer in substrate and this second grooved inner surface compliance of alignment mark regions simultaneously; And
This second polysilicon layer of etch-back removing this second polysilicon layer in this alignment mark regions and this first polysilicon layer of a part fully, and stays simultaneously this second polysilicon layer of part in this assembly district.
2. the processing procedure of integration alignment mark according to claim 1 and groove assembly, wherein this substrate is that a Silicon Wafer and this alignment mark regions are the Cutting Roads that is positioned at this wafer.
3. the processing procedure of integration alignment mark according to claim 1 and groove assembly, wherein this channel capacitor comprises:
One bottom electrode is surrounded in this substrate of groove of this Lower Half;
One top electrode is arranged in the groove of this Lower Half; And
One capacitance dielectric layer is arranged between this bottom electrode and this top electrode.
4. the processing procedure of integration alignment mark according to claim 1 and groove assembly, wherein the thickness of this first polysilicon layer is in the scope of 2000 to 4000 dusts.
5. the processing procedure of integration alignment mark according to claim 1 and groove assembly, wherein the thickness of this second polysilicon layer is in the scope of 2000 to 4000 dusts.
6. the processing procedure of integration alignment mark according to claim 1 and groove assembly more is included in this second polysilicon layer of etch-back and implements a milled processed step before, to remove this suprabasil this second polysilicon layer.
7. the processing procedure of integration alignment mark according to claim 6 and groove assembly, wherein this milled processed is that a cmp is handled.
8. a processing procedure of integrating alignment mark and groove assembly comprises the following steps:
One substrate is provided, and it has one first groove and one second groove, wherein this second groove be in order to as this alignment mark and its width greater than this first groove;
This first and this second lower half part of groove respectively form this groove assembly;
Form one first conductive layer on this groove assembly in these grooves;
In substrate, form one second conductive layer and insert this first groove and form this second conductive layer in this second grooved inner surface compliance simultaneously; And
This second conductive layer of etch-back with this second conductive layer and this a part of first conductive layer of removing this second groove fully, and stays this second conductive layer partly simultaneously in this first groove.
9. the processing procedure of integration alignment mark according to claim 8 and groove assembly, wherein this substrate is a silicon base.
10. the processing procedure of integration alignment mark according to claim 8 and groove assembly, wherein this groove assembly is a channel capacitor.
11. the processing procedure of integration alignment mark according to claim 10 and groove assembly, wherein this channel capacitor comprises:
One bottom electrode is surrounded in this substrate of channel bottom of this Lower Half;
One top electrode is arranged in the groove of this Lower Half; And
One capacitance dielectric layer, be arranged at that the groove of this Lower Half and this power on and between.
12. the processing procedure of integration alignment mark according to claim 8 and groove assembly, wherein this first conductive layer is a polysilicon layer.
13. the processing procedure of integration alignment mark according to claim 12 and groove assembly, wherein the thickness of this first conductive layer is in the scope of 2000 to 4000 dusts.
14. the processing procedure of integration alignment mark according to claim 8 and groove assembly, wherein this second conductive layer is a polysilicon layer.
15. the processing procedure of integration alignment mark according to claim 14 and groove assembly, wherein the thickness of this second conductive layer is in the scope of 2000 to 4000 dusts.
16. the processing procedure of integration alignment mark according to claim 8 and groove assembly more is included in this second conductive layer of etch-back and implements a milled processed step before, to remove this suprabasil this second conductive layer.
17. the processing procedure of integration alignment mark according to claim 16 and groove assembly, wherein this milled processed is that a cmp is handled.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03121243 CN1251304C (en) | 2003-03-28 | 2003-03-28 | Manufacturing process of integrated aligning mark and channel component element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03121243 CN1251304C (en) | 2003-03-28 | 2003-03-28 | Manufacturing process of integrated aligning mark and channel component element |
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|---|---|
| CN1534729A CN1534729A (en) | 2004-10-06 |
| CN1251304C true CN1251304C (en) | 2006-04-12 |
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| CN 03121243 Expired - Lifetime CN1251304C (en) | 2003-03-28 | 2003-03-28 | Manufacturing process of integrated aligning mark and channel component element |
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Granted publication date: 20060412 |