CN1243374C - Method for raising silicon nitride surface stickiness utilizing patterned metal structure - Google Patents
Method for raising silicon nitride surface stickiness utilizing patterned metal structure Download PDFInfo
- Publication number
- CN1243374C CN1243374C CNB021060738A CN02106073A CN1243374C CN 1243374 C CN1243374 C CN 1243374C CN B021060738 A CNB021060738 A CN B021060738A CN 02106073 A CN02106073 A CN 02106073A CN 1243374 C CN1243374 C CN 1243374C
- Authority
- CN
- China
- Prior art keywords
- layer
- photoresist
- passivation layer
- increase
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The present invention discloses a method for increasing a surface binding degree of silicon nitride by metal patterned structures. A plurality of metal patterned structures are formed on the surface of a passivation layer, particularly a silicon nitride layer, the effect of roughening the surface is manufactured, and therefore, the adhesive strength between the passivation layer and underfill which is subsequently formed on the passivation layer is enhanced. When the method of the present invention is used for forming metal patterned structures, under bump metallurgy (UBM) can be formed in a long bumping process, the under bump metallurgy (UBM) can be formed on the surface of the passivation layer simultaneously, wherein the components of the metal patterns are the same as those of the under bump metallurgy (UBM), and an undercutting mode of a metallic layer, which is caused by a two-stage etching process of forming the under bump metallurgy (UBM), has an anchor effect of increasing the adherence between the passivation layer and underfill.
Description
Technical field
The present invention relates to cover crystalline substance (flip chip) encapsulation technology, particularly relevant for a kind of method of utilizing the pattern metal structure to increase the silicon nitride surface sticky limit.
Background technology
The major function of IC encapsulation comprises: protect IC, the interface that information is transmitted between crystal grain (chip) and the ambient systems device is provided, so the IC processing procedure develops, the functional of system product all is the main cause that influences the development of IC encapsulation technology.Today, the requirement of electronic product was compact, and the technology that reduces crystallite dimension will be arranged; The miniaturization of IC processing procedure, the logic that causes intragranular to comprise increases, the pin positions that increase some inputs and output signal outside crystal grain of will trying every possible means more.Because these demands numerous caused the packaged type of many different a new generations, as: ball grid array (BGA), wafer size encapsulation (CSP), polycrystalline sheet module (multi-chip module; MCM), covering crystalline substance advanced technologies such as (FC) arises at the historic moment.Wherein chip package has been owing to reduced the path distance that wafer transmits to information between the ambient systems device, and has preferable electrical characteristic, becomes next encapsulation technology from generation to generation that quite attracts attention.
The chip package technology is to utilize the conductor projection as I/O.In the processing procedure that forms the conductor Solder Bumps, on aluminum metal weld pad (pad), utilize etch process etch passivation layer usually to expose weld pad.Respectively the combination layer of deposit barrier layers and conductive layer is thereon again, after general composition comprises Cr/Cu, Ti/Cu, Cr/CrCu/Cu, AL/NiV/Cu, utilize the micro-photographing process painting photoresist and form pattern, the photoresist pattern of formation has on aluminium welding pad windows.Utilize galvanoplastic to form tin lead and among windowing, contact, remove the photoresist pattern then and form Solder Bumps with conductive layer.Next step is to utilize Solder Bumps to remove the barrier layer and the conductive layer of not caught as etch mask, finish forming the Solder Bumps processing procedure, and the combination layer of barrier layer that stays and conductive layer is a metal under the alleged projection.
The Solder Bumps that stays is just finished soldering projection (solder bump) behind tin hot-fluid (solder reflow) processing procedure.See also Fig. 1, it is a typical composite packing structure schematic diagram, 3 of the face down of crystal grain 1 and substrates (substrate) link to each other with soldering projection 5, the hole that the filling thing (underfill) 7 of glue is full of is therebetween solidified to increase the intensity of soldering projection again then, and substrate 3 another sides then are the tin balls (solder ball) 9 that links to each other with system.Wherein can the adhesion strength between bottom sealing and crystal grain passivation layer be by the key factor of terminal reliability test.Present prior art in order to strengthen the adhesion strength between bottom sealing and crystal grain passivation layer, attempts being improved with the composition of various different bottom sealings; Or with benzyl ring butylene (benzocyclobutene, BCB) or poly-ethanamide (polyimide, PI) layer is a passivation layer, this passivation layer is done the surface handle, and for example increases the degree of roughness on this organic surface with the adhesion strength of reinforcement with the bottom sealing with plasma bombardment (plasma).If with the silicon nitride is passivation layer, then form a heavy passivation layer (re-passivation) thereon, BCB or PI layer are done the surface to this heavy passivation layer again and handled, and be little to the silicon nitride layer effect because of increasing surface roughness with plasma bombardment.
Yet, utilize ion bombardment need increase cost.And utilize the mode of adding one deck passivation layer, and not only on cost, increase to some extent, also prolong many on Production Time.Method provided by the present invention, it is coarse not make passivation layer surface with ion bombardment, also need not change the bottom sealing, is the wafer of passivation layer with the silicon nitride particularly, is a saving cost and a high efficiency method.
Summary of the invention
Purpose of the present invention between crystal grain passivation layer (passivation) and bottom sealing (underfill), increases the method for adhesion strength for being provided in the encapsulation procedure.
The principle that the present invention utilized can the increment surface for rough surface and material formed thereon between adhesion strength.Method of the present invention is to form a film on a surface, to the etching of being developed of this layer film, forms a pattern closely.Thereby simulate the effect of rough surface, increase this surperficial adhesion strength.
For reaching above-mentioned purpose, the present invention proposes a kind of method that increases sticky limit in the lug manufacturing process, comprises following steps at least: form a plurality of weld pads on wafer; Form a passivation layer on this wafer and these a plurality of weld pads; This passivation layer of patterning exposes the upper surface of these a plurality of weld pads; Form the projection lower metal layer on this passivation layer, and connect these a plurality of weld pads that expose to the open air; Utilize a photoresist define desire form the zone of Solder Bumps with in order to increase the pattern of this passivation layer surface roughness; This projection lower metal layer that etching is not covered by this photoresist; One half tone with long Solder Bumps pattern is overlayed on this wafer; Insert tin cream in the long Solder Bumps pattern of this half tone, engage with metal under this projection that is exposed on this wafer; And remove half tone.
Another kind of technical scheme of the present invention is: a kind of method that increases sticky limit in the lug manufacturing process comprises following steps at least: form a plurality of weld pads on wafer; Form a passivation layer on this wafer and these a plurality of weld pads; This passivation layer of patterning exposes the upper surface of these a plurality of weld pads; Form the projection lower metal layer on this passivation layer, and connect these a plurality of weld pads that expose to the open air; Utilize first photoresist to define the zone that desire forms Solder Bumps; Utilize to electroplate and form Solder Bumps on this projection lower metal layer that is not covered by this photoresist; Remove first photoresist; Utilize the definition of second photoresist in order to increase the pattern of this passivation layer surface roughness; This projection lower metal layer that etching exposes; And remove second photoresist.
Another technical scheme of the present invention is: a kind of method that increases the substrate sticky limit comprises following steps at least: forming a sacrifice layer increases on the substrate of sticky limit in a desire; Utilize photoresist to define in order to increase the pattern of this substrate surface for roughness at sacrifice layer; This sacrifice layer that etching is not covered by this photoresist; And remove this photoresist.Described sacrifice layer comprises two-layer layer structure inequality at least.This sacrifice layer that described etching is not covered by this photoresist comprises that this sacrifice layer of etching a plurality ofly has the male structure layer of jagged edge in this substrate surface to form.The spacing distance that more comprises the number of adjusting this male structure layer and two adjacent male structure layers is to change this substrate surface for roughness.
Method of the present invention is passed through at passivation layer, silicon nitride layer particularly, the surface forms some pattern metal structures (metal patterned structure), produces the effect of roughened surface, increases adhesion strength between passivation layer and bottom sealing formed thereon subsequently with this.Method provided by the present invention forms the pattern metal structure, and (underbump metallurgy, step UBM) are formed at the surface of passivation layer simultaneously can to form metal under the projection in long lug manufacturing process (bumping process).Wherein the constituent of metal pattern is identical with metal under the projection.Wherein form the two-stage etching processing procedure of metal under the projection,, anchoring effect (anchor effect) is arranged for the adhesion that increases between passivation layer and bottom sealing to the jagged edge kenel that metal level caused.
Description of drawings
Fig. 1 is shown for covering the sectional view of crystalline substance (flip chip) encapsulating structure;
The shown semiconductor crystal wafer sectional view that forms the projection lower metal layer that is positioned on the wafer for the present invention of Fig. 2;
Fig. 3 A is shown to form under the projection semiconductor crystal wafer sectional view of the intensive pattern of intermetallic under the metal and projection for the present invention;
Fig. 3 B is shown to be the enlarged drawing of dotted portion among Fig. 3 A;
The shown semiconductor crystal wafer sectional view that forms the tin ball for this Solder Bumps of hot-fluid of the present invention of Fig. 4;
Fig. 5 is shown to be the enlarged drawing of dotted portion among Fig. 4.
Embodiment
In encapsulation (package) processing procedure, after finishing long lug manufacturing process (bumping process), between crystal grain and substrate, the hole that is full of therebetween with the bottom sealing of glue is solidified to increase the intensity of soldering projection again.Can wherein the adhesion strength between bottom sealing and crystal grain passivation layer be after this crystal grain is finished encapsulation, by the key of reliability test.If the adhesion strength deficiency then has the danger of peeling off, lower useful life.The present invention discloses a kind of method that increases adhesion strength, be when utilizing under forming projection metal, make intensive pattern on the silicon nitride layer surface, increase the degree of roughness on surface, and formed jagged edge kenel causes anchoring effect (anchor effect) to the bottom sealing during by etch metal layers.Utilize the adhesion strength between this dual mode increase crystal grain passivation layer and filling thing.Be described in detail as follows, it is non-in order to limit the present invention that an explanation is only done in described preferred embodiment.
Consult Fig. 2, on wafer 2, have a metal pad (pad) 4, utilize photoresist to define the region of weld pad, expose weld pad 4 with etch process etch passivation layer 6.The composition of above-mentioned passivation layer 6 can comprise PI or BCB or silicon nitride.Then form projection lower metal layer 400 (with reference to Fig. 3 B); (under bump metal UBM) can select the metal/structures such as copper layer/nickel dam that comprise titanium or chromium for use to metal under the projection usually.Elder generation's deposit barrier layers 8 can be selected the metal that comprises titanium or chromium for use.Then form conductive layer thereon, conductive layer generally comprises copper or copper alloy, can form one earlier and be beneficial to the copper seed layer (seeding layer) 10 that copper material is electroplated, re-use copper electroplating layer 12, can re-use galvanoplastic then and form a nickel dam 14 on its surface, wherein the thickness of copper layer 12 is about 4 to 6 microns, and the thickness of nickel dam 14 is about 2 to 4 microns.Above-mentioned copper seed layer 10 can utilize sputtering way to be formed on the surface of barrier layer 8, and it consists of Cr/Cu or Ti/Cu.Aforementioned for material and thickness only as an embodiment in order to explanation, non-in order to limit spirit of the present invention, hereat the scope of the invention comprises the replacement of impartial function material.
Consult Fig. 3 A, carry out spin-coating program (spin-on), be coated with a photoresist layer 16 on this projection lower metal layer structure.Then utilize micro-photographing process on photoresist, to define the zone 100 that desire forms Solder Bumps, between the zone of the long Solder Bumps of desire, define an intensive pattern 200 simultaneously.Is the cover curtain with the photoresist, this each metal level of etching is till the passivation layer.Remove photoresist, then the mode with screen painting (print) forms Solder Bumps.There is desire to form the figure of Solder Bumps on the half tone, tin cream inserted, join with the metal level that exposes by half tone.Because the zone of intensive pattern is blocked by half tone, do not form in this zone so do not have tin cream.Through superheat flow (reflow), tin lead button in the tin cream forms the making that chondritic is finished the tin ball because of factors such as cohesive force, as shown in Figure 4 then.Remove scaling powder (fluxcleaning) then.
Shown in Fig. 4,5, by on be set forth in defined intensive pattern 200 between the zone that desire forms long Solder Bumps, form many male structure layers 201 and be distributed on the passivation layer 6.The surface that this male structure layer 201 makes passivation layer 6 is convex-concave and increase roughness obviously, and then increases the tack strength between passivation layer 6 and the follow-up bottom sealing (not icon) formed thereon.Wherein each male structure layer 201 comprises at least one metal level 2011, these metal level 2011 materials are identical with sacrifice layers such as barrier layer 8, copper seed layer 10, copper layer 12 or nickel dams 14, and the closeness that male structure layer 201 distributes can determine the tack strength of degree of roughness to increase demand on passivation layer 6 surfaces.
As form Solder Bumps with plating mode, then because of being to be divided into electrode with the metal part of exposing to form Solder Bumps.Can't define intensive pattern between Solder Bumps and Solder Bumps simultaneously with single photoresist.Can after made Solder Bumps, removing photoresist, form another layer photoresist again, utilize the intensive pattern between this another layer photoresist definition Solder Bumps in passivation layer surface.
What specify is that of the present invention focusing on causes rough surface and anchoring effect to increase the adhesion strength between passivation layer and bottom sealing to form the method for pattern metal structure in passivation layer surface.Therefore in the Solder Bumps processing procedure, form the step or the mode of this pattern metal structure or difference is arranged, do not break away from the scope of patent of the present invention.
The above embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when not limiting claim of the present invention with it, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim scope of the present invention.
Claims (10)
1. method that increases sticky limit in the lug manufacturing process, it is characterized in that: this method comprises following steps at least:
Form a plurality of weld pads on wafer;
Form a passivation layer on this wafer and these a plurality of weld pads;
This passivation layer of patterning exposes the upper surface of these a plurality of weld pads;
Form the projection lower metal layer on this passivation layer, and connect these a plurality of weld pads that expose to the open air;
Utilize a photoresist define desire form the zone of Solder Bumps with in order to increase the pattern of this passivation layer surface roughness;
This projection lower metal layer that etching is not covered by this photoresist;
One half tone with long Solder Bumps pattern is overlayed on this wafer;
Insert tin cream in the long Solder Bumps pattern of this half tone, engage with metal under this projection that is exposed on this wafer; And
Remove half tone.
2. the method for sticky limit in the increase lug manufacturing process as claimed in claim 1 is characterized in that: described in order to increasing the pattern of this passivation layer surface roughness, can increase adhesion strength between passivation layer and bottom sealing according to the surface roughness that it increased.
3. the method for sticky limit in the increase lug manufacturing process as claimed in claim 1, it is characterized in that: the step of this projection lower metal layer that described etching is not covered by this photoresist comprises that this projection lower metal layer of etching a plurality ofly has the male structure layer of jagged edge in this substrate surface to form.
4. method that increases sticky limit in the lug manufacturing process, it is characterized in that: this method comprises following steps at least:
Form a plurality of weld pads on wafer;
Form a passivation layer on this wafer and these a plurality of weld pads;
This passivation layer of patterning exposes the upper surface of these a plurality of weld pads;
Form the projection lower metal layer on this passivation layer, and connect these a plurality of weld pads that expose to the open air;
Utilize first photoresist to define the zone that desire forms Solder Bumps;
Utilize to electroplate and form Solder Bumps on this projection lower metal layer that is not covered by this photoresist;
Remove first photoresist;
Utilize the definition of second photoresist in order to increase the pattern of this passivation layer surface roughness;
This projection lower metal layer that etching exposes; And
Remove second photoresist.
5. the method for sticky limit in the increase lug manufacturing process as claimed in claim 4 is characterized in that: described in order to increasing the pattern of this passivation layer surface roughness, can increase adhesion strength between passivation layer and bottom sealing according to the surface roughness that it increased.
6. the method for sticky limit in the increase lug manufacturing process as claimed in claim 4, it is characterized in that: the step of this projection lower metal layer that described etching is not covered by this second photoresist comprises that this projection lower metal layer of etching a plurality ofly has the male structure layer of jagged edge in this substrate surface to form.
7. method that increases the substrate sticky limit, it is characterized in that: this method comprises following steps at least:
Forming a sacrifice layer increases on the substrate of sticky limit in a desire;
Utilize photoresist to define in order to increase the pattern of this substrate surface for roughness at sacrifice layer;
This sacrifice layer that etching is not covered by this photoresist; And
Remove this photoresist.
8. the method for increase sticky limit as claimed in claim 7 is characterized in that: described sacrifice layer comprises two-layer layer structure inequality at least.
9. the method for increase sticky limit as claimed in claim 8 is characterized in that: this sacrifice layer that described etching is not covered by this photoresist comprises that this sacrifice layer of etching a plurality ofly has the male structure layer of jagged edge in this substrate surface to form.
10, the method for increase sticky limit as claimed in claim 9 is characterized in that: the spacing distance that more comprises the number of adjusting this male structure layer and two adjacent male structure layers is to change this substrate surface for roughness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021060738A CN1243374C (en) | 2002-04-10 | 2002-04-10 | Method for raising silicon nitride surface stickiness utilizing patterned metal structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021060738A CN1243374C (en) | 2002-04-10 | 2002-04-10 | Method for raising silicon nitride surface stickiness utilizing patterned metal structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1450615A CN1450615A (en) | 2003-10-22 |
| CN1243374C true CN1243374C (en) | 2006-02-22 |
Family
ID=28680145
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021060738A Expired - Lifetime CN1243374C (en) | 2002-04-10 | 2002-04-10 | Method for raising silicon nitride surface stickiness utilizing patterned metal structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1243374C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101882596B (en) * | 2009-05-08 | 2012-06-06 | 中芯国际集成电路制造(上海)有限公司 | Method for etching metal layer |
| US8822106B2 (en) * | 2012-04-13 | 2014-09-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Grid refinement method |
| CN109192069B (en) * | 2018-09-28 | 2020-11-06 | 云谷（固安）科技有限公司 | Display panel and method for manufacturing the same |
-
2002
- 2002-04-10 CN CNB021060738A patent/CN1243374C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1450615A (en) | 2003-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6621164B2 (en) | Chip size package having concave pattern in the bump pad area of redistribution patterns and method for manufacturing the same | |
| US5982033A (en) | Semiconductor chip package | |
| US7034402B1 (en) | Device with segmented ball limiting metallurgy | |
| US8487432B2 (en) | Electronic structures including barrier layers and/or oxidation barriers defining lips and related methods | |
| US8487438B2 (en) | Integrated circuit system having different-size solder bumps and different-size bonding pads | |
| US20020086520A1 (en) | Semiconductor device having bump electrode | |
| US20080054461A1 (en) | Reliable wafer-level chip-scale package solder bump structure in a packaged semiconductor device | |
| US20050014355A1 (en) | Under-bump metallization layers and electroplated solder bumping technology for flip-chip | |
| US20070210450A1 (en) | Method of forming a bump and a connector structure having the bump | |
| US20040084206A1 (en) | Fine pad pitch organic circuit board for flip chip joints and board to board solder joints and method | |
| US20050242446A1 (en) | Integrated circuit package with different hardness bump pad and bump and manufacturing method therefor | |
| CN1291468C (en) | Method and apparatus for manufacturing interconnect structure | |
| US20100117231A1 (en) | Reliable wafer-level chip-scale solder bump structure | |
| US20040222520A1 (en) | Integrated circuit package with flat metal bump and manufacturing method therefor | |
| US6596611B2 (en) | Method for forming wafer level package having serpentine-shaped electrode along scribe line and package formed | |
| JPH11354563A (en) | Structure of semiconductor wiring | |
| US6774026B1 (en) | Structure and method for low-stress concentration solder bumps | |
| CN1243374C (en) | Method for raising silicon nitride surface stickiness utilizing patterned metal structure | |
| US6916732B2 (en) | Method of forming bumps | |
| CN100555593C (en) | Form the method for soldering projection | |
| CN101106114A (en) | Chip structure and its forming method | |
| US6692629B1 (en) | Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer | |
| US20080119056A1 (en) | Method for improved copper layer etching of wafers with c4 connection structures | |
| US11798885B2 (en) | Method of fabricating copper pillar bump structure with solder supporting barrier | |
| TW558782B (en) | Fabrication method for strengthened flip-chip solder bump |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20060222 |
|
| CX01 | Expiry of patent term |