CN1237780A - Contact window and its etching method - Google Patents
Contact window and its etching method Download PDFInfo
- Publication number
- CN1237780A CN1237780A CN98102315.0A CN98102315A CN1237780A CN 1237780 A CN1237780 A CN 1237780A CN 98102315 A CN98102315 A CN 98102315A CN 1237780 A CN1237780 A CN 1237780A
- Authority
- CN
- China
- Prior art keywords
- contact hole
- etching
- integrated circuit
- etch depth
- mentioned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005530 etching Methods 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000011229 interlayer Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 206010021143 Hypoxia Diseases 0.000 claims description 3
- 208000018875 hypoxemia Diseases 0.000 claims description 3
- 238000005496 tempering Methods 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 abstract description 15
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 15
- 239000004411 aluminium Substances 0.000 abstract description 10
- 229910052751 metal Inorganic materials 0.000 abstract description 8
- 239000002184 metal Substances 0.000 abstract description 8
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
The etching method of contact window for integrated circuit element includes the following three steps: a). non-equidirectional etching to form first etched depth; (b). equidirectional etching to form second etched depth; and c). non-equidirectional etching to form third etched depth, in which the specific value of the above-mentioned third etched depth and tolal etched depth formed from the above-mentioned first, second and third etched depths is less than 0.5. The contact window formed by using said method possesses excellent metal aluminium graded coverage rate, and can make electric connection reliable, and do not increase cost.
Description
The present invention relates generally to integrated circuit component, relates in particular in the integrated circuit component in order to engraving method that forms the contact hole that is electrically connected and the contact hole that forms thus.
Under the situation that does not limit range of application of the present invention, existing is that example describes with SRAM (SRAM) integrated circuit component.
In known 0.6 micron SRAM manufacture process, as shown in Figure 1a, after formation thickness was the polysilicon interlayer 12 of 3250 dusts (A) on the behaviour area 11, the oxide skin(coating) 13 that deposits 7500 dust thickness was on whole behaviour area 11.Then, shown in Fig. 1 b, through planarization, form the oxide skin(coating) 14 with flat surfaces, its surface apart from behaviour area 11 is 8500 dusts.Contact hole can be formed in the oxide skin(coating) 14 of 12 in adjacent two polysilicon interlayers by etching mode.If make this contact hole with the etching mode of general sub-micron grade, can produce the bad situation of metallic aluminium step coverage rate (Step Coverage), cause electrical connection unreliable.Figure 2 shows that with traditional sub-micron grade etching mode and in Fig. 1 b oxide skin(coating) 14, form contact hole 21.It adopts two step etching modes: (1) first step reaches laterally each etching 3500 dust downwards for waiting to etching, forms the part that highly is denoted as a; (2) second steps be non-grade to etching, downwards etching 5000 dusts form the part that highly is denoted as b.For avoiding 12 in contact hole 21 and polysilicon interlayer to produce leakage current, so the grade of first step is can not etching too dark to etching.But, make that so vertical depth ratio (b/a+b) is excessive, about 59%, thereby make corner 22 too sharp-pointed, even pass through temper again, it is bad that follow-up metal is covered.Fig. 3 promptly describes this kind situation, and wherein contact hole 21 is because of having underlying metal titanium (Ti) or titanium nitride (TiN) 31 and upper strata aluminium 32 through metalized.Upper strata aluminium 32 is producing phenomenon of rupture near underlying metal 31 places.The etched metallic aluminium step coverage rate of this two step (metallic aluminium covers the thinnest with the thickest thickness ratio) is 0%.Therefore, the electrical connection in the contact hole 21 only depends on underlying metal 31 to keep, and influences its reliability.
For addressing the above problem, utilized the high temperature aluminum method.But, though the high temperature aluminum method has preferable step coverage rate, about 15%-20%, its shortcoming is: (1) needs the two-period form elevated temperature, expends time in, and output is few, and wastes energy; (2) current characteristics is not good, easily chaps because of high temperature aluminum cooling rear surface, causes resistance value to produce unexpected variation; (3) equipment cost height.
Therefore, existing a kind of low-cost contact hole etching method that is applicable to sub-micron grade of demand, it can produce the contact hole with preferred metal aluminum step wedge or ladder coverage rate in original width or narrower width, its vertical depth ratio is lower and the corner angle is slick and sly, to form reliable electrical connection.
The purpose of this invention is to provide a kind of contact hole etching method.
Two of purpose of the present invention provides a kind of contact hole of tool preferred metal aluminum step wedge or ladder coverage rate.
Three of purpose of the present invention provides a kind of contact hole with low vertical depth ratio.
Four of purpose of the present invention provides the slick and sly contact hole of a kind of corner angle.
In order to achieve the above object, technical solution of the present invention is: a kind of contact hole etching method that is used for integrated circuit component comprises the following step: a) non-grade forms first etch depth to etching; B) etc. to etching, form second etch depth; C) non-grade forms the 3rd etch depth to etching; Wherein, above-mentioned the 3rd etch depth with by the ratio of the formed total etch depth of above-mentioned first, second and third etch depth less than 0.5.
Above-mentioned ratio is greater than the polysilicon thickness of interlayer of integrated circuit component and the ratio of above-mentioned total etch depth.
Above-mentioned contact hole etching method also comprises step d) makes contact hole top corner slynessization with the hypoxemia tempering.
The said integrated circuit element is 0.35～0.6 micron order.
Adopt the contact hole of the integrated circuit component of above-mentioned engraving method formation.
Contact hole etching method of the present invention has following advantage: (1) corner angle is slick and sly, is difficult for deposit; (2) vertically depth ratio reduces, and is easy to make metal to cover; (3) the metallic aluminium step coverage rate is preferable; (4) original width be can keep, design and electrical characteristic do not influenced; (5) applicable to 0.35～0.6 micron order integrated circuit.
The contact hole of the present invention of Xing Chenging has preferable metallic aluminium step coverage rate as stated above, make to be electrically connected reliably, and unlikely increase cost.
Below in conjunction with accompanying drawing and preferred embodiment the present invention is described in detail;
Fig. 1 a and Fig. 1 b are the constructed profile of the relevant contact structure of known 0.6 micron SRAM manufacturing process;
Fig. 2 is known sub-micron grade etching mode forms contact hole in Fig. 1 b a constructed profile;
Fig. 3 is the constructed profile of contact hole after metalized shown in Figure 2;
Fig. 4 a is the constructed profile according to the contact hole that first step forms of preferred embodiment of the present invention;
Fig. 4 b is the constructed profile according to second contact hole that step forms of preferred embodiment of the present invention;
Fig. 4 c is the constructed profile according to the contact hole that third step forms of preferred embodiment of the present invention;
Fig. 5 is the electron microscope enlarged photograph, shows according to preferred embodiment of the present invention formed section that has passed through the contact hole of metalized in 0.6 micron SRAM.
Shown in Fig. 4 a, be the implementation method of preferred embodiment first step of the present invention, with downward etching 1500 dusts in being etched in oxide skin(coating) 14 such as non-grade, and form contact hole 41.After, be depicted as preferred embodiment second step of the present invention as Fig. 4 b, waiting, and form contact hole 42 to etching mode etching 3500 dusts.Then, in Fig. 4 c, the third step of preferred embodiment of the present invention is to implement non-grade to etching, downward etching 3500 dusts, and form contact hole 43, and can pass through the hypoxemia tempering thereafter, make corner 44 slynessizationes of top.
In this preferred embodiment, has lower vertical depth ratio by the formed contact hole 43 of above-mentioned three step engraving methods of the present invention, about 41% (being B/A+B).In fact, the upper limit of this vertical depth ratio can tune to less than 50%, and its lower limit then must be considered the thickness of polysilicon interlayer 12.If Deng being Nitrogen trifluoride (NF to etched main etching gas
3), then causing the injury of polysilicon interlayer 12 easily, must before polysilicon interlayer 12 and oxide skin(coating) 14 contact-making surfaces, stop so waiting, shown in Fig. 4 c to etching.So, the lower limit of this vertical depth ratio system be set at greater than.Polysilicon interlayer 12 thickness/contact hole total depth.
Because of the contact hole that forms according to the inventive method has lower vertical depth ratio, preferable so contact hole corner 44 angles are slick and sly thereby the metallic aluminium on it covers situation, be unlikely fracture, shown in the photo of Fig. 5.After actual measurement, learn, adopt the metallic aluminium step coverage rate about 15%～20% of the inventive method.
Again, though the inventive method is that embodiment is illustrated with 0.6 micron-sized integrated circuit, and in fact at least applicable in the 0.35 micron-sized integrated circuit.
Though describe the present invention in detail with reference to above-mentioned preferred embodiment, but and nonrestrictive explanation, the person skilled in the art can consult above-mentioned explanation and carry out relevant change or modification, and therefore, all any change or modifications of making by content of the present invention include within the scope of the present invention.
Claims (5)
1. contact hole etching method that is used for integrated circuit component comprises the following step:
A) non-grade forms first etch depth to etching;
B) etc. to etching, form second etch depth;
C) non-grade forms the 3rd etch depth to etching;
Wherein, above-mentioned the 3rd etch depth with by the ratio of the formed total etch depth of above-mentioned first, second and third etch depth less than 0.5.
2. contact hole etching method as claimed in claim 1, wherein said ratio is greater than the polysilicon thickness of interlayer of integrated circuit component and the ratio of above-mentioned total etch depth.
3. contact hole etching method as claimed in claim 1 wherein also comprises step d) and makes contact hole top corner slynessization with the hypoxemia tempering.
4. contact hole etching method as claimed in claim 1, wherein said integrated circuit component are 0.35～0.6 micron order.
5. contact hole with the formed integrated circuit component of each engraving method in the claim 1 to 4.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002238128A CA2238128A1 (en) | 1998-05-20 | 1998-05-20 | 3-step etching for contact window |
| DE19823223A DE19823223A1 (en) | 1998-05-20 | 1998-05-25 | Three-step etching of contact via |
| GB9811203A GB2337850A (en) | 1998-05-20 | 1998-05-27 | Etching contact windows |
| CN98102315.0A CN1237780A (en) | 1998-05-20 | 1998-05-29 | Contact window and its etching method |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CA002238128A CA2238128A1 (en) | 1998-05-20 | 1998-05-20 | 3-step etching for contact window |
| DE19823223A DE19823223A1 (en) | 1998-05-20 | 1998-05-25 | Three-step etching of contact via |
| GB9811203A GB2337850A (en) | 1998-05-20 | 1998-05-27 | Etching contact windows |
| CN98102315.0A CN1237780A (en) | 1998-05-20 | 1998-05-29 | Contact window and its etching method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1237780A true CN1237780A (en) | 1999-12-08 |
Family
ID=31499382
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98102315.0A Pending CN1237780A (en) | 1998-05-20 | 1998-05-29 | Contact window and its etching method |
Country Status (4)
| Country | Link |
|---|---|
| CN (1) | CN1237780A (en) |
| CA (1) | CA2238128A1 (en) |
| DE (1) | DE19823223A1 (en) |
| GB (1) | GB2337850A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100383667C (en) * | 2002-02-08 | 2008-04-23 | 旺宏电子股份有限公司 | Semiconductor element pattern transferring method |
| US7449407B2 (en) | 2002-11-15 | 2008-11-11 | United Microelectronics Corporation | Air gap for dual damascene applications |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10041829B4 (en) * | 2000-08-25 | 2004-11-04 | N F T Nanofiltertechnik Gmbh | cooler |
| US7044212B1 (en) | 2000-08-25 | 2006-05-16 | Net Nanofiltertechnik Gmbh | Refrigeration device and a method for producing the same |
| DE10042235A1 (en) * | 2000-08-28 | 2002-04-18 | Infineon Technologies Ag | Process for producing an electrically conductive connection |
| DE102006026549A1 (en) * | 2006-06-08 | 2007-12-13 | Audi Ag | Process for producing friction discs of ceramic materials with improved friction layer |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5354386A (en) * | 1989-03-24 | 1994-10-11 | National Semiconductor Corporation | Method for plasma etching tapered and stepped vias |
| US5180689A (en) * | 1991-09-10 | 1993-01-19 | Taiwan Semiconductor Manufacturing Company | Tapered opening sidewall with multi-step etching process |
| EP0541160A1 (en) * | 1991-11-07 | 1993-05-12 | Koninklijke Philips Electronics N.V. | Method of manufacturing a semiconductor device whereby contact windows are provided in an insulating layer comprising silicon nitride in two etching steps |
| JP2988122B2 (en) * | 1992-05-14 | 1999-12-06 | 日本電気株式会社 | Dry etching apparatus and method for manufacturing semiconductor device |
-
1998
- 1998-05-20 CA CA002238128A patent/CA2238128A1/en not_active Abandoned
- 1998-05-25 DE DE19823223A patent/DE19823223A1/en not_active Withdrawn
- 1998-05-27 GB GB9811203A patent/GB2337850A/en not_active Withdrawn
- 1998-05-29 CN CN98102315.0A patent/CN1237780A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100383667C (en) * | 2002-02-08 | 2008-04-23 | 旺宏电子股份有限公司 | Semiconductor element pattern transferring method |
| US7449407B2 (en) | 2002-11-15 | 2008-11-11 | United Microelectronics Corporation | Air gap for dual damascene applications |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19823223A1 (en) | 1999-12-02 |
| GB2337850A (en) | 1999-12-01 |
| GB9811203D0 (en) | 1998-07-22 |
| CA2238128A1 (en) | 1999-11-20 |
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| PB01 | Publication | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| REG | Reference to a national code |
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