CN1229272A - Method for making dynamic RAM and metal link - Google Patents
Method for making dynamic RAM and metal link Download PDFInfo
- Publication number
- CN1229272A CN1229272A CN98115220.1A CN98115220A CN1229272A CN 1229272 A CN1229272 A CN 1229272A CN 98115220 A CN98115220 A CN 98115220A CN 1229272 A CN1229272 A CN 1229272A
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- China
- Prior art keywords
- titanium
- manufacture method
- insulating barrier
- titanium nitride
- capacitor
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 41
- 229910052751 metal Inorganic materials 0.000 title claims description 19
- 239000002184 metal Substances 0.000 title claims description 19
- 239000003990 capacitor Substances 0.000 claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 claims description 28
- 230000004888 barrier function Effects 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 19
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 14
- 239000010936 titanium Substances 0.000 claims description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 6
- 239000010937 tungsten Substances 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 4
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 claims description 4
- WOIHABYNKOEWFG-UHFFFAOYSA-N [Sr].[Ba] Chemical compound [Sr].[Ba] WOIHABYNKOEWFG-UHFFFAOYSA-N 0.000 claims description 3
- 229910002113 barium titanate Inorganic materials 0.000 claims description 3
- JRPBQTZRNDNNOP-UHFFFAOYSA-N barium titanate Chemical compound [Ba+2].[Ba+2].[O-][Ti]([O-])([O-])[O-] JRPBQTZRNDNNOP-UHFFFAOYSA-N 0.000 claims description 3
- HFGPZNIAWCZYJU-UHFFFAOYSA-N lead zirconate titanate Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ti+4].[Zr+4].[Pb+2] HFGPZNIAWCZYJU-UHFFFAOYSA-N 0.000 claims description 3
- 229910052451 lead zirconate titanate Inorganic materials 0.000 claims description 3
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 claims 3
- 230000002093 peripheral effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 25
- 239000011229 interlayer Substances 0.000 description 24
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 11
- 229920005591 polysilicon Polymers 0.000 description 11
- 239000003989 dielectric material Substances 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910015801 BaSrTiO Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
A technology for manufacturing DRAM chip and metallic connecting wire includes providing semiconductor substrate including cell area and peripheral circuit area, forming the first insulating layer with transistor and electric conducting layer on it, forming more openings to expose source/drain areas and electric conducting layer, forming memory node at the opening exposing source/drain area, forming the first conducting pin at the opening exposing conducting layer, forming dielectric layer and top electrode on memory node, forming the second insulating layer on capacitor and the first insulating layer, and forming the second conducting pin in contact with the first one on the second insulating layer.
Description
The present invention relates to a kind of dynamic random access memory (Dynamic Random Access Memory, DRAM) and the manufacture method of metal connecting line, particularly relate to a kind of use metal level-insulating barrier-metal level (Metal Insulator Metal, MIM) DRAM capacitor arrangement, reduce the depth-width ratio (Aspect Ratio) of contact hole/interlayer hole opening of periphery circuit region (Peripheral Region), and then finish the manufacture method of metal connecting line.
Along with the increase of the integrated level (Integration) of semiconductor element, the design rule (Design Rules) that generally needs phase down according to the integrated circuit component manufacture method reduces the circuit structure size of component.And the dwindling of the component size of DRAM capacitor, the capacitance of capacitor also can reduce, and can cause capacitor to be very easy to be subjected to the influence of alpha-radiation like this.In addition, when capacitance (Capacitance) reduces, must increase the frequency of replenishing (Reffesh) again by the holding capacitor stored charge.
Therefore, at present for the substrate surface that phases down at DRAM long-pending in the increase capacitance, and the capacitance structure of a succession of complexity is proposed, it has three dimensions charge storage surface.But the increase along with the complexity of capacitor arrangement can increase the height of capacitor, thereby make the height of capacitor be higher than periphery circuit region.The conductive plunger of periphery circuit region can be after capacitor be finished, and forms after finishing the planarization of insulating barrier of its top again.So during to the contact hole of periphery circuit region/interlayer hole opening composition, can cause the increase of its depth-width ratio, can improve the degree of difficulty of the contact hole/etching of interlayer hole opening and the deposition of metal level like this, so increase the difficulty of follow-up metal connecting line to integrated circuit.
Because the increase of the depth-width ratio of contact hole/interlayer hole opening needs to use expensive etching machine to carry out etching process, to reach the requirement on the manufacture craft.In addition, when inserting electric conducting material, also need the differentiate electric material to have good ladder and cover (Step Coverage) ability, to guarantee the conducting of circuit, so great restriction is arranged in the use of electric conducting material.N type (n-type) the polysilicon electric conducting material that DRAM is commonly used is for fear of high resistance and may cause P
+The counter-doping (Counter-doping) of doped region cause resistance to raise, and can't be used in periphery circuit region.
In addition, use in the method for polysilicon electric conducting material as the electrode of capacitor, use the dielectric layer of ONO (oxide-nitride thing-oxide) structure usually as capacitor in tradition.Traditional capacitor arrangement can't use the dielectric material of high-k (Dielectric Constant), because the material of high-k is easy and the polysilicon electric conducting material produces chemical reaction, metal electrode does not then have this problem.Yet, the surface area of the electrode of the memory space of electric charge and capacitor in the capacitor, and the dielectric dielectric constant between capacitor is directly related, therefore traditional ONO capacitor can't provide effective magnitude of the stored charge.
Therefore, first purpose of the present invention is to provide the manufacture method of a kind of DRAM and metal connecting line, utilizes the capacitor arrangement of MIM, reduces the depth-width ratio of the contact hole/interlayer hole opening of peripheral circuit.
Second purpose of the present invention is to provide the manufacture method of a kind of DRAM and metal connecting line, to increase the magnitude of the stored charge of capacitor.
For achieving the above object, the invention provides the manufacture method of a kind of DRAM and metal connecting line, comprise: the semiconductor substrate is provided, this semiconductor-based end, comprise a unit area and a periphery circuit region, there is a transistor this unit area, this periphery circuit region has a conductive layer at least, has been formed with first insulating barrier of this transistor of covering and this conductive layer on this semiconductor-based end; Form a plurality of openings in this first insulating barrier, these openings expose this transistorized source and this conductive layer; Form a memory node of a capacitor at this opening part that exposes this source/drain regions, and form one first conductive plunger at the opening part that exposes this conductive layer; On this memory node, form a dielectric layer and a top electrode successively, so finish the structure of this capacitor; On this capacitor and this first insulating barrier, form one second insulating barrier; In this second insulating barrier, form one second conductive plunger, and this second conductive plunger contacts with this first conductive plunger.
The manufacture method of DRAM of the present invention and metal connecting line is the capacitor arrangement of a kind of MIM of utilization, and two stages of using finish the manufacturing of the conductive plunger of periphery circuit region, therefore can reduce the depth-width ratio of the contact hole/interlayer hole opening of periphery circuit region, and can use low-resistance conductive materials to insert the storage node contacts window opening of unit area, and the contact hole of periphery circuit region/interlayer hole opening.In addition, the dielectric layer in the MIM capacitor structure can use the dielectric material of high-dielectric coefficient, so increase the magnitude of the stored charge of capacitor.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 and Fig. 2 A to Fig. 5 A are the manufacture methods that illustrates the metal connecting line of a kind of DRAM periphery circuit region according to one preferred embodiment of the present invention; And
Fig. 1 and Fig. 2 B to Fig. 5 B are the manufacture methods that illustrates the metal connecting line of a kind of DRAM periphery circuit region according to another preferred embodiment of the invention.
Fig. 1 to Fig. 5 illustrates the manufacture method of the metal connecting line of a kind of DRAM periphery circuit region according to a preferred embodiment of the invention.
At first please refer to Fig. 1, semiconductor substrate 100 is provided, comprising unit area (CellRegion) 103 and periphery circuit region 105.The effect of unit area 103 is to be used for storing data; And periphery circuit region is some address decoders (Address Decoder), be used for being decoded in the address of the memory cell of memory cell areas, and some circuit relevant with storage operation.
The forming process of the above element is as follows: the electric conducting material that at first forms one deck polysilicon on the semiconductor-based end 100, then carry out composition and etching, forming polysilicon conducting layers 113 at periphery circuit region 105, and the polysilicon conducting layers that is formed on unit area 103 is to select the grid 113 of transistor 112.Carry out ion doping afterwards,, and form doped regions 116,120 at periphery circuit region 105 with 103 formation source area 107 and drain regions 109 in the unit area.Then deposit first insulating barrier 110, its material for example is an oxide, covers structure of the whole semiconductor-based ends 100, forms the conductive layer 118 of composition as shown in the figure again above first insulating barrier 110, form second insulating barrier 111 afterwards again, its material for example is an oxide.Wherein first insulating barrier 110 and second insulating barrier 111 constitute insulating barrier 115, and its gross thickness 114 is about 1.2～1.5 μ m.
Afterwards, the while is 103 formation storage node contacts window (Storage Node Contact) openings 119 in the unit area, and form contact hole/interlayer hole openings 117 at periphery circuit region 105.Its method has two kinds, shown in Fig. 2 A and Fig. 2 B.
In Fig. 2 A, at first carry out anisotropic etching (Anisotropic Etching) manufacture craft, preferable methods is reactive ion etching (Reactive Ion Etching, a RIE) method, in order to formation storage node contacts window opening 119 above drain region 109, and expose drain region 109; And form contact window 117 at periphery circuit region 105 simultaneously.
Another kind method is shown in Fig. 2 B, and the method is in conjunction with anisotropic etching manufacture craft and isotropic etching (Isotropic Etching) manufacture craft.At first carry out anisotropic etching manufacture craft with Fig. 2 A, then carry out the isotropic etching manufacture craft again, its method for example is wet etch method (WetEtching), and the contact window 117 of the storage node contacts window opening 119 of unit area 103 and periphery circuit region 105 is simultaneously all etched, forms the profile as Fig. 2 B.
The present invention forms contact hole/interlayer hole opening 117 of phase I simultaneously at periphery circuit region 105 when forming the storage node contacts window opening 119 of capacitor.Because the present invention will finish in two stages at the conductive plunger of periphery circuit region 105, rather than form after the structure of capacitor is finished, rather than after the structure of capacitor is finished, form again again, therefore can reduce the depth-width ratio of contact hole/interlayer hole opening.So the present invention can use low-resistance conductive materials to insert at formed contact hole of phase I/interlayer hole opening 117.
Then please refer to Fig. 3 A and Fig. 3 B, above insulating barrier 115, form layer of conductive material, and fill up storage node contacts window opening 119 and contact hole/interlayer hole opening 117, it contacts with the drain region 109 of unit area 103, and contacts with 118 and doped region 116 with the conductive layer 113 of periphery circuit region 105.Then to this conductive layer composition, with 103 memory nodes 122 that form capacitors in the unit area, in addition, also the electric conducting material with insulating barrier 115 tops of periphery circuit region 105 divests, and forms conductive plungers 121 at periphery circuit region 105.Its electric conducting material for example is titanium/titanium nitride/tungsten (Ti/TiN/W), and its thickness is about 300～500 dusts, 300～600 dusts and 4000～6000 dusts respectively, or titanium/titanium nitride/platinum (Pt), also or titanium/titanium nitride/ruthenium-oxide (RuO
2) etc.
Wherein, Fig. 3 A is corresponding to Fig. 2 A, and Fig. 3 B is corresponding to Fig. 2 B.In addition, because the depth-width ratio of storage node contacts window opening 119 of the present invention and contact hole/interlayer hole opening 117, not existing excessive situation produces, therefore when inserting electric conducting material, do not require that electric conducting material need have good ladder to cover (Step Coverage) ability, so can insert above-mentioned more low-resistance electric conducting material that has, these electric conducting materials have lower resistance or contact resistance than normally used polysilicon electric conducting material, therefore can improve the transmission rate of data.
Then please refer to Fig. 4 A and Fig. 4 B, on whole underlying structure surface, form one deck dielectric material and one deck conductive layer successively, for example utilize the lithography manufacture craft afterwards, zone with the capacitor that limits unit area 103, with formation dielectric layer 123 and conductive layer 124, and conductive layer 124 is as the top electrode of capacitor.Wherein the dielectric material of dielectric layer 123 for example is tantalum oxide (Ta
2O
5), barium titanate (BaTiO
3), barium strontium (BaSrTiO
3) or lead zirconate titanate (PbZrTiO
3), and the ONO structure that these dielectric materials use than tradition has higher dielectric constant.Yet in traditional method, the material of these high-ks can't use, because the material of these high-ks causes the pollution of polysilicon electric conducting material easily, and easy and polysilicon electric conducting material generation chemical reaction.And capacitor storage node structure provided by the present invention can effectively cooperate the use of these high dielectric materials.In addition, the electric conducting material of conductive layer 124 for example is titanium nitride or tungsten, and its thickness is about 1000～1500 dusts.
Wherein Fig. 4 A is corresponding to Fig. 3 A, and Fig. 4 B is corresponding to Fig. 3 B.
Because the existing complicated capacitor arrangement of the aspect ratio of MIM capacitor structure of the present invention is low, therefore when periphery circuit region 105 follow-up second stage formed contact hole/interlayer hole opening, its depth-width ratio did not have excessive situation yet and occurs.
Then please refer to Fig. 5 A and Fig. 5 B, form one deck megohmite insulant at whole semiconductor-based basal surface, its thickness is about 0.8～1.0 μ m, and via the cmp manufacture craft, to obtain more smooth surface.Afterwards, carry out the formation step of the contact hole/interlayer hole of periphery circuit region 105 second stage.The insulating material layer of periphery circuit region 105 is limited contact hole/interlayer hole opening 127, make insulating material layer become insulating barrier 125, and contact hole/interlayer hole opening 127 filled up electric conducting material, to form conductive plunger 128, wherein conductive plunger 128 contacts with conductive plunger 121 in the insulating barrier 115.
The existing method that forms conductive plunger is after capacitor is finished, and limits its opening, so depth-width ratio is very big.And the present invention utilized for two stages finished conductive plunger, therefore can reduce the depth-width ratio of the contact hole/interlayer hole opening of periphery circuit region 105, and do not need extra photomask, do not need to use expensive etching machine to carry out the etching process of contact hole/interlayer hole opening yet.In addition, because the depth-width ratio of the formed contact hole of the present invention/interlayer hole opening is little,, therefore can use material as Fig. 3 A and the described high conductivity of Fig. 3 B so needn't require the gradient coating performance of the electric conducting material inserted fine.
Feature of the present invention is as follows:
(1) the present invention utilizes the MIM capacitor structure to reduce the depth-width ratio of the contact hole/interlayer hole opening of periphery circuit region.
(2) manufacture method of the metal connecting line of DRAM periphery circuit region provided by the present invention is to utilize for two stages finished the conductive plunger of periphery circuit region, therefore can avoid traditional excessive situation of depth-width ratio to occur.
(3) the present invention can not need to use extra photomask to improve the depth-width ratio of contact hole/interlayer hole opening.
(4) the present invention can not need use expensive etching machine to carry out the etching process of contact hole/interlayer hole opening.
(5) the present invention can use low-resistance conductive materials to insert the storage node contacts window opening of unit area, and the contact hole of periphery circuit region/interlayer hole opening, and whether the gradient coating performance of the conductive materials of needn't worrying reaches.
(6) dielectric material of the dielectric layer in the MIM capacitor structure of the present invention, can use dielectric material with high-k, such as tantalum oxide, barium titanate, barium strontium or lead zirconate titanate, and the material that does not have existing high-k causes electric conducting material to pollute, and with the problem of electric conducting material reaction.
Though disclosed the present invention in conjunction with a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art can make various changes and retouching without departing from the spirit and scope of the present invention, so protection scope of the present invention should be defined by accompanying Claim.
Claims (9)
1. the manufacture method of DRAM and metal connecting line comprises:
The semiconductor substrate is provided, this semiconductor-based end, comprise a unit area and a periphery circuit region, there is a transistor this unit area, and this periphery circuit region has a conductive layer at least, has been formed with first insulating barrier of this transistor of covering and this conductive layer on this semiconductor-based end;
Form a plurality of openings in this first insulating barrier, these openings expose this transistorized source and this conductive layer;
Form a memory node of a capacitor at the opening part that exposes this source/drain regions, and form one first conductive plunger at the opening part that exposes this conductive layer;
On this memory node, form a dielectric layer and a top electrode successively, so finish the structure of this capacitor;
On this capacitor and this first insulating barrier, form one second insulating barrier;
In this second insulating barrier, form one second conductive plunger, and this second conductive plunger contacts with this first conductive plunger.
2. manufacture method as claimed in claim 1 wherein, forms these openings in this first insulating barrier, these openings expose the method for this transistorized source and this conductive layer, also comprise the process of carrying out an anisotropic etching.
3. manufacture method as claimed in claim 1, wherein, form these openings in this first insulating barrier, these openings expose the method for this transistorized source and this conductive layer, also comprise the process of carrying out an anisotropic etching and an isotropic etching successively.
4. manufacture method as claimed in claim 3, wherein, this isotropic etching comprises a wet etch method.
5. manufacture method as claimed in claim 1, wherein, the employed electric conducting material of this memory node comprises one of titanium/titanium nitride/tungsten, titanium/titanium nitride/platinum and titanium/titanium nitride/ruthenium-oxide.
6. manufacture method as claimed in claim 1, wherein, the employed electric conducting material of this first conductive plunger comprises one of titanium/titanium nitride/tungsten, titanium/titanium nitride/platinum and titanium/titanium nitride/ruthenium-oxide.
7. manufacture method as claimed in claim 1, wherein, the employed electric conducting material of this second conductive plunger comprises one of titanium/titanium nitride/tungsten, titanium/titanium nitride/platinum and titanium/titanium nitride/ruthenium-oxide.
8. manufacture method as claimed in claim 1, wherein, the material of this dielectric layer comprises one of tantalum oxide, barium titanate, barium strontium and lead zirconate titanate.
9. manufacture method as claimed in claim 1, wherein, the material of this top electrode comprises one of titanium nitride and tungsten.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US4186898A | 1998-03-12 | 1998-03-12 | |
| US041,868 | 1998-03-12 | ||
| US041868 | 1998-03-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1229272A true CN1229272A (en) | 1999-09-22 |
| CN1159758C CN1159758C (en) | 2004-07-28 |
Family
ID=21918778
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB981152201A Expired - Lifetime CN1159758C (en) | 1998-03-12 | 1998-06-24 | Method for making dynamic RAM and metal link |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN1159758C (en) |
| TW (1) | TW370724B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420001C (en) * | 2005-05-27 | 2008-09-17 | 中芯国际集成电路制造(上海)有限公司 | Method for improving CMP process window of deep slot DRAM tungsten metal bit line |
| US7842603B2 (en) | 2006-06-29 | 2010-11-30 | Hynix Semiconductor Inc. | Method for fabricating semiconductor memory device |
| CN102832165A (en) * | 2011-06-16 | 2012-12-19 | 台湾积体电路制造股份有限公司 | Improved gap filling method for dual damascene process |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI579849B (en) * | 2015-07-15 | 2017-04-21 | 華邦電子股份有限公司 | Memory device and method of manufacturing the same |
-
1998
- 1998-06-04 TW TW087108819A patent/TW370724B/en not_active IP Right Cessation
- 1998-06-24 CN CNB981152201A patent/CN1159758C/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100420001C (en) * | 2005-05-27 | 2008-09-17 | 中芯国际集成电路制造(上海)有限公司 | Method for improving CMP process window of deep slot DRAM tungsten metal bit line |
| US7842603B2 (en) | 2006-06-29 | 2010-11-30 | Hynix Semiconductor Inc. | Method for fabricating semiconductor memory device |
| CN102832165A (en) * | 2011-06-16 | 2012-12-19 | 台湾积体电路制造股份有限公司 | Improved gap filling method for dual damascene process |
| CN102832165B (en) * | 2011-06-16 | 2015-08-19 | 台湾积体电路制造股份有限公司 | The improved gap filling method for dual-damascene technics |
Also Published As
| Publication number | Publication date |
|---|---|
| TW370724B (en) | 1999-09-21 |
| CN1159758C (en) | 2004-07-28 |
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