CN1228818C - Method for forming funnel-shaped dielectric layer window in semiconductor - Google Patents

Method for forming funnel-shaped dielectric layer window in semiconductor Download PDF

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CN1228818C
CN1228818C CN 01110219 CN01110219A CN1228818C CN 1228818 C CN1228818 C CN 1228818C CN 01110219 CN01110219 CN 01110219 CN 01110219 A CN01110219 A CN 01110219A CN 1228818 C CN1228818 C CN 1228818C
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dielectric layer
vias
funnel
layer
etch rate
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CN1378245A (en
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林启发
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华邦电子股份有限公司
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Abstract

一种在半导体组件中的漏斗形介层窗的制造方法,其中修饰过的介层窗的外形是经由改善介层窗开端的尖锐角度及湿式蚀刻部份(诸如,碗形部份)与干式蚀刻部份(诸如,垂直部份)交接处的尖锐角度而得之。 A method of manufacturing a funnel-shaped vias in the semiconductor device in which a modified shape through vias are vias improve a sharp angle and the beginning portion of a wet etch (such as a bowl-shaped portion) and dry etching part (such as a vertical portion) derived from the junction of the sharp angle. 此方法包括下列主要步骤;(1)利用电浆加强式化学气相沉积工艺,以沉积一层基部介电层于晶圆上;(2)沉积一层底部介电层于基部介电层上,其中底部介电层有一第一蚀刻速率;(3)沉积至少一层外形润饰的介电层于底部介电层上;(4)沉积一层顶部介电层于包括至少一层外形润饰的介电层的顶端上,顶部介电层有一第二蚀刻速率,其中第二蚀刻速率高于第一蚀刻速率;(5)形成一层光阻层于顶部介电层上,光阻层有一开口,以便能形成介层窗于多层介电层中;(6)同时利用湿式蚀刻与干式蚀刻工艺,以形成漏斗形介层窗于多层介电层中。 This method comprises the following major steps; (1) using plasma chemical vapor deposition process to strengthen, to deposit a layer of the base dielectric layer on the wafer; (2) depositing a bottom dielectric layer on the base dielectric layer, wherein the bottom dielectric layer having a first etch rate; (3) depositing at least one dielectric layer retouch shape on the bottom dielectric layer; (4) depositing a layer on the top dielectric layer comprises at least one layer of dielectric profile retouch on top of the dielectric layer, top dielectric layer having a second etch rate, wherein the second etch rate is higher than the first etching rate; (5) form a photoresist layer on top of the dielectric layer, the photoresist layer has an opening, in order to form vias in the multilayer dielectric layer; (6) by wet etching while the dry etching process to form a funnel-shaped vias in the multilayer dielectric layer. 所选择的介电层的材质的蚀刻速率能以改变电浆加强式化学气相沉积工艺中的至少一工艺参数来调整。 The selected material of the etch rate of the dielectric layer able to change at least one reinforcing plasma process parameters to adjust chemical vapor deposition process.

Description

在半导体中形成漏斗形介层窗的方法 The method for forming a funnel-shaped vias in a semiconductor

本发明是有关于一种修饰的方法,是有关于“湿式-附随-干式”的工艺(也可以称为一同时进行的“湿式与干式”工艺),在半导体组件中,介层窗典型地是用以连结由介电层分开的二层导电层。 The present invention relates to a method of modification, the process relates to a "wet - - appended dry" (which may be referred to as a "wet and dry" process simultaneously a), a semiconductor component, vias It is typically coupled to the dielectric layer separated by a conductive layer layer. 本发明特别是有关于一种改善“湿式-附随-干式”蚀刻的工艺(利用同时进行的湿式与干式蚀刻工艺),可用此工艺在半导体组件中制造漏斗形(一锥形部份或在垂直部份之上的碗形部份)介层窗。 The present invention particularly relates to an improved etching process is a "wet - - appended dry" (wet and dry etching process using the same time), this process can be used for manufacturing a funnel-shaped (tapered portion in a semiconductor component or bowl over the vertical portion of the part) vias. 本发明也是有关于一种新工艺来改善介层窗制造的方法。 The present invention also relates to a new process to improve the manufacturing method of vias. 本发明的主要优点为能制造具有平滑外形的介层窗,因可大幅改善存在于介层窗与光阻层之间以及湿式蚀刻区域与干式蚀刻区域之间的尖锐夹角。 The main advantage of the present invention is capable of producing vias having a smooth outer shape, the sharp angle present between the vias between the photoresist layer and the wet etching and dry etching region by region can be greatly improved. 本发明的另一主要优点为能制造改良的介层窗,但不会大幅提高制造成本或过度地将工艺复杂化。 Another major advantage of the present invention is capable of producing an improved vias, but does not substantially increase the manufacturing cost or unduly complicating the process.

在制造超大型集成(ULSI)电路时,垂直地堆积或整合复数个金属有线电路或金属层,以形成多重金属构造,已成为一种改善电路性能并且增加电路功能的复杂性的方法。 In the manufacture of very large integration (ULSI) circuits, stacked vertically, or a plurality of integrated circuits metal wire or a metal layer to form multiple metal structure, it has become a method of improving circuit performance and increase the complexity of the circuit functions. 金属有线电路是由所谓的“介层窗”来连结,而介层窗穿越介电层而夹于两层邻近的金属层之间。 Metal wire circuit is coupled to a so-called "vias", and the vias through the dielectric layer sandwiched between two layers adjacent to the metal layers.

首先在介电层中形成一穿通洞,而穿通洞形成于介电层中,且同时位于导电层上。 First, the dielectric layer is formed a through-hole, and the through-hole formed in the dielectric layer, while located on the conductive layer. 接着,于穿通洞中沉积导电材质以形成介层窗,为了提高于穿通洞中沉积导电物质的阶梯覆盖能力,特别是在溅镀沉积工艺中,所以穿通洞通常具有漏斗形的外形,诸如,通常垂直的下部份与由垂直的下部份的口放射出的锥形的部份。 Next, in a through hole depositing conductive material to form vias, in order to improve step coverage in the through-hole deposition of conductive material, particularly in the sputter deposition process, the through hole generally has a funnel-shaped configuration, such as, generally perpendicular to the lower portion of the tapered portion emitted by the vertical part of the mouth. 漏斗形的穿通洞典型地是以所谓的湿式-附随-干式蚀刻工艺来形成的,也就是同时利用湿式蚀刻工艺与干式蚀刻工艺来形成介电层。 The funnel-shaped through hole typically in so-called wet - appended - to form a dry etching process, i.e. while using a wet etching process and a dry etching process to form a dielectric layer. 干式蚀刻工艺主要是非等向性蚀刻,当其施行于介电层中,可以形成一垂直的通路。 Dry etching process mainly non-anisotropic etching, which is performed when the dielectric layer may be formed in a vertical path. 湿式蚀刻工艺主要是等向性蚀刻,其可使主要垂直于干式蚀刻方向的通路变宽。 Wet etching process mainly anisotropic etching, which can widen perpendicular to the main passage direction of dry etching. 当干式蚀刻进行时,随着介电层的深度增加,可借助减少湿式蚀刻的时间来降低湿式蚀刻累积的程度。 When the dry etching is performed with increasing depth of the dielectric layer, can be reduced by wet etching, wet etching time to reduce the degree of accumulation. 以如此方式即可形成漏斗形介层窗(诸如,穿通洞),其是由两部份组成,即均匀宽度的干式蚀刻(诸如,下)部份以及锥形或碗形宽度的湿式蚀刻(诸如,上)部份。 In such a manner to form a funnel-shaped vias (such as, through-hole), which is composed of two parts, i.e. uniform width dry etching (such as, lower) portion and a tapered bowl or wet etching width (such as the) part. 湿式蚀刻(上)部份的宽度是由口(诸如,干式蚀刻下部份与湿式蚀刻上部份的交叉处)到介电层的顶部表面逐渐增加。 Wet etching width (upper) part is (such as a part of the intersection of the upper portion and dry etching, wet etching) to the top surface of the dielectric layer gradually increases from the mouth.

依照公知的湿式-附随-干式工艺所形成的漏斗形介层窗的缺点为锥形部份有一非常跿峭的向上曲线部份。 In accordance with well-known wet - appended - funnel-shaped vias disadvantage dry process part is formed in a tapered portion with an upward curve of a very steep Tu. 如此跿峭的部份能降低阶梯覆盖能力,但是形成漏斗形的介层窗本是为了提高阶梯覆盖能力。 Tu so steep part reduces step coverage, but is formed funnel-shaped vias is present in order to improve step coverage. 为了在后续的溅镀沉积工艺中尽可能提高阶梯覆盖能力,锥形部份应越平滑越佳,而接近介层窗顶端的跿峭的向上曲线部份应大福地加以缓和。 In order to improve the step coverage as possible in the subsequent sputter deposition process, the smoother tapered portion should be the better, the curve upward portion near the top layer of dielectric window should be large steep Tu blessed be alleviated.

依照公知的湿式-附随-干式工艺所形成的漏斗形介层窗的另一缺点为于干式蚀刻部份与湿式蚀刻部份之间有尖锐夹角,以及介层窗与光阻层之间(也就是介层窗于介电层顶端的表面的流出角)也有尖锐夹角。 In accordance with well-known wet - appended - Another drawback of the funnel-shaped vias are formed by dry process is at a sharp angle, and vias with photoresist layers between dry etching and wet etching part portion Room (i.e. the outflow angle of the surface of the dielectric window at the top of the dielectric layer) is also a sharp angle. 尖锐的流出角也与上述介层窗的锥形部份的跿峭的向上曲线部份有关。 Sharp upward curve portion and the outflow angle also tapered portion of said vias is about Tu steep. 这些尖锐的夹角会造成总工艺的一些盲点而降低了产量。 These sharp angle will cause some blind spots and reduces total process yield.

在高竞争力的半导体工业中,重要的是要注意到每一种可能改善产量的方式。 In the highly competitive semiconductor industry, it is important to note that every possible way to improve the yield. 尤其较佳的是那些可以有效的运用成本的方式。 Particularly preferred are those ways to use cost effective.

因此本发明的主要目的是在半导体组件中发展出一种制造外型改良的介层窗的方法。 The main object of the present invention therefore is to develop a method of manufacturing a vias improved appearance in a semiconductor component. 特别是本发明的主要目是在发展出一种制造具有平滑锥形部份的介层窗的方法,使得在后续的溅镀程序中,以导电物质填满介层窗时,能达到最佳的阶梯覆盖能力。 In particular the main object of the invention is a method of manufacturing a dielectric window having a smooth tapered part of the development, so that in the subsequent sputtering process, when the conductive material to fill the vias, can achieve the best the step coverage. 利用本发明来制造介层窗,也能消除湿式蚀刻部份与光阻层之间的尖锐夹角,以及蚀刻部份与干式蚀刻部份的尖锐夹角。 The present invention is manufactured using vias, but also to eliminate the sharp angle between the portion of the photoresist layer by wet etching, and the etched portion with a sharp angle part of the dry etching.

本发明揭露的方法可以概括于下列主要步骤:1、沉积一层底部介电层于晶圆上,底部介电层有一第一蚀刻速率;2、沉积至少一层外形润饰的介电层于底部介电层上;3、沉积一层顶部介电层于包括至少一层外形润饰的介电层的顶端上,顶部介电层有一第二蚀刻速率,其中第二蚀刻速率高于第一蚀刻速率;4、形成一层光阻层于顶部介电层上,光阻层有一开口,以便能形成介层窗于多层介电层中;5、同时利用湿式蚀刻与干式蚀刻程序,以形成漏斗形介层窗于多层介电层中。 The method disclosed in the present invention can be summarized in the following major steps: 1, depositing a bottom dielectric layer on a wafer, a bottom dielectric layer has a first etch rate; 2, depositing at least one dielectric layer retouch shape at the bottom the dielectric layer; 3, depositing a layer on the top dielectric layer including at least one dielectric layer to the top of the outer shape of retouching, top dielectric layer having a second etch rate, wherein the second etch rate is higher than the first etch rate ; 4, form a photoresist layer on top of the dielectric layer, the photoresist layer with an opening so as to form vias in the multilayer dielectric layer; 5, while the use of wet etching and dry etching procedures to form funnel-shaped vias of the multilayer dielectric layer.

在沉积底部介电层前,先沉积一层基部介电层于晶圆上。 Before deposition the bottom dielectric layer, depositing a first dielectric layer on the base wafer. 同时地进行湿式蚀刻与干式蚀刻程序,漏斗形介层窗的垂直部份是通常形成于基部介电层中,而漏斗形介层窗的锥形部份通常形成于多层介电层中。 Simultaneously subjected to wet etching with a dry etching process, the vertical part of the funnel-shaped vias are usually formed in the base dielectric layer, and a conical funnel portion vias are typically formed in the multilayer dielectric layer . 然而漏斗形介层窗的垂直部份能部份伸入多层介电层中,同样地,漏斗形介层窗的锥形部份也能部份伸入基部介电层中。 However, the vertical portion of the funnel-shaped portion can extend into the vias in the dielectric layers, similarly, the tapered portion of the funnel-shaped vias can also extend into the base portion of the dielectric layer. 外型润饰的介电层的较佳蚀刻速率是介于第一蚀刻速率与第二蚀刻速率之间。 Exo retouch preferred etch rate of the dielectric layer is interposed between the first etch rate and the second etch rate. 倘若外型润饰的介电层的层数多于一层,此多层外型润饰的介电层的较佳蚀刻速率应随着距离晶圆越远而越大。 If the number of layers retouch appearance of more than one layer of the dielectric layer, the multilayer appearance retouch preferred etch rate of the dielectric layer should be larger as the distance from the wafer. 在最佳地情况下,对所有的介电层而言,应为连续地增加从底部介电层到顶部介电层的蚀刻速率,以获得非常平滑的介层窗外形。 In the best case, for all the dielectric layers, it should be increased continuously from the bottom of the etch rate of the dielectric layer to the top dielectric layer to obtain a very smooth profile vias.

在正常情况下,沉积比较多的介电层(诸如,基部介电层、底部介电层、至少一层外形润饰的介电层以及顶部介电层)在晶圆上,通常涉及冗长而且昂贵的工艺。 Under normal circumstances, more of depositing a dielectric layer (such as, a base dielectric layer, a bottom dielectric layer, an outer shape of the dielectric layer and the retouch top dielectric layer) on a wafer, typically it involves lengthy and expensive process. 因此,本发明的另一重要方面为能以相对简单的方式来形成这些多层介电层,所有这些介电层都是在略为改变沉积的条件下,以相同的沉积工艺来沉积的。 Therefore, another important aspect of the present invention is capable of a relatively simple manner to form these dielectric layers, all of which dielectric layers are deposited under conditions change slightly, the same deposition deposition process.

本发明更特别的是能利用观测方式来调整蚀刻速率,电浆加强式化学气相沉积的介电层的蚀刻速率(干式与湿式)可经由改变一个或两个工艺参数而调整之,譬如反应气体的分压、产生电浆的射频功率、温度以及气体成份的比例,等等。 More particularly, the present invention is able to use the observation way to adjust the etch rate, plasma etch rate of the dielectric layer to strengthen the chemical vapor deposition (dry and wet) can be adjusted by varying one or both of the process parameters, such as the reaction partial pressure of the gas, the plasma generating RF power ratio, temperature, and gas composition, and the like. 若选择适当的介电材质,则介电材质的蚀刻速率可经由改变一个或多个工艺参数而调整之。 When selecting an appropriate dielectric material, the dielectric etch rate of the material can be electrically adjusted by varying one or more of the process parameters. 以有效地运用成本的方式,通过控制这些工艺参数,可依电浆加强式化学气相沉积工艺来形成最适宜的具有不同蚀刻速率分布的混合介电层,以便在后续工序中,能形成具有圆润外形的漏斗形介层窗,因此消除了介层窗的顶部以及垂直部份与碗形部份的交接处的尖锐角度。 Use of cost-effective manner, by controlling the process parameters, to follow reinforcing plasma chemical vapor deposition process to form the most suitable mixing dielectric layers having different etch rate distributions, in a subsequent step for, can be formed having rounded funnel shape vias, thereby eliminating the acute angle of the top portion and perpendicular to the intersection with the bowl-shaped portion of the vias.

为让本发明能更明显易懂,下文特举较佳实施例,并配合所附图式,作详细说明如下:图面说明:图1为公知的漏斗形介层窗的制造侧视图;图2为依照本发明的较佳实施例的一种漏斗形介层窗的制造侧视图。 In order to make the present invention can be more fully understood by reading the following preferred embodiments and accompanying figures, described in detail below: Description drawings: FIG. 1 is a side view of a known manufacturing a funnel-shaped vias; and FIG. 2 is a side view of one kind of funnel for producing vias in accordance with the preferred embodiment of the present invention. 此漏斗形介层窗具有平滑的外型,而其交接处的尖锐夹角已获得改善;图3为氧化硅的干式蚀刻速率与湿式蚀刻速率分别相对于氧/硅比例的变化图。 This funnel-shaped vias having a smooth appearance, and sharp angle junction which has been improved; FIG. 3 is a dry etching rate of wet etching rate of silicon oxide with respect to oxygen / silicon ratio changes FIG. 而氧/硅比例为在进行电浆加强式化学气相沉积工艺的反应室内,氧气与硅化氢的比例,以形成氧化硅于硅基底上;以及图4为依照本发明的较佳实施例连续改变电浆加强式化学气相沉积的工艺参数。 The ratio of oxygen / silicon ratio strengthening chemical vapor deposition process for performing plasma reaction chamber, oxygen and silicon hydrides to form a silicon oxide on the silicon substrate; and Figure 4 is continuously changed in accordance with the preferred embodiment of the present invention. Sharpening plasma chemical vapor deposition process parameters.

附图标记说明:1:漏斗形介层窗2:碗形上部份3:垂直下部份4:介层窗出口处的尖锐角度5:碗形部份与垂直部份的交接处的尖锐角度10:漏斗形介层窗11:多层介电层构造12:基部介电层13:底部介电层 REFERENCE NUMERALS: 1: 2 vias funnel: a bowl-shaped section 3: vias sharp angle at the outlet 5:: a bowl-shaped part 4 vertical portion of the vertical part of the sharp junction angle 10: funnel-shaped vias 11: multilayer dielectric structure 12: base dielectric layer 13: a bottom dielectric layer

14:复数个外形润饰的介电层15:顶部介电层16:获得改善的介层窗出口处的角度17:获得改善的碗形部份与垂直部份交接处的角度实施例本发明提供在半导体组件中新的的制造漏斗形介层窗的方法以改善介层窗的外形。 14: a plurality of dielectric layers shape retouch 15: top dielectric layer 16: the angle at the outlet of vias of improved 17: improved portion of the vertical portion of the bowl-shaped junction of the embodiment of the present invention to provide an angle the new method of manufacturing a funnel-shaped vias in the semiconductor assembly to improve the appearance of the vias. 本发明的漏斗形介层窗相较于公知的漏斗形介层窗有较平滑的锥状部份,或至少改善了介层窗的开端及湿式蚀刻(诸如碗形部份)与干式蚀刻(诸如垂直部份)交接处的尖锐角度,在后续的溅镀工序中,以导电物质填满介层窗时,能达到最佳的阶梯覆盖能力。 A funnel-shaped funnel-shaped vias vias compared to the present invention there is known a smoother tapered portion, or at least improved and vias start wet etching (such as a bowl-shaped portion) and the dry etching junction of the sharp angle (such as a vertical part), in the subsequent sputtering step, when the conductive material to fill the vias, to achieve optimum step coverage.

本发明的方法可以概括于下列主要步骤:1、沉积一层基部介电层于晶圆上;2、沉积一层底部介电层于基部介电层上,底部介电层有一第一蚀刻速率;3、沉积至少一层外形润饰的介电层于底部介电层上;4、沉积一层顶部介电层于包括至少一层外形润饰的介电层的顶端上,顶部介电层有一第二蚀刻速率,其中第二蚀刻速率高于第一蚀刻速率;5、形成一层光阻层于顶部介电层上,光阻层有一开口,以便能形成介层窗于多层介电层中;6、同时利用湿式蚀刻与干式蚀刻工艺,以形成漏斗形介层窗于多层介电层中。 The method of the present invention can be summarized in the following major steps: 1, depositing a dielectric layer on the base wafer; 2, depositing a bottom dielectric layer on the base dielectric layer, a bottom dielectric layer having a first etch rate ; 3, depositing at least one dielectric layer retouch shape on the bottom dielectric layer; 4, depositing a dielectric layer on top of the top dielectric layer comprises at least one shape retouched, the top dielectric layer having a first second etching rate, wherein the second etch rate is higher than the first etching rate; 5, form a photoresist layer on top of the dielectric layer, the photoresist layer with an opening so as to form the vias in the dielectric layers ; 6, while the use of wet etching and dry etching process, to form a funnel-shaped vias in the multilayer dielectric layer.

请参照图1,其所绘示为公知漏斗形介层窗1的制造侧视图。 Referring to FIG 1, which are well-known for producing depicted a side view of the funnel-shaped vias 1. 介层窗1包括一碗形上部份是等向性湿式蚀刻(与干式蚀刻)多层介电层后而形成的,垂直的下部份3是主要由于非等向性干式蚀刻多层介电层后而形成的。 Vias 1 comprises a bowl-shaped upper portion is isotropic wet etching (dry etching) after the multilayer dielectric layer is formed, the vertical part 3 is mainly due to the anisotropic dry etching plurality after the interlayer dielectric layer is formed. 图1显示碗形上部份的外形斜率连续的增加,以致在介层窗出口处有尖锐的角度4。 Figure 1 shows part of the bowl-shaped appearance on the slope increases continuously, so that a sharp angle of vias 4 in the outlet. 图1亦显示在碗形湿式蚀刻部份2与垂直的干式蚀刻部份3的交接处有另一尖锐角度5。 Figure 1 also shows the wet etching in the bowl part 2 with the junction perpendicular to dry etching of the portion 3 has a further acute angle of 5.

请参照图2,其所绘示的即是依照本发明的较佳实施例的漏斗形介层窗的制造侧视图。 Referring to FIG 2, which is depicted i.e. for producing side view of a funnel-shaped vias of the preferred embodiment of the present invention. 介层窗10是形成于一润饰过的多层介电层构造11中,多层介电层构造11包括一层基部介电层12、一层底部介电层13、复数个外形润饰的介电层14以及一层顶部介电层15。 Vias 10 formed in a retouched structure of dielectric layers 11, the multilayer structure 11 of the dielectric layer 12, a dielectric layer of a bottom layer of a base layer comprising a dielectric layer 13, a plurality of retouch shape mediators dielectric layer 14 and a 15 layer top dielectric layer. 图2显示一较平滑的介层窗外形10,而明显改善了交接处的尖锐角度16、17。 2 shows a smoother appearance vias 10, and the acute angle significantly improved junction 16, 17. 虽然基部介电层12与底部介电层13以不同的名称来描述之,但若以相同的工艺参数来沉积基部介电层12与底部介电层13,则此二层即可合并为一层。 Although the base dielectric layer 12 and the bottom dielectric layer 13 with different names to describe it, but if the same process parameters to be deposited of the base dielectric layer 12 and the bottom dielectric layer 13, then this can be combined into a Layer Floor. 虚线部份是依照公知的工艺所形成的介层窗外形。 Dotted line is part of vias in accordance with well-known process shape is formed.

基部介电层上的多层介电层也可以合称为非基部多层介电层构造。 The multilayer dielectric layer on the base dielectric layer may be collectively referred to as a non-base layer of a multilayer dielectric structure. 同时的进行湿式蚀刻与干式蚀刻工艺,漏斗形介层窗的垂直部份是通常形成于基部介电层中,而漏斗形介层窗的碗形部份通常形成于基部介电层上的多层介电层中(诸如非基部多层介电层构造)。 Wet etching is performed simultaneously with the dry etching process, the vertical part of the funnel-shaped vias are usually formed in the base dielectric layer, and a funnel-shaped bowl portion vias are usually formed on the base dielectric layer the multilayer dielectric layer (dielectric layers, such as non-base configuration). 然而漏斗形介层窗的垂直部份能部份伸入多层介电层中,同样地,漏斗形介层窗的碗形部份也能部份伸入基部介电层中。 However, the vertical portion of the funnel-shaped portion can extend into the vias in the dielectric layers, in the same manner, bowl-shaped part of the funnel-shaped vias can also extend into the base portion of the dielectric layer. 外型润饰的介电层的较佳蚀刻速率是介于第一蚀刻速率与第二蚀刻速率之间。 Exo retouch preferred etch rate of the dielectric layer is interposed between the first etch rate and the second etch rate. 倘若外型润饰的介电层的层数多于一层,此多层外型润饰的介电层的较佳蚀刻速率应随着距离晶圆越远而越大。 If the number of layers retouch appearance of more than one layer of the dielectric layer, the multilayer appearance retouch preferred etch rate of the dielectric layer should be larger as the distance from the wafer. 在最佳地情况下,对所有的介电层而言,应为连续的增加从底部介电层到顶部介电层的蚀刻速率,以获得非常平滑的介层窗外形。 In the best case, for all the dielectric layers, it should be increased continuously from the bottom of the etch rate of the dielectric layer to the top dielectric layer to obtain a very smooth profile vias.

在本发明的工艺中,所选择的较佳介电材质的蚀刻速率能随着改变电浆加强式化学气相沉积工艺的一个或多个参数而调整之,譬如反应气体的分压、产生电浆的射频功率、温度以及气体成份的比例,等等。 In the process of the present invention, the preferred etch rate of dielectric materials selected can enhance the change with a plasma chemical vapor deposition process or a plurality of adjustment parameters, such as the partial pressure of the reaction gas, plasma is generated RF power, temperature, and gas composition ratio, and the like.

作为上述关联的例子,请参照图3,其所绘示为四乙基硅酸盐(tetra-ethy1-ortho-silicate,TEOS)的干式蚀刻速率与湿式蚀刻速率分别相对于氧/硅比例的变化图,而氧/硅比例为在进行电浆加强式化学气相沉积程序的反应室内,氧气与硅化氢的比例,以形成氧化硅于硅基底上。 Examples of the associated Referring to FIG 3, which is depicted as tetraethyl silicate (tetra-ethy1-ortho-silicate, TEOS) and the dry etching rate of wet etching rate with respect to oxygen / silicon ratio FIG change, and the oxygen / silicon ratio of the proportion of reinforcing the reaction chamber of the chemical vapor deposition process, a silicon hydride of oxygen plasma is performed to form a silicon oxide on the silicon substrate. 同样地,可改变反应室射频的功率或改变温度或反应气体的分压来调整四乙基硅酸盐的干式蚀刻速率与湿式蚀刻速率。 Likewise, the reaction chamber may be varied or changing the RF power or the temperature of the reaction gas partial pressure to adjust the dry etching rate of wet etching rate of tetraethyl silicate. 若选择适当的介电材质,而介电材质的蚀刻速率可经由改变一个或多个工艺参数而调整之,通过控制这些工艺参数,可依电浆加强式化学气相沉积工艺,形成最适宜的具有不同蚀刻速率分布的混合介电层,以便在后续工序中,能形成具有平滑外型的漏斗形介层窗,而改善了介层窗的顶部以及垂直部份与碗形部份的交接处的尖锐角度。 When selecting an appropriate dielectric material, and the etch rate of the dielectric material may be altered by one or more process parameters and adjustments, by controlling the process parameters, to follow reinforcing plasma chemical vapor deposition process, the most suitable form having mixing dielectric layers having different etch rate distributions, in a subsequent step to, can form a funnel-shaped dielectric window having a smooth appearance, and improves the top of the vias and the vertical part of the junction portion of the bowl acute angle.

因为本发明并不需要费很大的功夫来增加外形润饰的介电层的层数,在实际的应用上,能控制介电层的蚀刻率的工艺条件是以连续的方式来调整之,诸如工艺可分成许多步骤,而每一步骤代表增加少许的紧接着的前一步骤的工艺参数,以致在外形润饰的介电层中,形成一蚀刻速率分布的梯度。 Since the present invention does not require great effort to increase the charge layers of the dielectric layer shape retouched, in actual application, the dielectric layer can be controlled process conditions is to adjust the etching rate of a continuous manner, such as process can be divided into a number of steps, and each step of the process parameter indicative of the added immediately before a little step, so that the outer shape of the dielectric layer of polish, a gradient of an etch rate profile. 请参照图4,工艺参数可为反应气体的分压、产生电浆的射频功率、温度以及气体成份的比例,等等。 Please refer to the ratio of the partial pressure of process parameters may be the reaction gas, generating RF power, temperature, and gas composition of the plasma of FIG. 4, and the like. 必要时,湿式浸泡工艺能用来细部地修饰蚀刻后的介层窗的外形。 If necessary, a wet process can be used to soak detail modifying the shape of the vias after etching.

介层窗的碗形部份的整个外形以及碗形部份与垂直部份的交角,能进一步由调整基部介电层的蚀刻速率来控制之。 Entire contour portion and the vertical portion of the bowl the bowl-shaped part of the crossing angle of the vias can be further controlled by the adjustment of the etch rate of the dielectric layer of the base. 必要时,基部介电层中也有蚀刻速率分布的梯度,诸如干式蚀刻的蚀刻速率随着距离晶圆越远而越小,可进一步减少碗形部份与垂直部份的交角。 If necessary, a base dielectric layer has a gradient distribution of etch rate, etch rate such as dry etching and smaller farther away from the wafer can be further reduced and the vertical part of the bowl-shaped portion intersecting angle. 增加干式蚀刻速率可以减少干式蚀刻所需的时间,因此,减少了垂直于干式蚀刻方向的湿式蚀刻程度,也因此减少了碗形部份与垂直部份的夹角。 Increase the rate of dry etching can reduce the time required to dry etching, thus reducing the degree of wet etching dry etching perpendicular direction, thus reducing the angle between the vertical part of the bowl-shaped portion.

下列的范例将更详细的说明本发明。 The present invention is described in detail in the following examples more. 虽然下列的范例,包括本发明的较佳实施例,是为了说明本发明而揭露的例子,然其并非为了用以限定本发明。 Although the following examples, including the preferred embodiment of the present invention, to illustrate the present invention and examples disclosed, they are not intended to limit the invention.

在进行电浆加强式化学气相沉积程序的反应室内,借着调整含硅的SiH4成份气体与含氧的O2成份气体的气流比例,而沉积一系列的四乙基硅酸盐层于晶圆上。 Strengthening performing plasma chemical vapor deposition process in the reaction chamber, the gas flow by adjusting the ratio of SiH4 silicon-containing gas and oxygen-containing components of the gas components O2, deposited a series of tetraethyl silicate layers on the wafer . 于以NH4F作为缓冲之用的HF化学蚀刻溶液中,测试由不同化学气相组合而成的具有不同化学计量的氧化硅层的蚀刻速率。 In NH4F HF chemical etching solution to use as a buffer, a test composition different from the chemical vapor etching rate of the silicon oxide layer having a different stoichiometry. 测试结果摘要于表一。 Summary of test results in Table 1.

表一 Table I

如表一所示,在电浆加强式化学气相沉积工艺中,当气流中的氧/硅的比例增加,则相对应沉积的四乙基硅酸盐的蚀刻速率亦增加。 As shown in Table I, reinforcing chemical vapor deposition process, an increased proportion of oxygen in the gas flow / silicon, the etch rate of deposition corresponding tetraethyl silicate is also increased in the plasma. 同时进行湿式蚀刻与干式蚀刻包含有不同计量的四乙基硅酸盐层的晶圆,以形成具有平滑外形的碗形部份的漏斗形介层窗,如图2所示。 Simultaneously with wet etching comprises dry etching the wafer of different measurement tetraethyl silicate layers, to form a bowl-shaped portion has a smooth outer shape of a funnel-shaped vias, as shown in FIG. 图2亦显示若加宽垂直部份(诸如,干式蚀刻所形成的下部份)的宽度,不会影响由湿式蚀刻所形成的上部份的总体宽度。 Figure 2 also shows that if the widened vertical portion (such as a lower portion formed by dry etching) width, will not affect the overall width of the upper portion of a formed wet etching.

虽然本发明为了说明,已以较佳实施例揭露如上,但依照本发明而作的各种明显的改进与变型是有可能的。 Although the present invention is for purposes of illustration, the preferred embodiment has been described above, it is made in accordance with the present invention and various obvious modifications and variations are possible. 所选择的实施例及其中的描述提供了本发明的原则以及实际应用的最佳说明,使得任何熟习此技艺者能利用本发明于各种的实施例中,也可以为了特殊用途而作各种改进。 The embodiment chosen and described in embodiments of the present invention provides principles and best illustrate the actual application, such that any person skilled in this art to the embodiment can utilize the invention in various embodiments, may be made for various specific purposes Improve. 本发明的保护范围当以权利要求书为准。 The scope of the present invention the following claims and equivalents.

Claims (8)

1.一种在半导体中形成漏斗形介层窗的方法,其特征在于:包括:(a)沉积一基部介电层于一晶圆上;(b)沉积一底部介电层于该基部介电层上,该底部介电层有一第一蚀刻速率;(c)沉积至少一外形润饰的介电层于该底部介电层上;(d)沉积一顶部介电层于该至少一层外形润饰的介电层上,其中该顶部介电层有一第二蚀刻速率,而且该第二蚀刻速率高于该第一蚀刻速率,其中该底部介电层,该至少一层外形润饰的介电层以及该顶部介电层合称为一非基部介电层,而且全部该介电层的蚀刻速率是以改变电浆加强式化学气相沉积工艺中的至少一工艺参数来调整;以及(e)同时进行一湿式蚀刻与干式蚀刻工艺于一光阻层配合情况下,以形成漏斗形介层窗,漏斗形介层窗有一碗形上部份与一通常垂直的下部份,分别位于该非基部介电层与该基部介电层中。 1. A method for the funnel-shaped vias are formed in the semiconductor, characterized by: comprising: (a) depositing a base dielectric layer on a wafer; (b) depositing a bottom dielectric layer on the base dielectric the dielectric layer, the bottom dielectric layer having a first etch rate; (c) depositing a dielectric polish profile layer on at least the bottom dielectric layer; (d) depositing a dielectric layer on the top of at least one profile retouched on the dielectric layer, wherein the top dielectric layer having a second etch rate, and the second etch rate is higher than the first etch rate, wherein the bottom dielectric layer, the at least one layer of a dielectric layer shape retouch and the top dielectric layer are collectively referred to a non-base dielectric layer, the dielectric layer and all of the etch rate of the at least one process parameter is changed to adjust the reinforcing plasma chemical vapor deposition process; and (e) simultaneously performing a wet etching and a dry etching process in a case where the photoresist layer with, to form a funnel-shaped vias, vias with a funnel-shaped with a bowl-shaped portion and a generally vertical lower portion, which are located in non- a base dielectric layer and the base dielectric layer.
2.如权利要求1所述的在半导体中形成漏斗形介层窗的方法,其特征在于:其中该步骤(c)包括形成至少二层该外形润饰的介电层的次步骤。 The method for forming a funnel-shaped vias in a semiconductor as claimed in claim in claim 1, wherein: wherein the step (c) comprises the step of forming at least a secondary dielectric layer of the floor polish of the outer shape.
3.如权利要求1所述的在半导体中形成漏斗形介层窗的方法,其特征在于:其中该介电层的材质的蚀刻速率能以改变电浆加强式化学气相沉积工艺中的一反应气体的分压、产生电浆的射频功率、温度以及气体成份的比例来调整。 3. The method for forming a funnel-shaped vias in a semiconductor according to claim 1, wherein: wherein the etch rate of the dielectric layer material can be changed to strengthen a reactive plasma chemical vapor deposition process partial pressure of the gas, the plasma generating RF power, temperature, and gas composition ratio can be adjusted.
4.如权利要求1所述的在半导体中形成漏斗形介层窗的方法,其特征在于:其中该介电层为四乙基硅酸盐是以一含硅的成份与一含氧的成份的气体组合沉积而得的。 4. A method for forming a funnel-shaped vias in a semiconductor according to claim 1, wherein: wherein the dielectric layer is a silicon-containing tetraethyl silicate and an oxygen-containing ingredients ingredients the gas composition obtained by deposition.
5.如权利要求4所述的在半导体中形成漏斗形介层窗的方法,其特征在于:其中该含硅的成份为SiH4与该含氧的成份为O2气体。 5. The method for forming a funnel-shaped vias in a semiconductor as claimed in claim 4, wherein: wherein the silicon-containing ingredients is SiH4 and the oxygen-containing component is O2 gas.
6.如权利要求1所述的在半导体中形成漏斗形介层窗的方法,其特征在于:其中选择该第二蚀刻速率,使得接近该介层窗外形顶端的斜率减少。 6. A method as claimed in claim 1 said funnel-shaped vias are formed in the semiconductor, characterized in that: wherein selecting the second etch rate, such that the vias close to the top of the slope to reduce the outer shape.
7.如权利要求1所述的在半导体中形成漏斗形介层窗的方法,其特征在于:其中该步骤(c)包括形成复数层外形润饰的介电层的次步骤,且该些外形润饰的介电层具有连续增加的蚀刻速率。 7. A method for forming a funnel-shaped vias in a semiconductor according to claim 1, wherein: wherein the step (c) a plurality of times a step shape retouch layer comprises a dielectric layer is formed, and the plurality of profile retouch the dielectric layer has an etch rate increases continuously.
8.如权利要求1所述的在半导体中形成漏斗形介层窗的方法,其特征在于:其中该基部介电层包括复数层次层,且该些次层的蚀刻速率随着该次层与该晶圆的距离增加而减少。 8. A method for forming a funnel-shaped vias in a semiconductor according to claim 1, wherein: the base portion wherein the dielectric layer comprises a plurality of hierarchical layers, and the plurality of times the etch rate of the layer with the sublayer from the wafer increases.
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