CN1207917C - High-speed low power consumption MQ encoder applicable dto JPEG2000 standard - Google Patents

High-speed low power consumption MQ encoder applicable dto JPEG2000 standard Download PDF

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CN1207917C
CN1207917C CN 03129690 CN03129690A CN1207917C CN 1207917 C CN1207917 C CN 1207917C CN 03129690 CN03129690 CN 03129690 CN 03129690 A CN03129690 A CN 03129690A CN 1207917 C CN1207917 C CN 1207917C
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probability
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华林
朱珂
周晓方
章倩苓
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Fudan University
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Abstract

The present invention relates to a high-speed low-consumption MQ encoder suitable for the JPEG 2000 standard. On the premise of guaranteeing that the result completely coincides with that of the compression of the JPEG 2000 standard, the present invention provides improvements for a spacing calculation part, an interval reformation part and a byte output part in the MQ encoding algorithm, and designs the MQ encoder according to the structure of a three-level flow type parallel circuit. The present invention has greater improvement in the processing speed, the chip area, the power consumption, etc., and can satisfy the requirements of a plurality of high-grade mobile multimedia devices.

Description

Be applicable to the high-speed low-power-consumption MQ encoder of JPEG2000 standard
Technical field
The present invention relates to a kind of high-speed low-power-consumption adaptive binary arithmetic coding device (MQ encoder) of the JPEG2000 of meeting standard.
Background technology
Adaptive binary arithmetic coding is a kind of lossless data compression technology, it can remove the redundancy in the initial data effectively, the actual compression effect is better than Huffman encoding, and need not to transmit the Huffman code table, so be widely used in the fields such as compression of medical image, text and executable code.
Traditional binary arithmetic coding is that an information table that is encoded is shown as an interval between real number 0 and 1.Information is long more, and more little at interval, figure place is many more.Continuous symbol reduces at interval according to the size of a certain pattern generating probability in the information source.The symbol that may occur lacks than the scope that the symbol that occurs not too easily reduces, and therefore only increases less bit.Full breadth before any information of transmission is [0,1].When a symbol was processed, this scope just narrowed down according to distributing to that part of of this symbol.Otherwise, can return to serial data from code string from the inverse process of coding with relatively big or small method.
In recent years, binary arithmetic coding has had new development again, and its improvement mainly concentrates on " adaptive probability estimation model " and the optimization of " reformation in fixed length interval " and the aspects such as reduction of algorithm complex.The ABIC of IBM (compression of self adaptation bi level image) has adopted the Q encoder to carry out adaptive binary arithmetic coding, and its template comprises 7 neighboring pixels, totally 128 contexts (context).The JBIG standard has adopted the QM encoder, and its template comprises 10 neighboring pixels, totally 1024 contexts.About the detailed content of ABIC and JBIG referring to J.L.Mitchell and W.B.Pennebaker, " Optimal hardware and software arithmetic codingprocedures for the Q-coder; " IBM J.Res.Develop., vol.32, no.6, pp.727-736, Nov.1988. and W.B.Pennebaker, J.L.Mitchell, G.G.Langdon, Jr., and R.B.Arps, " An Overview of the Basic Principles of theQ-Coder Adaptive Binary Arithmetic Coder, " IBM J.Res.Develop.32,717-726 (1988)..
The MQ encoder is the another kind of improved Q encoder that the JPEG2000 standard is adopted, and it is also adopted by the JBIG2 standard.Compare with the Q encoder, the MQ encoder has been inherited approximate, the interval automatic adjustment of fixed length of no multiplication and the strategy of position buffer memory, has increased the Bayesian learning process in condition exchange and the probability Estimation state machine.The probability Estimation template of MQ encoder comprises 8 neighboring pixels, totally 19 contexts (context), 47 probability states.
Fig. 1 has shown the input of MQ encoder.According to the JPEG2000 standard, original image produces wavelet coefficient through wavelet transformation, and these wavelet coefficients are sent into the MQ encoder through context CX (ConteXt) and the data D to be compressed that generates behind the Bit-Plane Encoding, the code stream CD that output was at last compressed.
Whole cataloged procedure can be divided into probability Estimation, interval calculation, interval reformation and four key steps such as exchange, byte output, and initialization and ending (FLUSH), wherein interval reformation and exchange and byte output two go on foot to have only when condition is suitable just to be carried out (as shown in Figure 2).In detail software flow pattern can be referring to the JPEG2000 standard: ISO/IEC 15444-1:JPEG 2000 image coding system, 2000, (FinalCommittee Draft Version 1.0).
In the MQ coding, represent the small probability symbol with LPS, its probability is Qe; Represent big probability symbol with MPS, its probability is 1-Qe.Two special register A and C are set during coding, and the numerical value among the register A is the width in subinterval, and promptly at interval, the numerical value among the register C is the original position in subinterval, still represents with A, C respectively.
In traditional binary arithmetic coding, C and A constantly revise by following rule:
When low probability symbol LPS arrives C = C A = A × Qe
When high probability symbols MPS arrives C = C + A × Qe A = A - A × Qe
C+A is the right endpoint in subinterval, and the result of arithmetic coding drops in [C, C+A] subinterval.
Because A ≈ 1, the MQ encoder has carried out approximate processing in order to improve arithmetic speed to multiplying:
When low probability symbol LPS arrives C = C A = Qe
When high probability symbols MPS arrives C = C + Qe A = A - Qe
By the makeover process of C and A as can be known, the absolute value of C and A constantly reduces, and the figure place behind the decimal point is more and more longer, and this is unfavorable for the realization of hardware.The interval reformation is in A<0.75 o'clock, C and A be multiply by 2, until 0.75≤A<1.5 (see figure 3)s.
When low probability symbol LPS arrived very continually, the value of Qe can increase to more than 0.5 gradually, and at this moment the interval of low probability symbol LPS will be greater than the interval of high probability symbols MPS.For fear of this situation, MPS and LPS can be exchanged (see figure 4).
The MQ encoder adopt one can be to the automatic estimation model of probability of the complexity of initial data fast adaptation, it has the finite state machine of 47 states, and each state is corresponding to a probability Estimation Qe, next state (NMPS or NLPS) and condition switching signal (SWITCH).These states are organized the ordering (see figure 5) with adaptive level, the so automatic estimation model of probability of all corresponding cover of each context (CX).
When beginning to encode, encoder does not comprise the prior information of image, is assumed to be approximately equalised initial probability distribution so adopt 0 state to represent.After a pixel was encoded, the index of the appointed new pixel content of this model upgraded.After the arrival of each big probability symbol (MPS), automatic state machine just jumps to the next state that is positioned at the delegation right side, and it has less LPS probability.After the arrival of each small probability symbol (LPS), automatic state machine just jumps to and is positioned at the suitable position (when this state is transition state) of one deck down, or with the preceding state (when this state is non-transition state) of delegation, it has bigger LPS probability.Therefore, transition state only can be accessed at learning phase, and pointer can be stable at stable state at last.If variation had taken place again probability statistics afterwards,, also can come back to transition state from stable state in order to carry out local adaptation.
Though omitted multiplying, reform in loaded down with trivial details interval judgement, frequent interval and complicated byte output makes that still the software execution speed of MQ encoder is lower.Therefore, the VLSI of high speed MQ encoder realizes very necessary for the realtime graphic compressibility.In recent years, many experts realize studying to the hardware of binary arithmetic coder (comprising Q encoder and QM encoder), but for the MQ encoder, because algorithm is newer, its VLSI is implemented in and belongs to the forward position both at home and abroad, and are little ripe.M.Boo for example, JDBruguera and T. Lang " A Vlsi Architecture For Arithmetic Coding Of Multi-Level Images " IEEETransactions on Circuits and Systems-II, vol.45, NO.1, January 1998; And the H.H.Chen in Taiwan, C.J.Lian, K.F.Chen, L.G.Chen, " Contextbased Adaptive Arithmetic Encoder Design for JPEG 2000 ", inProceedings of Taiwan VLSI Design/CAD Symposium 2001, section C1-10, August 2001.These designs all can not be satisfied the needs of many high-end mobile devices (as digital camera) on speed, area and the power consumption of chip, therefore the VLSI to the MQ encoder still needing to realize further research.
Summary of the invention
The objective of the invention is to propose a kind of high-speed low-power-consumption MQ encoder of the JPEG2000 of being applicable to standard, to satisfy the needs of many high-end mobile multimedia equipment.
The high-speed low-power-consumption MQ encoder of the JPEG2000 standard that is applicable to that the present invention proposes, at first under the on all four prerequisite of compression result of assurance and JPEG2000 standard, MQ encryption algorithm in the JPEG2000 standard has been carried out corresponding improvement and abbreviation, realized with the high efficiency low-power consumption that adapts to hardware; Based on improving algorithm, adopt the parallel circuit structural design MQ encoder of three grades streamline, then with further raising coding rate.
The cataloged procedure of the MQ encoder that the present invention proposes can be divided into probability Estimation, interval calculation, interval reformation and exchange, 4 key steps of byte output, and initialization and ending (FLUSH).The present invention is under the prerequisite of the compression result that does not change the JPEG2000 standard, interval calculation quite loaded down with trivial details in the JPEG2000 standard and differentiation flow process (are comprised totally five subprograms such as CODE0/CODE1, CODELPS/CODEMPS, see the JPEG2000 standard for details: ISO/IEC 15444-1:JPEG 2000 image coding system, 2000, FinalCommittee Draft Version 1.0) improve, abbreviation is a differentiation/execution in step (see figure 6).That is: if data D to be compressed is the small probability symbol, and at interval A more than or equal to the probability Qe of the small probability symbol of twice; Data D perhaps to be compressed is big probability symbol, and A is less than the probability Qe of the small probability symbol of twice at interval, and then A is Qe at interval, and starting point C is constant.Otherwise A is that original interval A deducts Qe at interval, and starting point C is that original starting point C adds Qe.So just reduce the complexity of hardware, reduced power consumption.
The present invention quickens " the interval reformation " and " byte output " process in order to improve the processing speed of MQ encoder." the interval reformation " and " byte output " in the JPEG2000 standard are flow process (see figure 7)s that circulation is carried out.Each register A and register C move to left one (multiply by 2), till interval A is more than or equal to 0.75.When having moved 8 (CT=0), byte of output from register C.This shows that if the value among the register A very little (minimum may be 0.0000000000000001), then needing to circulate many times just may be more than or equal to 0.75 (circulating at most 15 times), such arithmetic speed is too low.Therefore, the present invention has adopted a kind of interval accelerating algorithm of reforming, and as shown in Figure 8, at first judges interval A in order to reach " more than or equal to 0.75 and less than 1.5 " required figure place L that moves to left, then with register A and all disposable L position that moves to left of register C.Need not circulation like this, once just can finish the output of interval reformation and maximum two bytes, improved the processing speed of MQ encoder greatly, further reduced power consumption.
The present invention has proposed the parallel circuit structure of corresponding three class pipeline, with the further coding rate that improved according to above improvement and the abbreviation that the MQ encryption algorithm is carried out.This structure is divided into three parts with whole M Q encoder: " probability Estimation and condition exchange " module 91, " interval calculating and reformation " module 92 and " byte output " module 93 (seeing Fig. 9 for details).
" probability Estimation and condition exchange " module 91 comprises not only readable but also can write 911, one only readable probability Qe tables 912 of register file (RegisterFile), and a probability Qe register 913 and a SMB register 914.The MPS (CX) of register file 911 every behavior 1bit and the Index (cx) of 6bit, totally 19 CX are so register file 911 sizes are 19 * 7bit.Qe shows the NLPS of NMPS, 6bit of Qe, 6bit of every behavior 16bit and the SWITCH of 1bit, has 47 states, so Qe table 912 size is 47 * 29bit.The CX of outside input selects I (CX) and MPS (CX) from register file, I (CX) has from Qe shows and selects Qe, NMPS, NLPS and SWITCH then.Expression D is big probability or small probability behind the D of outside input and MPS (CX) XOR.When effective clock when arriving, I (CX), MPS (CX) and probability Qe register 913 and SMB register 914 obtain upgrading.Here, SMB register 914 is the sign test bit register.
" interval calculate with reform " module 92 comprises CT register 926, interval register A 927 and the input data attribute register 928 of one " zero is counted decoder " 921, two shift unit able to programme 922, home location register C 923, a most-significant byte buffer BH924, low eight digit buffer BL925, control displacement." interval calculating and reformation " module 92 is that big probability symbol or small probability symbol carry out interval calculating according to probability Qe and the D of low code data D, and at interval the result of calculation of A calculate from left end by " zero is counted decoder " 921 until first total till 1 what are individual continuous 0, promptly pass through Calculate and make the required figure place that moves to left in 0.75≤A<1.5; Then by " shift unit able to programme " 922 with interval register A927 and the disposable position that moves on to of home location register C923, obtain new interval A and starting point C; If data output is arranged, then deposit among two 8 the buffer BH924 and BL925, BL is the code word that is used for guaranteeing can not occurring in the output code flow between FF90h~FFFF, because this is the scope of the defined identifier of JPEG2000 standard; Simultaneously, CT register 926 changes plus coujnt into by original subtraction counting, and carry digit CT is that 6 bit complements are represented, initial value is-4 (111100); When CT is timing, the BYTE number (0/1/2) of the Senior Three bit representation of CT in anterior bumper BH924 and buffer BL925, low three (scope is 0~7) of CT represented the BIT number that shifts out among the register C.
" byte output " module 93 comprises that the width of two 8 data register DL931 and DH932 and expression byte output number is 2 register number933.If " interval calculating and reformation " module 92 has new data to produce, then with the data among buffer BH924 and BL925 inputs data register DL931 and DH932, and with CT[4:3] figure place (may be 0,1,2) the input register number933 of the dateout of expression.
Data of the present invention are input as: the contextual CX of data to be encoded D, expression D, and two prop signal of expression input data attribute, represent 4 states of importing data.If D, the CX of input are valid data, the state of then importing data accordingly is normal; Otherwise be invalid.When the MQ end-of-encode, need add state of termination over1 and the over2 of two clock cycle, carried out necessary ending process flush in the MQ coding flow process.And necessary initiating process initial resets or carries out during over2 in Circuits System in the MQ coding flow process.
Description of drawings
Fig. 1 shows the input and output of MQ encoder.
Fig. 2 shows MQ coding flow process.
Fig. 3 shows the interval reformation schematic diagram in the MQ coding flow process.
Fig. 4 shows the MPS/LPS condition exchange schematic diagram in the MQ coding flow process.
Fig. 5 indicating probability is estimated the tissue and the migration schematic diagram of finite state machine automatically.
Fig. 6 shows the interval calculation flow process behind the abbreviation.
Fig. 7 shows interval reformation and the byte output flow chart that the circulation in the JPEG2000 standard is carried out.
Fig. 8 shows that quicken to reform in the interval of adopting the improvement algorithm and multibyte output schematic diagram.
Fig. 9 shows the three class pipeline parallel organization circuit diagram of MQ encoder.Wherein, 91 is " probability Estimation and condition exchange " module, and 92 is " interval calculating and reformation " module, and 93 is " byte output " module.In " probability Estimation and condition exchange " module 91,911 is register file (RegisterFile), and 912 is an only readable probability Qe table, and 913 is a probability Qe register, and 914 is a SMB register; In " interval calculating and reformation " module 92,921 is " zero is counted decoder ", 922 is two shift units able to programme, 923 is home location register C, 924 is high 8 buffer BH, and 925 are low eight digit buffer BL, and 926 is the CT register, 927 is interval register A, and 928 are input data attribute register; In " byte output " module 93,931,932 is two 8 data register DL and DH, and 933 width for expression byte output number are 2 register number.
Figure 10 shows that the MQ encoder is based on the utilization in the digital image compression coded system of JPEG2000.
Figure 11 shows the sequential chart of MQ encoder in the JPEG2000 coded system.
Below in conjunction with JPEG2000 digital image compression coded system the present invention is described in further detail.
The structured flowchart of JPEG2000 encoder at first carries out preliminary treatment to source image data as shown in figure 10, comprises color space transformation, image segmentation (tiling) and deducts three processes of flip-flop (DC-shift); Then each " image sheet " (tiling) carried out wavelet transform DWT, purpose is that the energy major part is focused on low frequency sub-band, and the vast zone of high-frequency sub-band can occur a lot of 0 or absolute value very little, be convenient to the further compressed image of EBCOT encoder of back like this.Again the wavelet coefficient after the conversion is carried out the EBCOT coding by code block (code-block), purpose is in order to allow wavelet coefficient successively quantize by " importance ", corresponding point of cut-off is provided, and with wavelet coefficient by the probabilistic classification that may become " importance ", to improve the compression efficiency of back MQ encoder.Then to " bit plane " through context (CX) classification the carrying out MQ coding that the symbol D of EBCOT coding gained provides according to EBCOT, to eliminate or to reduce the comentropy redundancy of image, further improve compression ratio.At last through optimizing the output code flow of tissue back formation standard.
Improvement algorithm of the present invention verifies that by MATLAB corresponding circuit carries out the description of RTL level with the Verilog language, and emulation in Verilog-XL.
The sequential of the present invention in the JPEG2000 coded system as shown in figure 11.
The present invention has adopted SMIC 0.18u CMOS1P4M technological standards cell library, by DESIGN-COMPILER comprehensive after, finish placement-and-routing by the APOLLO instrument.
With STAR-RC to this layout extraction RC parameter to the .spef file, be converted to the .sdf file again, the net table that reactionary slogan, anti-communist poster is gone into after comprehensive carries out the domain post-simulation, carries out Time-Series analysis and power consumption analysis with PRIME-TIME and PRIME-POWER respectively then, the result is as follows:
(1) processing speed of the present invention:
Main clock frequency of the present invention reaches as high as 200MHz, and disposal ability is 1Data/Cycle, i.e. 200M Data/Sec; And document H.H.Chen, C.J.Lian, K.F.Chen, L.G.Chen, " Contextbased Adaptive Arithmetic Encoder Design for JPEG2000 ", in Proceedings of Taiwan VLSI Design/CAD Symposium 2001, section C1-10, the disposal ability of the MQ encoder among the August 2001. only is 100M Data/Sec.
(2) chip area of the present invention:
Random logic of the present invention is 8663, and chip area is about 0.1mm 2Document H.H.Chen, C.J.Lian, K.F.Chen, L.G.Chen, " Contextbased Adaptive Arithmetic Encoder Design for JPEG 2000 ", in Proceedings of Taiwan VLSIDesign/CAD Symposium 2001, section C1-10, the random logic of the MQ encoder among the August2001. is 11000.
(3) power consumption of the present invention:
The present invention is 1.8v at supply voltage, and dominant frequency is that the average power consumption under the situation of 100MHz is about 7.3mW.

Claims (3)

1, a kind ofly is applicable to the high speed of JPEG2000 standard, the coding method of low-power consumption MQ encoder, be divided into initialization, probability Estimation, interval calculation, interval reformation and exchange, byte output and 6 steps that end up, it is characterized in that not changing under the compression result prerequisite of JPEG2000 standard, with interval calculation in the JPEG2000 standard and differentiation flow process abbreviation is a differentiation and execution in step: if data D to be compressed is the small probability symbol, and interval A is more than or equal to the probability Qe of the small probability symbol of twice; Data D perhaps to be compressed is big probability symbol, and A is less than the probability Qe of the small probability symbol of twice at interval, and then A is Qe at interval, and starting point C is constant; Otherwise A is that original interval A deducts Qe at interval, and starting point C is that original starting point C adds Qe.
2, the coding method of MQ encoder according to claim 1, it is characterized in that " the interval reformation " and " byte output " process in the JPEG2000 standard are quickened: at first judge interval A in order to reach " more than or equal to 0.75 and less than 1.5 " required figure place L that moves to left, then will interval A and all disposable L position that moves to left of starting point C.
3, a kind of high speed that is applicable to the JPEG2000 standard, low-power consumption MQ encoder based on claim 1 and 2 described coding methods, it is characterized in that adopting the circuit structure of three grades of flowing water, comprise three parts: " probability Estimation and condition exchange " module (91), " interval calculating and reformation " module (92) and " byte output " module (93), wherein:
" probability Estimation and condition exchange " module (91) comprises not only readable but also can a write register file (911), an only readable probability Qe table (912), and the register of a probability Qe (913) and a SMB register (914), SMB register (914) is the sign test bit register here;
" interval calculating and reformation " module (92) comprises " zero is counted decoder " (921), two shift units able to programme (922), a home location register C (923), most-significant byte buffer BH (924), low eight digit buffer BL (925), CT register (926), interval register A (927) and input data attribute register (928); " interval calculating and reformation " module (92) is that big probability symbol or small probability symbol carry out interval calculating according to probability Qe and the D of low code data D, and at interval the result of calculation of A calculate from left end by " zero is counted decoder " (921) until first total till 1 what are individual continuous 0, promptly pass through Calculate and make the required figure place that moves to left in 0.75≤A<1.5; Then by " shift unit able to programme " (922) with interval register A (927) and the disposable position that moves on to of home location register C (923), obtain new interval A and starting point C; If data output is arranged, then deposit among two 8 the buffer BH (924) and BL (925), simultaneously, CT register (926) is counted by original subtraction and is changed plus coujnt into; Number CT adopts 6 bit complements to represent in the CT register (926), and initial value is-4; When CT is timing, the BYTE number of the Senior Three bit representation of CT in anterior bumper BH (924) and buffer BL (925), the bit number that shifts out among the low three bit representation register C (923) of CT, the CT register is for controlling shift register here,
" byte output " module (93) comprises two 8 data register DL (931) and 2 register number (933) of DH (932) and expression byte output number; If " interval calculating and reformation " module (92) has new data to produce, then with the data among buffer BH (924) and the BL (925) inputs data register DL (931) and DH (932), and with CT[4:3] the figure place input register number (933) of the dateout represented.
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CN102088607B (en) * 2011-02-28 2014-06-18 西安电子科技大学 Memory quotient (MQ) coding method and circuit based on JPEG (joint photographic experts group) 2000 standard
CN102340316A (en) * 2011-09-07 2012-02-01 上海大学 FPGA (Field Programmable Gate Array)-based micro-space oversampling direct-current balance serial deserializer
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