CN103491375A - JPEG compression system based on bin DCT algorithm - Google Patents
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Abstract
The invention discloses a JPEG compression system based on a bin DCT algorithm. The key improvement of the JPEG compression system lies in a compression algorithm, and the adopted algorithm is a newly-developed bin DCT algorithm. In the algorithm, all the coefficients are in the binary system and all the multiplication is replaced into shift and addition operation so that the algorithm can be achieved more easily and faster through hardware and software. The complexity of DCT conversion is reduced through the binary DCT algorithm; compared with a traditional algorithm, the JPEG compression system has the advantages that the compression ratio of images is increased at the cost of certain image quality, and thus the JPEG compression system can be widely applied to various wireless multimedia sensor network systems similar to wireless head monitoring systems.
Description
Technical field
The present invention relates to a kind of image compression system, be specifically related to a kind of low expense towards wireless sense network, high compression rate and the JPEG compressibility based on the binDCT algorithm.
Background technology
From the sixties in 20th century, along with electronic technology and computer technology improving constantly and universal, the Applied Digital method is carried out image processing (Digital Image Processing) and has been entered the high-speed developing period.The digitized processing of image means to make picture signal to transmit in high quality, and is convenient to retrieval, analysis, processing and the storage of image.But the expression of digital picture needs a large amount of data spaces, thereby must carry out data compression coding.
Through the basic research of more than 30 years, image compression encoding research entered new period from beginning of the nineties late 1980s.Enter into practical research on the one hand, continue on the other hand to go deep into theoretical research.
The research of practical aspect concentrates on International Standards Organization and the ITU of International Telecommunications Union combines on several standards of formulation, has effectively promoted practical development.Formed draft in 1988, the ITU-TH.261 suggestion that nineteen ninety passes through, be that Image Compression Coding Technology moves towards practical essential step, and it is the knot product of 40 years achievements in research of image compression encoding.The standard of the international compressed encoding of a series of images has been proposed after entering the nineties in succession.The mixed coding technology that these suggestions generally adopt is the most practical current high efficient coding method, has obtained propagation and employment widely.The development trend of Image Compression is: algorithm is more complicated, compression ratio is higher, the compression ratio of JPEG is in the l:20 left and right, the compression ratio of JPEG2000 will be l:200 or higher, and the MPEG compression standard is also through the several generations development, from MPEG-1 to MPEG-2, MPEG-4 till now, compression algorithm becomes increasingly complex, and operand is increasing, and compression ratio is also more and more higher.
Wireless multimedia sensor network (WMSN) is the novel sensor network with multimedia messages perceptional functions such as audio frequency, video, images grown up on the basis of traditional wireless sensor networks (WSN).In radio multimedia sensor network, have a JPEG IP kernel of processing efficiently video flowing very important.
In the environment of wireless multi-hop, unpressed original video stream needs great bandwidth.Therefore, clearly for multimedia sensor network, need effective lossless compressiong.Traditional be applied to wireless and wired video coding technique and be based on and by source encoder, adopt statistical method to reduce bit to produce speed.For reaching this purpose, encoder reduces the redundant information in a frame by compress technique in frame, also has employing inter-frame compression techniques (also referred to as predictive coding or estimation) to reduce the redundant information between shaking continuously simultaneously.
To the research of jpeg coder, be mainly to concentrate on these aspects in the world: compression algorithm is improved, the heavy framework of restructural chip and IP kernel.Dynamic reconfigurable allows selectively to substitute some logical block when operation, in order to improve the area utilization of FPGA.Method about the restructural chip.Generally be based on mixed hardware/software architecture.The application component of computation-intensive wherein is mapped in specific hardware-core.These kernels distribution FPGA resource on the same stage.And remainingly by software, realized.Reduce more area in the mode of sacrificing a small amount of performance by this method.The encoder of realizing exactly low expense by the framework of revising IP kernel is arranged again, for example Qihui Zhang mentions a kind of new framework mode, divide other part to allow two one dimension continuous transformation processions to decompose the utilization of two-dimensional dct computing module, result internal memory transposition parallel with in the middle of it, can reach higher running frequency, and, by extra SIPO, PISO and register bank realize.
But the study hotspot of current JPEG is optimized processor speed and obtains high-quality image.The low expense of this kind of design and wireless sense network and image high compression rate require to run counter to, and these methods have higher complexity, realize comparatively complicated.
Summary of the invention
The object of the invention is to provide a kind of JPEG compressibility based on the binDCT algorithm for the existing deficiency of prior art, and it has solved the problems such as the little compressible of current image compression system, high expense and high complexity.
In order to solve these problems of the prior art, technical scheme provided by the invention is:
A kind of JPEG compressibility based on the binDCT algorithm, described JPEG compressibility comprises binDCT module, Zigzag module, quantization modules, coding module and controller module, in system work process,
The binDCT module, according to the binDCT algorithm, is carried out the binDCT conversion by 8 * 8 data blocks of input, and will be exported data and send into the Zigzag module;
By the matrix after the conversion of input, the order according to Zigzag rearranges in the Zigzag unit, then will export data and deliver to quantization modules;
Quantization modules will be exported the matrix reciprocal that data are multiplied by quantization matrix, data be inputed to coding module after completing quantification;
It is DC component and alternating current component that coding module is exported Data Division by quantization modules, and DC component and alternating current component are adopted to different coded systems, completes respectively differential coding and variable-length encoding and moisture in the soil coding; Control module is responsible for producing logic control signal and the timing control signal of all modules, finally coded data is exported.
For technique scheme, the inventor also has further optimization embodiment.
As optimization, the binDCT module adopts the binDCT matrix when view data is carried out to discrete cosine transform, all multiply operations of dct transform are transformed to displacement and add operation, the binDCT module using data every eight as one group, after advanced every trade conversion, then be listed as variation, after completing one-dimensional transform, carry out again two-dimensional transform, finally complete the binDCT conversion.
As optimization, the Zigzag module has adopted two ram, and adopting ping-pong operation, the processing of ping-pong operation is mainly that input traffic is assigned in data buffer zone zigram0 and zigram1 during by input data selection unit etc.
Further, at first the Zigzag module arrives zigram0 by the data flow cache of input, then by the input data selection, switched, and the data flow cache of input is arrived to zigram1, meanwhile, also will the selection by output data selection unit by the data of zigram0, deliver to quantization modules and processed; The switching again by the input data selection unit the 3rd cycle more afterwards, by the data flow cache of input, to zigram0, meanwhile, the switching by output data selection unit by the data of zigram1 again, deliver to quantization modules and processed; So circulation, go round and begin again.
As optimization, the quantizer of quantization modules constantly produces address signal, read quantization parameter from the quantization parameter table, the quantization parameter table comprises the quantization parameter table of depositing brightness signal Y and two quantization parameter tables of carrier chrominance signal UV, what in the quantization parameter table, deposit is the inverse of corresponding quantization step, and quantization modules directly multiplies each other binDCT coefficient and the quantization parameter read.
As optimization, coding module is DC component and AC component by Data Division; Wherein the DC value adopts the mode of differential coding, there will be a large amount of continuous zero through the AC data after quantizing, to AC Run-Length Coding (RLE) for data, a large amount of zero just can mean by fewer data, reduce the bit number used, then the AC data are carried out to the VLC coding, according to the size of VLI code, carry out Huffman encoding, and the AC component carries out the VLC coding, according to size and the run length of the VLC code of AC coefficient, check in corresponding Huffman code from the Huffman code table
Control whole coding as the optimal controller module for by the user, inputting 8 registers, set quantization table and the Huffman table that the MCU form of input picture and quantity, each component are corresponding and produce that coding starts and stop signal etc. by the user, whole cataloged procedure is carried out to sequential and logic control.
With respect to scheme of the prior art, advantage of the present invention is:
JPEG compressibility emphasis based on binDCT described in the invention improves aspect compression algorithm, and the algorithm of employing is emerging binDCT algorithm.In this algorithm, all coefficients are that binary system and all multiplication are replaced as displacement and add operation, therefore can more simply and by hardware and software, realize fast.Reduced the complexity of DCT conversion by binary system DCT algorithm, simultaneously relative traditional algorithm, the present invention is usingd and is sacrificed certain picture quality as cost, improves the compression ratio of image, thereby can extensive use and similar in the various radio multimedia sensor network systems such as the end of a thread monitoring.
The accompanying drawing explanation
Below in conjunction with drawings and Examples, the invention will be further described:
The general structure schematic diagram of the JPEG compressibility that Fig. 1 is the embodiment of the present invention;
Fig. 2 is the binDCT matrix in the embodiment of the present invention;
Fig. 3 is the binDCT module frame chart in the embodiment of the present invention;
Fig. 4 is the picture element matrix input sequence in the embodiment of the present invention;
Fig. 5 is the Zigzag module frame chart in the embodiment of the present invention;
Fig. 6 is the quantization modules block diagram in the embodiment of the present invention;
Fig. 7 is the coding module block diagram in the embodiment of the present invention;
Fig. 8 is the huff module status machine frame figure in the embodiment of the present invention;
Fig. 9 is the pack module status machine frame figure in the embodiment of the present invention;
Figure 10 is the controller module block diagram in the embodiment of the present invention.
embodiment
Below in conjunction with specific embodiment, such scheme is described further.Should be understood that these embodiment are not limited to limit the scope of the invention for the present invention is described.The implementation condition adopted in embodiment can be done further adjustment according to the condition of concrete producer, and not marked implementation condition is generally the condition in normal experiment.
Embodiment:
The present embodiment has been described a kind of JPEG compressibility based on the binDCT algorithm, its general structure as shown in Figure 1, described JPEG compressibility comprises binDCT module, Zigzag module, quantization modules, coding module and controller module, in system work process
The binDCT module, according to the binDCT algorithm, is carried out the binDCT conversion by 8 * 8 data blocks of input, and will be exported data and send into the Zigzag module;
By the matrix after the conversion of input, the order according to Zigzag rearranges in the Zigzag unit, then will export data and deliver to quantization modules;
Quantization modules will be exported the matrix reciprocal that data are multiplied by quantization matrix, data be inputed to coding module after completing quantification;
It is DC component and alternating current component that coding module is exported Data Division by quantization modules, and DC component and alternating current component are adopted to different coded systems, completes respectively differential coding and variable-length encoding and moisture in the soil coding; Control module is responsible for producing logic control signal and the timing control signal of all modules, finally coded data is exported.
As mentioned above, whole JPEG compressibility is divided into two parts, and one is the compressed encoding part, and one is control section.The input data of compressed encoding part are initial data to be encoded, through binDCT module, Zigzag module, quantization modules, coding module, finally obtain final data; Control section be input as address and control inputs, be mainly the register of being convenient to configure the JPEG IP kernel, the Image Coding process is controlled, control section is last must export data.
Kernel variable in the binDCT module, the binDCT matrix as shown in Figure 2.By matrix is observed and can be found, the binDCT matrix has symmetric feature.Adopt coefficient C0-C11 to be replaced one kind of value, can be by matrix conversion.According to the algorithm of binDCT, whole binDCT conversion only need to and be shifted by addition and can realize, by the structure of whole binDCT module as shown in Figure 3.
The binDCT module comprises 7 modules.Wherein the dctctrl module is control module, is responsible for producing control signal, and mulh, selecth, tri-modules of sumh are carried out the horizontal binDCT conversion of one dimension to data, and mulv, selectv, tri-modules of sumv are carried out One-dimensional Vertical binDCT conversion to data.The plug-in ram that zigram0 and zigram1 are the zigzag module.The plug-in ram that dctram is the dct module.Mulv and mulh module are responsible for the pixel of input and the coefficient of binDCT coefficient matrix are multiplied each other.Due to what adopt, be complement arithmetic, therefore, by simple displacement and addition, the pixel value by all coefficients with input is multiplied each other.At first the input pixel is deducted to 128.Making the scope of input pixel between-128-128, is even function.What input is positive number, deducts after 128, and data may be negative, therefore when deducting 128, negative need to be converted to complement code.The pixel of input is input as eight simultaneously, in order to improve operational precision, need to carry out the position expansion to data, after last two-dimensional transform completes, then clips extension bits.
The Introduced cases pixel is inputted by 8 * 8 matrix one by one.The order of input is by the row input, and as shown in Figure 4, input sequence is X00, X01 ... X07 ... X70 ... X77.
The function of selcth and selcth is arranged mulh and the mulv result drawn that multiplies each other according to the order of matrix.The result that the responsible every row of sumh and sumv module multiply each other adds symbol, then carries out summation operation.The dctctrl module is responsible for producing the control signal of selcth, selctv, sumh and sumv module, produces the address signal of dctram simultaneously, completes the transposition of line translation result.The main input signal of dctctrl module is clock signal clk, synchronous initial signal strt.Input a pixel of each clock input by row.Dctctrl has completed the transposition to line translation simultaneously.Adopt respectively 4 three digit counters to realize address transition.Wherein ahh and ahl have formed the memh signal, and avh and avl have formed the memv signal, the address input and output signal that these two signals are respectively dctram.Because the memh signal is different with memv signal-count method, so writing address and the difference of reading address, transpose of a matrix completed.
The output data that are input as the binDCT module of Zigzag module.The present invention has adopted two ram, adopts ping-pong operation.The processing of ping-pong operation is mainly that input traffic is assigned in data buffer zone zigram0 and zigram1 during by input data selection unit etc.At first the data flow cache of input is arrived to zigram0, then, by the input data selection, switched, and the data flow cache of input is arrived to zigram1, meanwhile, also will the selection by output data selection unit by the data of zigram0, deliver to quantization modules and processed.Afterwards, then the switching again by the input data selection unit the 3rd cycle, by the data flow cache of input, to zigram0, meanwhile, the switching by output data selection unit by the data of zigram1 again, deliver to quantization modules and processed.So circulation, go round and begin again.The Zigzag module is divided into three parts, two zigram and a control signal generation module zigzag.The visible Fig. 5 of its block diagram.
Because the output data of binDCT module are not Y, but the transposition of Y, so the first step is to utilize the Zigzag module to carry out transposition to Y.Realize that transposition is very simple, utilize a counter x to be counted the input data, because the data input is inputted by row.Only the Senior Three position of x and the 3rd need to be put upside down, then be stored data, can be obtained the transposition of Y.Second step is the order generation read signal according to Zigzag by the Zigzag module.After image is carried out to the zigzag sequence, high fdrequency component is separated with low frequency component.Matrix can be obtained to quantized result divided by the quantization matrix defined in Joint Photographic Experts Group.
But, in hardware circuit, multiplication is more easily realized than division, and the hardware circuit expended still less.Therefore replace division with multiplication, replace the operation quantized, try to achieve the matrix reciprocal of quantization matrix.
Due to after asking down, coefficient is less, therefore by doubly rear storage of the coefficient magnify 2n of the coefficient matrix of storage.In this way, divide operations is converted to multiply operation.Due to quantization matrix corresponding to the different components of image, therefore solidify two quantization tables in the JPEG IP kernel, for different components, adopt different quantization tables to be quantized.Because coefficient amplifies, so the value of quantization table deposited two numerical value, and one is the number after amplifying, and one for amplifying 2
nn doubly.The visible Fig. 6 of the block diagram of quantization modules.F1 and f2 representative function in figure.Always have two functions in Fig. 6, the f1 major function is according to control signal, and the corresponding tabular value that quantizes, will quantize tabular value and be separated in advance, be separated into quantization table value of magnification and shift value sh.The output of zigzag module and quantification tabular value are input in the mul module, two numbers are multiplied each other, complete quantization operation.The value muli obtained is inputted into f2, according to the value of sh, carry out shifting function, right-shift operation, obtain original value ym.Again by ym input state machine 1, after being rounded to operation, this number delivers to output, the value after finally being quantized.
In coding module, for DC component and the AC component of data, adopt different coded systems.At first the DC component is carried out to differential coding, then result is carried out to variable-length encoding, the AC component is carried out to variable-length encoding simultaneously, finally carry out Huffman encoding.Finally complete the coding of all data, the data packing is output as to enc.Wherein Huffman encoding, employing be static Huffman table, be about to needed tabular value and be solidificated in IP kernel.Our module that all codings is relevant is placed in a total module.Because the processing of JPEG compression is processed according to one by one 8 * 8, then when inputting last processing block, needing a signal prompt be last piece, and this signal is the last signal.And the Huffman table that different components are corresponding different, therefore need a marker current color component.The visible Fig. 7 of the block diagram of coding module.
Component after quantizing inputs to and becomes module, and the len module is carried out differential coding to DC component wherein.The len module completes the Run-Length Coding to the differential coding of DC data and AC data.The difference value that the huff module completes the DC coefficient carries out the VLI coding, value to the AC coefficient is carried out the VLC coding, and the size according to DC coefficient VLI code, check in corresponding Huffman code from the Huffman code table, according to size and the run length of the VLC code of AC coefficient, check in corresponding Huffman code from the Huffman code table.Due to from huff module output valve indefinite length, therefore need the pack module to be packed.Finally the data fit Joint Photographic Experts Group in order to allow after encoding, need to add flag bit to data, and this function is completed by the aflag module.The store module mainly is responsible for the data that produce in the buffer memory cataloged procedure, gives the aflag module by data and is processed.
The len module has been mainly the differential coding of DC coefficient, and the ZRL in calculated data, and AC is carried out to variable-length encoding.In the len module, designed an asynchronous FIFO, in order to the buffer memory coded data.
The major function of huff module is the address of calculating the Huffman tabular value.Produce ZRL and EOB simultaneously.Whenever producing ZRL of output of continuous 16 0 coefficients.In order to obtain higher compression ratio, all ZRL codes are dropped with a single EOB and replace.Carry out the single clock coding for each data, and the ZRL code is pushed in a very shallow FIFO, if module terminates with 0 value, refresh and replaced by the EOB code.The Huffman value of extracting from the Huffman table passes to the pack module and is packed.
When carrying out Huffman encoding, need to process especially according to special circumstances, for example, when encoding finally or needing to insert the reboot flag position.Therefore at a state machine of inside modules design, simulated.The visible Fig. 8 of the block diagram of state machine.
Altogether having designed 6 kinds of states, is respectively waits, normal, padr, padf, restrt and flsh.Wherein the waits state is wait state, synchronously restart or asynchronously restart or clear signal effective the time in module, and be this state always., mean when the stuff module has data to be processed when not being empty as the FIFO of len module, enter the normal state.When initial register is designed to insert when restarting position, when the restart signal is effective, enter the padr state, prepare to insert the reboot flag position.After the padr state, insert the reboot flag position, enter the normal state after completing.In the normal state, if treated time last processing block, if the data that last coding obtains, less than 32, need to be carried out position and fill, meet the condition of byte-aligned, if, when therefore final_sig is 1, enter the padf state.After the padf state completes, need to supplement the EOB flag bit, enter the flsh state.
The pack module is packed the Huffman code value (hcode) after coding and the DC that calculates of len module and the value (fvalue) after the AC variable-length encoding, and the data that are packaged into 32 are exported.State machine main purpose in the pack module is to distinguish the reboot flag position to insert situation.The visible Fig. 9 of state machine diagram.
As seen from Figure 9, always have idle, restrt, flushc and flush1 one of four states.This state machine is that the position filling in order to insert restart flag bit and image ending is served.If asynchronous or synchronously reset or clear signal effective the time, be the idle state.In the idle state, if flush=1, when needing to carry out the end filling, enters the flush1 state.According to the size of corresponding remaining data, supplement the 0xf of corresponding size, until supply 32.The flush1 state enters the flushc state after finishing, and carries out continuous f and fills.When the idle state, if restart=1 enters the restrt state.Insert 32 extra bit data.After insertion, if flush=1 and dout_vldi=1 enter the flushc state; If flush=1 and dout_vldi=0, enter the flush1 state; If flush=0 and dout_vldi=1, enter the idle state, mean that the reatart flag bit inserts complete, enter normal encoding.
The function of aflag module is mainly to read from memory module 32 bit data and its flag bit, the outputting encoded data simultaneously that coding obtains.Its flag bit state passed through, the aflag module determines whether will expand to 0xff00 for the data of 0xff.Only have when this bit of 0xff and carry out not for flag bit the time.
The store module comprises the 4bit degree of depth, the FIFO of 36bit width.The flag bit byte of the data that comprise 4 bytes in each FIFO and 4bit.Because the final enc data that produce are 8 bit data, therefore 32 bit data of coming the buffer memory coding to produce with this FIFO.Can reading-white-writing data, do not produce and block up.
Controller module is reading out data from the register configuration of user's input, converts it to corresponding timing control signal and logic control signal.The visible Figure 10 of the block diagram of control module.In Figure 10, input signal is that din is the register configuration data that the user inputs, and the eover signal is from coding module.When completing, coding produces the eover signal.At first extract corresponding logic control signal output from input register.Obtain corresponding registers signal r1-r7 and control register group.Produce current color component signal col1 and its inhibit signal col2 and module control signal nextcomp, the colors component that the representative input is new simultaneously.Then by the corresponding Huffman table of color component selection, obtain Huffman table control signal colh.Finally according to colh signal and register configuration signal, select the input of corresponding current Huffman table hti as center module.Secondly, produce the control signal ncol of current color number of components.This signal is obtained to color component quantity colsel by the inquiry register.Again, change the counter mcucnt of mcu and mc into kernel enabling signal go and kernel stop signal stp.In figure, state is responsible for generating the state of control module.This state machine always has 7 states.Be respectively the encoding state ectrl_ende of idle condition ectrl_ewait, beginning encoding state ectrl_estart, first DCT encoding state ectrl_edctw1, second DCT encoding state ectrl_edctw2, second DCT encoding state delaying state ectrl_nx3w, normal encoding state ectrl_enc and last MCU.
If the go signal is effective, the kernel enabling signal effectively enters the beginning encoding state.If the en signal is effective, the en signal comes from coding module, when the FIFO of variable-length encoding non-NULL and less than the time effective.Enter first DCT encoding state.When en=1 and nx0=1 enter second DCT encoding state.Enter the ectrl_enx3w state in the time of en=1 again and nx0=1.In the time of en=1 and nx3=1, enter encoding state.When the finali signal is effective, enter last MCU encoding state.
Above-mentioned example is only explanation technical conceive of the present invention and characteristics, and its purpose is to allow the person skilled in the art can understand content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalent transformations that Spirit Essence is done according to the present invention or modification, within all should being encompassed in protection scope of the present invention.
Claims (7)
1. the JPEG compressibility based on the binDCT algorithm, is characterized in that, described JPEG compressibility comprises binDCT module, Zigzag module, quantization modules, coding module and controller module, in system work process,
The binDCT module, according to the binDCT algorithm, is carried out the binDCT conversion by 8 * 8 data blocks of input, and will be exported data and send into the Zigzag module;
By the matrix after the conversion of input, the order according to Zigzag rearranges in the Zigzag unit, then will export data and deliver to quantization modules;
Quantization modules will be exported the matrix reciprocal that data are multiplied by quantization matrix, data be inputed to coding module after completing quantification;
It is DC component and alternating current component that coding module is exported Data Division by quantization modules, and DC component and alternating current component are adopted to different coded systems, completes respectively differential coding and variable-length encoding and moisture in the soil coding; Control module is responsible for producing logic control signal and the timing control signal of all modules, finally coded data is exported.
2. the JPEG compressibility based on the binDCT algorithm according to claim 1, it is characterized in that, the binDCT module adopts the binDCT matrix when view data is carried out to discrete cosine transform, all multiply operations of dct transform are transformed to displacement and add operation, the binDCT module using data every eight as one group, after advanced every trade conversion, be listed as again variation, after completing one-dimensional transform, then carry out two-dimensional transform, finally complete the binDCT conversion.
3. the JPEG compressibility based on the binDCT algorithm according to claim 1, it is characterized in that, the Zigzag module has adopted two ram, adopting ping-pong operation, the processing of ping-pong operation is mainly that input traffic is assigned in data buffer zone zigram0 and zigram1 during by input data selection unit etc.
4. the JPEG compressibility based on the binDCT algorithm according to claim 3, it is characterized in that, at first the Zigzag module arrives zigram0 by the data flow cache of input, then by the input data selection, switched, and the data flow cache of input is arrived to zigram1, meanwhile, also will the selection by output data selection unit by the data of zigram0, deliver to quantization modules and processed; The switching again by the input data selection unit the 3rd cycle more afterwards, by the data flow cache of input, to zigram0, meanwhile, the switching by output data selection unit by the data of zigram1 again, deliver to quantization modules and processed; So circulation, go round and begin again.
5. the JPEG compressibility based on the binDCT algorithm according to claim 1, it is characterized in that, the quantizer of quantization modules constantly produces address signal, read quantization parameter from the quantization parameter table, the quantization parameter table comprises the quantization parameter table of depositing brightness signal Y and two quantization parameter tables of carrier chrominance signal UV, what in the quantization parameter table, deposit is the inverse of corresponding quantization step, and quantization modules directly multiplies each other binDCT coefficient and the quantization parameter read.
6. the JPEG compressibility based on the binDCT algorithm according to claim 1, is characterized in that, coding module is DC component and AC component by Data Division; Wherein the DC value adopts the mode of differential coding, there will be a large amount of continuous zero through the AC data after quantizing, to AC Run-Length Coding (RLE) for data, a large amount of zero just can mean by fewer data, reduce the bit number used, then the AC data are carried out to the VLC coding, according to the size of VLI code, carry out Huffman encoding, and the AC component carries out the VLC coding, according to size and the run length of the VLC code of AC coefficient, check in corresponding Huffman code from the Huffman code table.
7. the JPEG compressibility based on the binDCT algorithm according to claim 1, it is characterized in that, controller module is controlled whole coding for by the user, inputting 8 registers, set quantization table and the Huffman table that the MCU form of input picture and quantity, each component are corresponding and produce that coding starts and stop signal etc. by the user, whole cataloged procedure is carried out to sequential and logic control.
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| CN103957426A (en) * | 2014-04-11 | 2014-07-30 | 河海大学 | RGB565 true color image lossy compression and decompression method |
| CN110659014A (en) * | 2018-06-29 | 2020-01-07 | 赛灵思公司 | Multiplier and neural network computing platform |
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